From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by sourceware.org (Postfix) with ESMTPS id 673B838515C7 for ; Mon, 23 May 2022 19:38:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 673B838515C7 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-wm1-x32e.google.com with SMTP id r6-20020a1c2b06000000b00396fee5ebc9so179648wmr.1 for ; Mon, 23 May 2022 12:38:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=hy5wSo1mJuahiMPX9zoJMyBVWBleWJpGAH9cl+W2DSk=; b=Twj8a9sykY6NeYm6hsNGvWMpKUYYXrrm32+bBDk2djZGbnkjrvpJj/Zgl6Gs5v6uab +qc+P73Dg56ZNLTP9cdEbjqobDbg4ujCI5zvQq9JNuJX6UYt/jf9GVtiLiF850T+SK8D kUdkRY4qEn9JFvwUxd3H2vOn3XAnZUe4pkhyRrE8tYA4fQooQe0NhMKjDv+aOJxlilBG ieyz9tyNPc1TpBpEuDXYOO6AXLjSIgD0hevHywHrXQZdanmZCwnnakLQyh9wXV7H/+Zs cVe+dmGiV7zhdnEW1YR0z3wNp6gzzRw2fwC9FjsZEDpyFalp+36LP/SrN/lKFBG3hhYQ X7og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=hy5wSo1mJuahiMPX9zoJMyBVWBleWJpGAH9cl+W2DSk=; b=xWjGzxmODc66jDTkHrxJufeS01NBmf7GVWlohDRCyRxTj0LLVsKyeNHMbTAXEmlnFb eBvt8SpZUz0iYHQTeaK5pDcWBDM02mkZE55yDMuIqnGcrlXMCZKYiI+zRvyyZbmwbvO0 3TewLPQgTXyOZrfLeWHX+GucyvmhZiZeL9xI5sO4G6cBuBQ+DFFEAqOUEWRlgvQJF0JT EYmnBtBpGpm16m5835OOSduAqMMoBjPM7XUEV2/mynmtA61hEk24LL8KeWNmOAncdG5I NFzOPZum28ReP/h4op6XZfB5GN7NUAmoWg3+Jm/EMwP0ht69K72YuZf+cc6Jf6qH84sG 5wng== X-Gm-Message-State: AOAM533iEikBrQ1MloVRz2GleYDz1cUXukFWD9fSRJj1kT/f7bFgE1WL cX5bKd2HriwyUU7KGi5l7JJbUM8l0CMQUyxoI2NRrw== X-Google-Smtp-Source: ABdhPJz0/2MMr7cpp2dKBFEuxFJjb3lkDsNApgbKEgUgdKd80wNeBHz2Uu2YWe8sHEW7jml+tvpwH54wKN66MNdRSCw= X-Received: by 2002:a05:600c:511a:b0:397:50b9:f5be with SMTP id o26-20020a05600c511a00b0039750b9f5bemr539379wms.188.1653334681826; Mon, 23 May 2022 12:38:01 -0700 (PDT) MIME-Version: 1.0 References: <20220523181209.2208136-1-vineetg@rivosinc.com> In-Reply-To: <20220523181209.2208136-1-vineetg@rivosinc.com> From: Philipp Tomsich Date: Mon, 23 May 2022 21:37:51 +0200 Message-ID: Subject: Re: [PATCH] [PR/target 105666] RISC-V: Inhibit FP <--> int register moves via tune param To: Vineet Gupta Cc: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, Palmer Dabbelt , =?UTF-8?Q?Christoph_M=C3=BCllner?= , gnu-toolchain@rivosinc.com, Andrew Waterman X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, HTML_MESSAGE, JMQ_SPF_NEUTRAL, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 May 2022 19:38:06 -0000 Good catch! On Mon, 23 May 2022 at 20:12, Vineet Gupta wrote: > Under extreme register pressure, compiler can use FP <--> int > moves as a cheap alternate to spilling to memory. > This was seen with SPEC2017 FP benchmark 507.cactu: > ML_BSSN_Advect.cc:ML_BSSN_Advect_Body() > > | fmv.d.x fa5,s9 # PDupwindNthSymm2Xt1, PDupwindNthSymm2Xt1 > | .LVL325: > | ld s9,184(sp) # _12469, %sfp > | ... > | .LVL339: > | fmv.x.d s4,fa5 # PDupwindNthSymm2Xt1, PDupwindNthSymm2Xt1 > | > > The FMV instructions could be costlier (than stack spill) on certain > micro-architectures, thus this needs to be a per-cpu tunable > (default being to inhibit on all existing RV cpus). > > Testsuite run with new test reports 10 failures without the fix > corresponding to the build variations of pr105666.c > > | === gcc Summary === > | > | # of expected passes 123318 (+10) > | # of unexpected failures 34 (-10) > | # of unexpected successes 4 > | # of expected failures 780 > | # of unresolved testcases 4 > | # of unsupported tests 2796 > > gcc/Changelog: > > * config/riscv/riscv.cc: (struct riscv_tune_param): Add > fmv_cost. > (rocket_tune_info): Add default fmv_cost 8. > (sifive_7_tune_info): Ditto. > (thead_c906_tune_info): Ditto. > (optimize_size_tune_info): Ditto. > (riscv_register_move_cost): Use fmv_cost for int<->fp moves. > > gcc/testsuite/Changelog: > > * gcc.target/riscv/pr105666.c: New test. > > Signed-off-by: Vineet Gupta > --- > gcc/config/riscv/riscv.cc | 9 ++++ > gcc/testsuite/gcc.target/riscv/pr105666.c | 55 +++++++++++++++++++++++ > 2 files changed, 64 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/pr105666.c > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index ee756aab6940..f3ac0d8865f0 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -220,6 +220,7 @@ struct riscv_tune_param > unsigned short issue_rate; > unsigned short branch_cost; > unsigned short memory_cost; > + unsigned short fmv_cost; > bool slow_unaligned_access; > }; > > @@ -285,6 +286,7 @@ static const struct riscv_tune_param rocket_tune_info > = { > 1, /* issue_rate */ > 3, /* branch_cost */ > 5, /* memory_cost */ > + 8, /* fmv_cost */ > true, /* > slow_unaligned_access */ > }; > > @@ -298,6 +300,7 @@ static const struct riscv_tune_param > sifive_7_tune_info = { > 2, /* issue_rate */ > 4, /* branch_cost */ > 3, /* memory_cost */ > + 8, /* fmv_cost */ > true, /* > slow_unaligned_access */ > }; > > @@ -311,6 +314,7 @@ static const struct riscv_tune_param > thead_c906_tune_info = { > 1, /* issue_rate */ > 3, /* branch_cost */ > 5, /* memory_cost */ > + 8, /* fmv_cost */ > false, /* slow_unaligned_access */ > }; > > @@ -324,6 +328,7 @@ static const struct riscv_tune_param > optimize_size_tune_info = { > 1, /* issue_rate */ > 1, /* branch_cost */ > 2, /* memory_cost */ > + 8, /* fmv_cost */ > false, /* slow_unaligned_access */ > }; > > @@ -4737,6 +4742,10 @@ static int > riscv_register_move_cost (machine_mode mode, > reg_class_t from, reg_class_t to) > { > + if ((from == FP_REGS && to == GR_REGS) || > + (from == GR_REGS && to == FP_REGS)) > + return tune_param->fmv_cost; > + > return riscv_secondary_memory_needed (mode, from, to) ? 8 : 2; > } > > diff --git a/gcc/testsuite/gcc.target/riscv/pr105666.c > b/gcc/testsuite/gcc.target/riscv/pr105666.c > new file mode 100644 > index 000000000000..904f3bc0763f > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/pr105666.c > @@ -0,0 +1,55 @@ > +/* Shamelessly plugged off > gcc/testsuite/gcc.c-torture/execute/pr28982a.c. > + > + The idea is to induce high register pressure for both int/fp registers > + so that they spill. By default FMV instructions would be used to stash > + int reg to a fp reg (and vice-versa) but that could be costlier than > + spilling to stack. */ > + > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64g -ffast-math" } */ > + > +#define NITER 4 > +#define NVARS 20 > +#define MULTI(X) \ > + X( 0), X( 1), X( 2), X( 3), X( 4), X( 5), X( 6), X( 7), X( 8), X( 9), \ > + X(10), X(11), X(12), X(13), X(14), X(15), X(16), X(17), X(18), X(19) > + > +#define DECLAREI(INDEX) inc##INDEX = incs[INDEX] > +#define DECLAREF(INDEX) *ptr##INDEX = ptrs[INDEX], result##INDEX = 5 > +#define LOOP(INDEX) result##INDEX += result##INDEX * (*ptr##INDEX), > ptr##INDEX += inc##INDEX > +#define COPYOUT(INDEX) results[INDEX] = result##INDEX > + > +double *ptrs[NVARS]; > +double results[NVARS]; > +int incs[NVARS]; > + > +void __attribute__((noinline)) > +foo (int n) > +{ > + int MULTI (DECLAREI); > + double MULTI (DECLAREF); > + while (n--) > + MULTI (LOOP); > + MULTI (COPYOUT); > +} > + > +double input[NITER * NVARS]; > + > +int > +main (void) > +{ > + int i; > + > + for (i = 0; i < NVARS; i++) > + ptrs[i] = input + i, incs[i] = i; > + for (i = 0; i < NITER * NVARS; i++) > + input[i] = i; > + foo (NITER); > + for (i = 0; i < NVARS; i++) > + if (results[i] != i * NITER * (NITER + 1) / 2) > + return 1; > + return 0; > +} > + > +/* { dg-final { scan-assembler-not "\tfmv\\.d\\.x\t" } } */ > +/* { dg-final { scan-assembler-not "\tfmv\\.x\\.d\t" } } */ > -- > 2.32.0 > >