From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by sourceware.org (Postfix) with ESMTPS id BF09D3858D37 for ; Tue, 27 Dec 2022 19:52:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org BF09D3858D37 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ed1-x52c.google.com with SMTP id s5so20276460edc.12 for ; Tue, 27 Dec 2022 11:52:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=BM1t9Eo2Tk24mG9ffmBba+G0wg/uTnKNQPqE+07iEng=; b=bO5e1dhPeraWhbQeLIb/vlQBDp1pRRDX6r5dk0DCFJ7EXDzFc4ZgjtiG9OiEv7R0vi ZdLx4673+GwDQfRofDrupl5KCm0AJn4hKSh5nPnXglrjXP/RZTjsfl5JPwAlYuIBbvW0 r+mzP83Z/jwNkRNPleuA98AwYt6nuMH4imiV6rLKRR6dmCP6ZdFVQcLapKnkvvjwSH9N +BEvUiB0WdTi4HQni050O8W6RC/CogW2z/eq4ZTlUbhnCKgilBbzXTHXFgFjpmHpQbSF gLRQMRUwameYHpMU1FbANYsjvuW7gz2If69OlpYfmO4myQHSmU+4UmBcAQiP9hJ0i+Jd IQSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=BM1t9Eo2Tk24mG9ffmBba+G0wg/uTnKNQPqE+07iEng=; b=EqHLeBN2ILhfw3/CzQnxQPQo5fSQbZVDVfmmcUlCentWaEWfe5HxVFuDQDlOFKWFU1 wwMvNIa/KSSmCbTw0V1DmdpmziATYL/daPaY2u6VYZDpbfjc6LFFvCckywuRzYbxSRex HBKyXedIHemBMlc1GhprkysGj1Fk4T9PzjXwhQMghrPKJ79Yf900petVQvFJc+cLLSdV jCwtK0Fn5FUfhFP7gqfknanl4b018kESUVx7HbfL+E0w8EXgr8OdhmusCbdHjZqcQ0x2 +M05A3+7qyW5AB9UoXEnqEuQbY2JLPh80lzNS83bI+prjAm9NUGAbXqozi17wkae/Rg2 5mHg== X-Gm-Message-State: AFqh2koNXNDUkDq4uxiiPRBp+GFks6aKwioIZ7z1A7+iQG3x7PvSeqXq /HnnOy6J4Pz0N1nUuz6ZfGct0PC1BfinB5GLvv4VOg== X-Google-Smtp-Source: AMrXdXs2/CHcZYdxj70vctLgfdR3+9Ssd5EniTaHtG3srebroKDA4F2UbANzRh9qxPmqzXJfIbTgekZQNxUdfBZT3nc= X-Received: by 2002:a50:cc47:0:b0:461:b6a9:c5cb with SMTP id n7-20020a50cc47000000b00461b6a9c5cbmr2616171edi.148.1672170727620; Tue, 27 Dec 2022 11:52:07 -0800 (PST) MIME-Version: 1.0 References: <20221219010838.3878675-1-christoph.muellner@vrull.eu> <20221219010838.3878675-3-christoph.muellner@vrull.eu> In-Reply-To: From: Philipp Tomsich Date: Tue, 27 Dec 2022 20:51:56 +0100 Message-ID: Subject: Re: [PATCH v2 02/11] riscv: Restructure callee-saved register save/restore code To: Kito Cheng Cc: Christoph Muellner , gcc-patches@gcc.gnu.org, Jim Wilson , Palmer Dabbelt , Andrew Waterman , Jeff Law , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Content-Type: multipart/alternative; boundary="00000000000039512905f0d4964c" X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,HTML_MESSAGE,JMQ_SPF_NEUTRAL,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --00000000000039512905f0d4964c Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Applied to master (with the change from the reviews), thanks! Philipp. On Mon, 19 Dec 2022 at 07:30, Kito Cheng wrote: > just one more nit: Use INVALID_REGNUM as sentinel value for > riscv_next_saved_reg, otherwise LGTM, and feel free to commit that > separately :) > > On Mon, Dec 19, 2022 at 9:08 AM Christoph Muellner > wrote: > > > > From: Christoph M=C3=BCllner > > > > This patch restructures the loop over the GP registers > > which saves/restores then as part of the prologue/epilogue. > > No functional change is intended by this patch, but it > > offers the possibility to use load-pair/store-pair instructions. > > > > gcc/ChangeLog: > > > > * config/riscv/riscv.cc (riscv_next_saved_reg): New function. > > (riscv_is_eh_return_data_register): New function. > > (riscv_for_each_saved_reg): Restructure loop. > > > > Signed-off-by: Christoph M=C3=BCllner > > --- > > gcc/config/riscv/riscv.cc | 94 +++++++++++++++++++++++++++------------ > > 1 file changed, 66 insertions(+), 28 deletions(-) > > > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > > index 6dd2ab2d11e..a8d5e1dac7f 100644 > > --- a/gcc/config/riscv/riscv.cc > > +++ b/gcc/config/riscv/riscv.cc > > @@ -4835,6 +4835,49 @@ riscv_save_restore_reg (machine_mode mode, int > regno, > > fn (gen_rtx_REG (mode, regno), mem); > > } > > > > +/* Return the next register up from REGNO up to LIMIT for the callee > > + to save or restore. OFFSET will be adjusted accordingly. > > + If INC is set, then REGNO will be incremented first. */ > > + > > +static unsigned int > > +riscv_next_saved_reg (unsigned int regno, unsigned int limit, > > + HOST_WIDE_INT *offset, bool inc =3D true) > > +{ > > + if (inc) > > + regno++; > > + > > + while (regno <=3D limit) > > + { > > + if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) > > + { > > + *offset =3D *offset - UNITS_PER_WORD; > > + break; > > + } > > + > > + regno++; > > + } > > + return regno; > > +} > > + > > +/* Return TRUE if provided REGNO is eh return data register. */ > > + > > +static bool > > +riscv_is_eh_return_data_register (unsigned int regno) > > +{ > > + unsigned int i, regnum; > > + > > + if (!crtl->calls_eh_return) > > + return false; > > + > > + for (i =3D 0; (regnum =3D EH_RETURN_DATA_REGNO (i)) !=3D INVALID_REG= NUM; > i++) > > + if (regno =3D=3D regnum) > > + { > > + return true; > > + } > > + > > + return false; > > +} > > + > > /* Call FN for each register that is saved by the current function. > > SP_OFFSET is the offset of the current stack pointer from the start > > of the frame. */ > > @@ -4844,36 +4887,31 @@ riscv_for_each_saved_reg (poly_int64 sp_offset, > riscv_save_restore_fn fn, > > bool epilogue, bool maybe_eh_return) > > { > > HOST_WIDE_INT offset; > > + unsigned int regno; > > + unsigned int start =3D GP_REG_FIRST; > > + unsigned int limit =3D GP_REG_LAST; > > > > /* Save the link register and s-registers. */ > > - offset =3D (cfun->machine->frame.gp_sp_offset - sp_offset).to_consta= nt > (); > > - for (unsigned int regno =3D GP_REG_FIRST; regno <=3D GP_REG_LAST; re= gno++) > > - if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) > > - { > > - bool handle_reg =3D > !cfun->machine->reg_is_wrapped_separately[regno]; > > - > > - /* If this is a normal return in a function that calls the > eh_return > > - builtin, then do not restore the eh return data registers as > that > > - would clobber the return value. But we do still need to save > them > > - in the prologue, and restore them for an exception return, so > we > > - need special handling here. */ > > - if (epilogue && !maybe_eh_return && crtl->calls_eh_return) > > - { > > - unsigned int i, regnum; > > - > > - for (i =3D 0; (regnum =3D EH_RETURN_DATA_REGNO (i)) !=3D > INVALID_REGNUM; > > - i++) > > - if (regno =3D=3D regnum) > > - { > > - handle_reg =3D FALSE; > > - break; > > - } > > - } > > - > > - if (handle_reg) > > - riscv_save_restore_reg (word_mode, regno, offset, fn); > > - offset -=3D UNITS_PER_WORD; > > - } > > + offset =3D (cfun->machine->frame.gp_sp_offset - sp_offset).to_consta= nt > () > > + + UNITS_PER_WORD; > > + for (regno =3D riscv_next_saved_reg (start, limit, &offset, false); > > + regno <=3D limit; > > + regno =3D riscv_next_saved_reg (regno, limit, &offset)) > > + { > > + if (cfun->machine->reg_is_wrapped_separately[regno]) > > + continue; > > + > > + /* If this is a normal return in a function that calls the > eh_return > > + builtin, then do not restore the eh return data registers as > that > > + would clobber the return value. But we do still need to save > them > > + in the prologue, and restore them for an exception return, so = we > > + need special handling here. */ > > + if (epilogue && !maybe_eh_return > > + && riscv_is_eh_return_data_register (regno)) > > + continue; > > + > > + riscv_save_restore_reg (word_mode, regno, offset, fn); > > + } > > > > /* This loop must iterate over the same space as its companion in > > riscv_compute_frame_info. */ > > -- > > 2.38.1 > > > --00000000000039512905f0d4964c--