From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by sourceware.org (Postfix) with ESMTPS id 76F4D38582BC for ; Mon, 14 Nov 2022 23:00:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 76F4D38582BC Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lj1-x231.google.com with SMTP id l8so15281349ljh.13 for ; Mon, 14 Nov 2022 15:00:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=sUXgFXB7BVqAWci5zyPyAeikImRjqDm5QVKw6nqUJT8=; b=Kev4hTKYOx1VbuZSUMkZ9cLtbF1MMjrEwIfGyCsEmQtA3aApAH5kVPo1g7H+0IoPQs 2tkB1yFJxqoL8a2aa0AIviCzrHus+u/iA3ruLgWOPG+MaF6vylacTcY4LfGg+vATi5O6 CD0HDDh+xcPVI/daWYV6GML75lMG8Zs6OJJKZIxsVzaDQsBpnq8ZB803b3g4uMwlvb7S AfTQxLISY8SIjSpR34/35CS0qyhNZbRGw9wmzaEQ+LX4MOyvw+pHgsLM6nKg7Dsuqor2 mKRVxajEjYRIyKw5KxC+DwSYdvYJAOEpzqOeP+OFF0smQo3lgyBPsG4ZLsMTVC/Ybsar etZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sUXgFXB7BVqAWci5zyPyAeikImRjqDm5QVKw6nqUJT8=; b=uMOMxysWjpiQeu6hSrryKLJdSZ0aTEAoDgeLGPIwG2GhqAEXMINJzux/zrS64XRZAo 4IWwXSYM/sVGdmV3L6YYWNGZqIRHI9xCkhgUP5FTlfHfW6lcvW0kcAVHXo65qlXiSxA3 nJQ8DL2F3/6BOCQsoWS+sC/c8Y/HP2r9dL4fFgKyJGfKoWZEuGR+tbzawntuBNOn6n6w fZhSytMozlyKayghaP6jukWkqVn0zEzf+gfxCEXq7V+rtr109WbzKPaD0Ds0ssNGavPn SWgLXfph/m5wL8qeFiRLyA+0Th6ZzZivbA+hkln20ldftrAMVUZeiL97o9HWtBy5MND1 DG2w== X-Gm-Message-State: ANoB5pmyzgNqqIfcR82oZyP6VgDwVfYWJu+IsV3yw8JeQPnZgESn4n0Q DpbfCzyYYqareD/Fpz5yKfR7Em5u4aHouQ4BDTxcwA== X-Google-Smtp-Source: AA0mqf7raCsDNnz3gIF7WZomipT/++tg3lvkTVCLkGQBVzu/e/DgtY0r9q+E0785ZrtXU0jOv/aPRHSkU4t/DIqljhw= X-Received: by 2002:a2e:8052:0:b0:278:f5b8:82c8 with SMTP id p18-20020a2e8052000000b00278f5b882c8mr3415261ljg.228.1668466830679; Mon, 14 Nov 2022 15:00:30 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Philipp Tomsich Date: Tue, 15 Nov 2022 00:00:19 +0100 Message-ID: Subject: Re: [PATCH v2 0/2] Basic support for the Ventana VT1 w/ instruction fusion To: Palmer Dabbelt Cc: jeffreyalaw@gmail.com, gcc-patches@gcc.gnu.org, Vineet Gupta , jlaw@ventanamicro.com, Kito Cheng , christoph.muellner@vrull.eu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-3.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,JMQ_SPF_NEUTRAL,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, 14 Nov 2022 at 23:47, Palmer Dabbelt wrote: > > [Trying to join the threads here.] > > On Mon, 14 Nov 2022 13:28:23 PST (-0800), philipp.tomsich@vrull.eu wrote: > > Jeff, > > > > On Mon, 14 Nov 2022 at 22:23, Jeff Law wrote: > >> > >> > >> On 11/14/22 13:00, Palmer Dabbelt wrote: > >> > On Sun, 13 Nov 2022 12:48:22 PST (-0800), philipp.tomsich@vrull.eu w= rote: > >> >> > >> >> This series provides support for the Ventana VT1 (a 4-way superscal= ar > >> >> rv64gc_zba_zbb_zbc_zbs_zifenci_xventanacondops core) including supp= ort > >> >> for the supported instruction fusion patterns. > >> >> > >> >> This includes the addition of the fusion-aware scheduling > >> >> infrastructure for RISC-V and implements idiom recognition for the > >> >> fusion patterns supported by VT1. > >> >> > >> >> Note that we don't signal support for XVentanaCondOps at this point= , > >> >> as the XVentanaCondOps support is in-flight separately. Changing th= e > >> >> defaults for VT1 can happen late in the cycle, so no need to link t= he > >> >> two different changesets. > >> >> > >> >> Changes in v2: > >> >> - Rebased and changed over to .rst-based documentation > >> >> - Updated to catch more fusion cases > >> >> - Signals support for Zifencei > >> >> > >> >> Philipp Tomsich (2): > >> >> RISC-V: Add basic support for the Ventana-VT1 core > >> >> RISC-V: Add instruction fusion (for ventana-vt1) > >> >> > >> >> gcc/config/riscv/riscv-cores.def | 3 + > >> >> gcc/config/riscv/riscv-opts.h | 2 +- > >> >> gcc/config/riscv/riscv.cc | 233 ++++++++++++++= ++++ > >> >> .../risc-v-options.rst | 5 +- > >> >> 4 files changed, 240 insertions(+), 3 deletions(-) > >> > > >> > I guess we never really properly talked about this on the GCC mailin= g > >> > lists, but IMO it's fine to start taking code for designs that have > >> > been announced under the assumption that if the hardware doesn't > >> > actually show up according to those timelines that it will be assume= d > >> > to have never existed and thus be removed more quickly than usual. > >> Absolutely. I have zero interest in carrying around code for > >> nonexistent or dead variants. > >> > > >> > That said, I can't find anything describing that the VT-1 exists asi= de > >> > from these patches. Is there anything that describes this design an= d > >> > when it's expected to be available? > >> > >> What do you need? I can give some broad overview information on the > >> design, but it would likely just mirror what's already been mentioned = in > >> these patches. > >> > >> > >> As far as schedules. I'm not sure what I can say. I'll check on that= . > > I'm less worried about the "does this pipeline model match the HW" bits, > at least until the HW is publicly available then all we can do is rely > on the vendor (and even after the HW is public the vendor might be the > only one who cares enough to figure things out, nothing we can really do > upstream there). We've had some issues with nobody caring enough about > the C906 pipeline model to sort out whether some patches are a net win, > but if nobody (including the vendor) cares about the HW enough to > benchmark things then there's not much we can do. > > My bigger worry is getting roped in to supporting a bunch of hardware > that doesn't actually exist yet and may never make it outside some > vendor's lab. That can generally be a ton of work and filters > throughout GCC, even outside of the RISC-V backend. We've already got > enough chaos just trying to follow the ISA, chasing down issues related > to hardware that may not ever manifest is just going to lead to > craziness. > > So on my end the point of the schedule is to have something we can look > at and determine that the hardware is somehow defunct. The fairest way > we could come up with was to tie it to some sort of company announcement > of the hardware: obviously everyone knows their internal timelines, but > that's not fair to companies that don't employ someone with commit > access. Requirement some sort of public announcement means everyone has > the same rules to play by, IMO that's really important in RISC-V land as > there's so many vendors. > > >> It was never my intention to bypass any process/procedures here. So if= I > >> did, my apologies. > > > > The controversial part is XVentanaCondOps (as it is a vendor-defined > > extension), so I'll certainly hold off on that until both you and > > Palmer are in agreement on how to proceed there. > > The pipeline models are essentially in the same spot. We've got a bit > of a precedent there for taking them just based on an announcement, but > there isn't one here. > > [and the other side of the thread] > > On Mon, 14 Nov 2022 13:14:35 PST (-0800), philipp.tomsich@vrull.eu wrote: > > On Mon, 14 Nov 2022 at 21:58, Palmer Dabbelt wrot= e: > >> > >> On Mon, 14 Nov 2022 12:03:38 PST (-0800), philipp.tomsich@vrull.eu wro= te: > >> > On Mon, 14 Nov 2022 at 21:00, Palmer Dabbelt w= rote: > >> >> > >> >> On Sun, 13 Nov 2022 12:48:22 PST (-0800), philipp.tomsich@vrull.eu = wrote: > >> >> > > >> >> > This series provides support for the Ventana VT1 (a 4-way supersc= alar > >> >> > rv64gc_zba_zbb_zbc_zbs_zifenci_xventanacondops core) including su= pport > >> >> > for the supported instruction fusion patterns. > >> >> > > >> >> > This includes the addition of the fusion-aware scheduling > >> >> > infrastructure for RISC-V and implements idiom recognition for th= e > >> >> > fusion patterns supported by VT1. > >> >> > > >> >> > Note that we don't signal support for XVentanaCondOps at this poi= nt, > >> >> > as the XVentanaCondOps support is in-flight separately. Changing= the > >> >> > defaults for VT1 can happen late in the cycle, so no need to link= the > >> >> > two different changesets. > >> >> > > >> >> > Changes in v2: > >> >> > - Rebased and changed over to .rst-based documentation > >> >> > - Updated to catch more fusion cases > >> >> > - Signals support for Zifencei > >> >> > > >> >> > Philipp Tomsich (2): > >> >> > RISC-V: Add basic support for the Ventana-VT1 core > >> >> > RISC-V: Add instruction fusion (for ventana-vt1) > >> >> > > >> >> > gcc/config/riscv/riscv-cores.def | 3 + > >> >> > gcc/config/riscv/riscv-opts.h | 2 +- > >> >> > gcc/config/riscv/riscv.cc | 233 ++++++++++++= ++++++ > >> >> > .../risc-v-options.rst | 5 +- > >> >> > 4 files changed, 240 insertions(+), 3 deletions(-) > >> >> > >> >> I guess we never really properly talked about this on the GCC maili= ng > >> >> lists, but IMO it's fine to start taking code for designs that have= been > >> >> announced under the assumption that if the hardware doesn't actuall= y > >> >> show up according to those timelines that it will be assumed to hav= e > >> >> never existed and thus be removed more quickly than usual. > >> >> > >> >> That said, I can't find anything describing that the VT-1 exists as= ide > >> >> from these patches. Is there anything that describes this design a= nd > >> >> when it's expected to be available? > >> > > >> > I have to defer to Jeff on this one. > >> > >> Looks like you already committed it, though: > >> > >> 991cfe5b30c ("RISC-V: Add instruction fusion (for ventana-vt1)") > >> b4fca4fc70d ("RISC-V: Add basic support for the Ventana-VT1 core") > >> > >> We talked about this multiple times and I thought you were on board wi= th > >> the proposed "hardware needs to be announced" changes, did I > >> misunderstand that? > > > > Sorry =E2=80=94 I had assumed that the "basic support" changes were agr= eed > > upon between you and Jeff, given that Jeff had given the OK. > > If anything was agreed on we would have talked about it on publicly on > the mailing list, these are community-oriented decisions and need to be > made as such. It's true that sometimes folks talk outside the mailing > lists about these things, but we're pretty careful to reflect everything > back so everyone has a chance to be part of these discussions. > > > My position is still the same as discussed at LPC that "hardware needs > > to be announced". > > Even that hasn't been talked about on the mailing lists -- or really > even in any GNU toolchain related forum, we talked some about it some at > Plumbers for Linux and in private about GCC, but the takeaway there for > GCC was that you wanted to go talk to the Ventana folks to see if it was > OK with them. The mistake of making an assumption was mine, as I had again raised the issue with the Ventana folks (and particularly with Jeff) as recently as two weeks ago and read more into his "OK" than it was meant to mean. > Sounds like that just added to the confusion, though, so maybe we should > just have these discussion on the lists from now on? I'll stay with my assertion that some things are easier discussed off-list. However, taking them back to the appropriate mailing lists and larger groups (as we had done at LPC in the RISC-V MC) is the best way to summarize and ensure consensus. We need to go through the process of how this "announcement" happens once, so we have a blueprint for the future and no one resorts to assumptions next time. Let's get this done for the XVentanaCondOps merge between Jeff and the rest of us, so we have something that we can refer back to. Apologies again for the confusion, Philipp.