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From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: Jim Wilson <jimw@sifive.com>
Cc: GCC Patches <gcc-patches@gcc.gnu.org>, Philipp Tomsich <prt@gnu.org>
Subject: Re: [PATCH v1 2/2] RISC-V: Adjust predicates for immediate shift operands
Date: Mon, 16 Nov 2020 23:45:00 +0100	[thread overview]
Message-ID: <CAAeLtUAcKgxLO_L8J-ycaOPUPtFX8tVHV_7uwqNEUu+S6Lo85w@mail.gmail.com> (raw)
In-Reply-To: <CAFyWVabSM4JVBmCSRb7__p5GFRDJE52k4M+LwNGGw6OM=GDwnw@mail.gmail.com>

Jim,

On Mon, 16 Nov 2020 at 23:28, Jim Wilson <jimw@sifive.com> wrote:
>
> On Mon, Nov 16, 2020 at 10:57 AM Philipp Tomsich <philipp.tomsich@vrull.eu>
wrote:
>>
>> In case a negative shift operand makes it through into the backend,
>> it will be treated as unsigned and truncated (using a mask) to fit
>> into the range 0..31 (for SImode) and 0..63 (for DImode).
>
>
> This is a de-optimization.  This doesn't make any sense.  The ISA manual
clearly states the shift counts are truncated.  Some targets do this with
SHIFT_COUNT_TRUNCATED, but that is known to cause problems, so the RISC-V
port is doing it in the shift expanders.  I believe that other targets do
this too.

This is an de-optimization only, if applied without patch 1 from the
series: the change to VRP ensures that the backend will never see a shift
wider than the immediate field.
The problem is that if a negative shift-amount makes it to the backend,
unindented code may be generated (as a shift-amount, in my reading, should
always be interpreted as unsigned).

Note that with tree-vrp turned on (and patch 1 of the series applied), you
will see

.L3:
li a0,0

generated, anyway.

> Also, note that replacing
>   slli a0, a0, 31
> with
>   li a1, -1;
>   sll a0, a0, a1
> doesn't change the operation performed.  The shift count is still
truncated to 31, and so you get the exact same result from both code
sequences.  All you have done is make the code bigger and slower which is
undesirable.

I do agree that this does not address the issue of a shift that is wider
than the register width, even though it makes sure we reject this from the
immediate field.
That said: what is the correct behavior/result of this operation?

> Also note that the testcase has implementation defined results, so there
is no wrong answer here, and nothing wrong with what the RISC-V port is
doing.
>
>> +/* { dg-final { scan-assembler "sll" } } */
>
>
> I don't think that this will work as a grep for sll will also match
slli.  You would need to add a space or tab or maybe both to the search
string to prevent matches with slli.  Or alternatively use
scan-assembler-not "slli" which will match and fail for both slli and slliw.

Good catch. I turned this check around, but submitted the wrong one.

Thanks,
Philipp.

  reply	other threads:[~2020-11-16 22:45 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-16 18:57 [PATCH v1 1/2] Simplify shifts wider than the bitwidth of types Philipp Tomsich
2020-11-16 18:57 ` [PATCH v1 2/2] RISC-V: Adjust predicates for immediate shift operands Philipp Tomsich
2020-11-16 22:27   ` Jim Wilson
2020-11-16 22:45     ` Philipp Tomsich [this message]
2020-11-17 17:06       ` Jim Wilson
2020-11-16 22:38 ` [PATCH v1 1/2] Simplify shifts wider than the bitwidth of types Jim Wilson
2020-11-16 22:59   ` Philipp Tomsich
2020-11-16 23:38 ` Jeff Law
2020-11-17 11:53   ` Philipp Tomsich
2020-11-17 15:56     ` Jeff Law
2020-11-17 16:29       ` Philipp Tomsich
2020-11-17 16:46         ` Jakub Jelinek
2020-11-17 16:54           ` Jeff Law
2020-11-17 16:58             ` Jakub Jelinek
2020-11-18 23:46               ` Jeff Law
2020-11-17 17:23             ` Philipp Tomsich
2020-11-17 18:02               ` Jakub Jelinek
2020-11-17 17:14           ` Jim Wilson
2020-11-17 17:55             ` Jakub Jelinek
2020-11-17 16:35       ` Philipp Tomsich

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