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From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: Jeff Law <jeffreyalaw@gmail.com>
Cc: gcc-patches@gcc.gnu.org, Jeff Law <jlaw@ventanamicro.com>,
	 Palmer Dabbelt <palmer@rivosinc.com>,
	Christoph Muellner <christoph.muellner@vrull.eu>,
	 Kito Cheng <kito.cheng@gmail.com>,
	Vineet Gupta <vineetg@rivosinc.com>
Subject: Re: [PATCH] RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori
Date: Wed, 16 Nov 2022 21:01:46 +0100	[thread overview]
Message-ID: <CAAeLtUAhLuD06BmCrYWw_Cdhge8rN0X3gmTyQAwA-LhxQ4pNMQ@mail.gmail.com> (raw)
In-Reply-To: <cbbe20b9-98fc-6c78-6a05-5aff602dac5a@gmail.com>

[-- Attachment #1: Type: text/plain, Size: 1118 bytes --]

Applied to master. Thanks!

Philipp.

On Tue, 15 Nov 2022 at 18:36, Jeff Law <jeffreyalaw@gmail.com> wrote:

>
> On 11/13/22 13:48, Philipp Tomsich wrote:
> > We avoid reassociating "(~(a >> BIT_NO)) & 1" into "((~a) >> BIT_NO) & 1"
> > by splitting it into a zero-extraction (bext) and an xori.  This both
> > avoids burning a register on a temporary and generates a sequence that
> > clearly captures 'extract bit, then invert bit'.
> >
> > This change improves the previously generated
> >      srl   a0,a0,a1
> >      not        a0,a0
> >      andi  a0,a0,1
> > into
> >      bext  a0,a0,a1
> >      xori  a0,a0,1
> >
> > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> >
> > gcc/ChangeLog:
> >
> >       * config/riscv/bitmanip.md: Add split covering
> >       "(a & (1 << BIT_NO)) ? 0 : 1".
> >
> > gcc/testsuite/ChangeLog:
> >
> >       * gcc.target/riscv/zbs-bext.c: Add testcases.
> >       * gcc.target/riscv/zbs-bexti.c: Add testcases.
>
> OK.   Not terribly happy with the SUBREG, but I can guess that's an
> artifact of other patterns which require that operand to be QImode.
>
>
> Jeff
>
>
>

      reply	other threads:[~2022-11-16 20:01 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-13 20:48 Philipp Tomsich
2022-11-15 17:36 ` Jeff Law
2022-11-16 20:01   ` Philipp Tomsich [this message]

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