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References: <20221113204824.4062042-1-philipp.tomsich@vrull.eu>
 <20221113204824.4062042-2-philipp.tomsich@vrull.eu> <a8eadd0c-052f-a307-b767-11dc991a89c4@gmail.com>
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From: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: Mon, 14 Nov 2022 16:57:43 +0100
Message-ID: <CAAeLtUAtam-R-waHnOkUYf-NGv+9+iuxAMnpJQsqXrtL7_eauA@mail.gmail.com>
Subject: Re: [PATCH v2 1/2] RISC-V: Add basic support for the Ventana-VT1 core
To: Jeff Law <jeffreyalaw@gmail.com>
Cc: gcc-patches@gcc.gnu.org, Palmer Dabbelt <palmer@rivosinc.com>, 
	Vineet Gupta <vineetg@rivosinc.com>, Jeff Law <jlaw@ventanamicro.com>, 
	Kito Cheng <kito.cheng@gmail.com>, Christoph Muellner <christoph.muellner@vrull.eu>
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On Mon, 14 Nov 2022 at 16:52, Jeff Law <jeffreyalaw@gmail.com> wrote:
>
>
> On 11/13/22 13:48, Philipp Tomsich wrote:
> > The Ventana-VT1 core is compatible with rv64gc, Zb[abcs], Zifenci and
> > XVentanaCondOps.
> > This introduces a placeholder -mcpu=ventana-vt1, so tooling and
> > scripts don't need to change once full support (pipeline, tuning,
> > etc.) will become public later.
> >
> > gcc/ChangeLog:
> >
> >       * config/riscv/riscv-cores.def (RISCV_TUNE): Add ventana-vt1.
> >       (RISCV_CORE): Ditto.
> >       * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): Ditto.
> >       * config/riscv/riscv.cc: Add tune_info for ventana-vt1.
> >       * config/riscv/riscv.md: Add ventana-vt1.
> >       * doc/gcc/gcc-command-options/machine-dependent-options/risc-v-options.rst:
> >       Document -mcpu= and -mtune with ventana-vt1.
>
> OK.
>
>
> WRT the scheduler description.  I have one, but I think it's on the
> server at the vacation house which went offline a couple weeks ago and
> due to health reasons I haven't been up there to reset the internet
> connection.  Worst case I can just rebuild it from scratch, it's not
> that complex.

This series is pointing 'ventana-vt1' back to 'generic', so we could
also add the pipeline description later in the release cycle...

Philipp.