From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by sourceware.org (Postfix) with ESMTPS id 370E33858D38 for ; Thu, 10 Nov 2022 13:24:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 370E33858D38 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lf1-x130.google.com with SMTP id c1so3197724lfi.7 for ; Thu, 10 Nov 2022 05:24:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=atmWZ3Cw+3I9BU03JCGCRiFykRE+jJI+2YnB+MYfmrY=; b=l+Huv7pdbwbsn1Bo/+2Hiai+EwSj2kHmMT2IYGzW2Q+WJB/4Oktq0HfkwaTNZnq8eG KrHqTcCwXSW4O/+xKmortcyy8Yq97TR1hZvaQY6dn7uhF5T5fBEMAyfZ4naY8dXIIvWk //UW1FOeJDuytxtae6JLdAJ2fwT7HbNGxcLnK9bXkbFdgQLIzcqZK7CFmSb3qqih1GpD 4NiE7fxQJDCNQkRzjT4aIeZtve9mfzJTO7sjCQvBgLLsWsIRVEiZb7n9Oy7hMbJui2tM WwiG/h0ukUviMJK5rvU052COZtje7dLm4PNu98CFOvjCP+LTt+6RhZnsjkVPTru/n7rp NhXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=atmWZ3Cw+3I9BU03JCGCRiFykRE+jJI+2YnB+MYfmrY=; b=TsUcdOtysjYr9SXCGkbVuY0jKDspHyJcxT8fpANAKI1Tae83A8+guGqebiMHr0MTvT UZZIpPcLbyZQryK4pvIzIv4CeqBvZdW1Ld7ry/UFyFlGv5jA6vWX3vvLkuK9nRgEJj/l RPBvLB2dVRsQD1GXNQE9m5uX7kX0dnHpMN5dVRkl87qcb3XKNV01eDXks+z+ulg6A0lq jdmbZ6fuaKlbEoEmghp8zvCKrsacmdSTTNnKuqz9Ug/0biA0ba2xy5RjPDh3eanSQiim I119UXl8vVi4rEsYp3bQyW+hFYuOSd+z5UN5uKwtq/Q3m5w+rbTDgaUx/gHKlG6c2Veu kI/A== X-Gm-Message-State: ACrzQf1rFPYRZeQqU9EQZb8+V+Gu3qiUx6kww4R09XqOivlPJBMrIVUU OSudhj0kRvGR2dTODRqAANf1VAtbD/TI3zZrJpOz2A== X-Google-Smtp-Source: AMsMyM6yN/T3I9veQJjZYHtO/JtU/TNGW/Vca92YMrM4j2++9LMh18DVdZax+j24My6eo8nZDk6DBy1u8kzTpM9Q6hA= X-Received: by 2002:a19:f812:0:b0:4a4:1c92:2736 with SMTP id a18-20020a19f812000000b004a41c922736mr20824087lff.441.1668086692596; Thu, 10 Nov 2022 05:24:52 -0800 (PST) MIME-Version: 1.0 References: <20221109230736.3240512-1-philipp.tomsich@vrull.eu> In-Reply-To: From: Philipp Tomsich Date: Thu, 10 Nov 2022 14:24:40 +0100 Message-ID: Subject: Re: [PATCH] RISC-V: Implement movmisalign to enable SLP To: Kito Cheng Cc: gcc-patches@gcc.gnu.org, Vineet Gupta , Jeff Law , Palmer Dabbelt , Christoph Muellner Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, 10 Nov 2022 at 02:24, Kito Cheng wrote: > > I am not sure if I am missing something, your testcase should rely on > movmisalignhi pattern, but you defined movmisalign with ANYF > mode iterator rather than movmisalign with HI, SI, DI? It was already defined with the ANYI iterator in the patch, but that seems to be a moot point... > > And seems the testcase compile with `-march=3Drv64gc -mabi=3Dlp64 > -mtune=3Dsize -O2` w/o this patch already generated lhu/sh pair? ...as this change is needed on our GCC 12.x tree, but the current trunk seems to correctly form the lhu on master (at least for the artificial testcase) even without it. Thanks for catching this! I'll put this back to the end of the queue: this has to be looked at with the original underlying issue in SPEC CPU 2017. You'll probably not hear more on this specific case until after the close of phase 1. =E2=80=94Philipp. > > On Wed, Nov 9, 2022 at 3:08 PM Philipp Tomsich = wrote: > > > > The default implementation of support_vector_misalignment() checks > > whether movmisalign is present for the requested mode. This > > will be used by vect_supportable_dr_alignment() to determine whether a > > misaligned access of vectorized data is permissible. > > > > For RISC-V this is required to convert multiple integer data refs, > > such as "c[1] << 8) | c[0]" into a larger (in the example before: a > > halfword load) access. > > We conditionalize on !riscv_slow_unaligned_access_p to allow the > > misaligned refs, if they are not expected to be slow. > > > > This benefits both xalancbmk and blender on SPEC CPU 2017. > > > > gcc/ChangeLog: > > > > * config/riscv/riscv.md (movmisalign): Implement. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/riscv/movmisalign-1.c: New test. > > * gcc.target/riscv/movmisalign-2.c: New test. > > * gcc.target/riscv/movmisalign-3.c: New test. > > > > Signed-off-by: Philipp Tomsich > > --- > > > > gcc/config/riscv/riscv.md | 18 ++++++++++++++++++ > > gcc/testsuite/gcc.target/riscv/movmisalign-1.c | 12 ++++++++++++ > > gcc/testsuite/gcc.target/riscv/movmisalign-2.c | 12 ++++++++++++ > > gcc/testsuite/gcc.target/riscv/movmisalign-3.c | 12 ++++++++++++ > > 4 files changed, 54 insertions(+) > > create mode 100644 gcc/testsuite/gcc.target/riscv/movmisalign-1.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/movmisalign-2.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/movmisalign-3.c > > > > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > > index 289ff7470c6..1b357a9c57f 100644 > > --- a/gcc/config/riscv/riscv.md > > +++ b/gcc/config/riscv/riscv.md > > @@ -1715,6 +1715,24 @@ > > MAX_MACHINE_MODE, &operands[3], TRUE); > > }) > > > > +;; Misaligned (integer) moves: provide an implementation for > > +;; movmisalign, so the default support_vector_misalignment() will > > +;; return the right boolean depending on whether > > +;; riscv_slow_unaligned_access_p is set or not. > > +;; > > +;; E.g., this is needed for SLP to convert "c[1] << 8) | c[0]" into a > > +;; HImode load (a good test case will be blender and xalancbmk in SPEC > > +;; CPU 2017). > > +;; > > +(define_expand "movmisalign" > > + [(set (match_operand:ANYI 0 "") > > + (match_operand:ANYI 1 ""))] > > + "!riscv_slow_unaligned_access_p" > > +{ > > + if (riscv_legitimize_move (mode, operands[0], operands[1])) > > + DONE; > > +}) > > + > > ;; 64-bit integer moves > > > > (define_expand "movdi" > > diff --git a/gcc/testsuite/gcc.target/riscv/movmisalign-1.c b/gcc/tests= uite/gcc.target/riscv/movmisalign-1.c > > new file mode 100644 > > index 00000000000..791a3d63335 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/movmisalign-1.c > > @@ -0,0 +1,12 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=3Drv64gc -mabi=3Dlp64 -mtune=3Dsize" } */ > > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */ > > + > > +void f(unsigned short *sink, unsigned char *arr) > > +{ > > + *sink =3D (arr[1] << 8) | arr[0]; > > +} > > + > > +/* { dg-final { scan-assembler-times "lhu\t" 1 } } */ > > +/* { dg-final { scan-assembler-not "lbu\t" } } */ > > + > > diff --git a/gcc/testsuite/gcc.target/riscv/movmisalign-2.c b/gcc/tests= uite/gcc.target/riscv/movmisalign-2.c > > new file mode 100644 > > index 00000000000..ef73dcb2d9d > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/movmisalign-2.c > > @@ -0,0 +1,12 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=3Drv64gc -mabi=3Dlp64 -mtune=3Dsize -mstrict-a= lign" } */ > > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */ > > + > > +void f(unsigned short *sink, unsigned char *arr) > > +{ > > + *sink =3D (arr[1] << 8) | arr[0]; > > +} > > + > > +/* { dg-final { scan-assembler-times "lbu\t" 2 } } */ > > +/* { dg-final { scan-assembler-not "lhu\t" } } */ > > + > > diff --git a/gcc/testsuite/gcc.target/riscv/movmisalign-3.c b/gcc/tests= uite/gcc.target/riscv/movmisalign-3.c > > new file mode 100644 > > index 00000000000..963b11c27fd > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/movmisalign-3.c > > @@ -0,0 +1,12 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=3Drv64gc -mabi=3Dlp64 -mtune=3Drocket" } */ > > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */ > > + > > +void f(unsigned short *sink, unsigned char *arr) > > +{ > > + *sink =3D (arr[1] << 8) | arr[0]; > > +} > > + > > +/* { dg-final { scan-assembler-times "lbu\t" 2 } } */ > > +/* { dg-final { scan-assembler-not "lhu\t" } } */ > > + > > -- > > 2.34.1 > >