From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by sourceware.org (Postfix) with ESMTPS id F08FB3874744 for ; Tue, 14 Jun 2022 11:39:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org F08FB3874744 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-wr1-x436.google.com with SMTP id h5so10939118wrb.0 for ; Tue, 14 Jun 2022 04:39:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=sHdlH1MQ6v4mZuQuUIKxUZfWeprKz2Ak3m9uDF+c0FE=; b=f0ta5bLWVBAEKx36Ddr3j2QZU5H+mfSyQVGTuxbnLZFTaSo59jO96IiLFK2PCn1PLQ cD1EwK39POHnS/8yWu74e+WhhXVIXD1i0ujotlpnKaW6xov+7tRH5FOBNpYuK6+sBqar wX/wwyGkqrbCtYxdL7m+mp4ew70+SduNwg4hjShP3Rt6KQiYIBhXDi9ZjCZP2IlMdBRc 8JXyqwob2FgRKG0uZX5iyvoKaBDN1yQDMox1JCde8SWKKLWHC4vBh/WDGIQ2Mcu+ggdk F6O0U+DJKgRqXPxnbNlNX6gp50Cns2Eh+bwEgrBAayvdHUg1IiX6jdA32hg3seVUSZ9I bT3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=sHdlH1MQ6v4mZuQuUIKxUZfWeprKz2Ak3m9uDF+c0FE=; b=Rr0FNY9yMCbj+EZAm6LWMRdNq1l36fStImi/gHNzhvxtM33FsgVBgUim9b8mQGp8oF 6v1mI2XR8wMRHAB0LifDh0HFgAmmrLlpo0h6GqghUEDjqqzCwGkSDr9r0pNCq7GfwVT+ DewhZqW7rUsQ3xkW1C58qw7ZdqYbdWDxLlFw1bTnPBPfnKXTU4YXYFZh+9h1Xrh0lmWg 2UAlA8xmNoqcGws+/cOw6u3QySfTx/JCvaebsTME/RrXL0tS/4BJkyPJZavotiDcTY+i X8ZQjI4EfAlJAn235qEgORNNmtNysxUma5uYL1tFZh8pu9HK0+Hx0fku++IoCSJFLeLm LEHw== X-Gm-Message-State: AJIora83OWDZ1n7Lc5fw9MH8HmzdoVpDGq7CuvtiMo/mutMHLsttQ27t 9j4QIjqwjkzUo3Ef1NXvjfkthY+kBZTw5aYQroUqsQ== X-Google-Smtp-Source: AGRyM1s5pgm6PsULB7Czgb5cfwqZzh57h9YsYlKG7LxioG1d+USxHeV3yfd4CQjx7b87fDsJbXBM2C/88Izy0+sSEN8= X-Received: by 2002:adf:e847:0:b0:214:1e17:991b with SMTP id d7-20020adfe847000000b002141e17991bmr4272861wrn.288.1655206772659; Tue, 14 Jun 2022 04:39:32 -0700 (PDT) MIME-Version: 1.0 References: <20220524214703.4022737-1-philipp.tomsich@vrull.eu> <20220524214703.4022737-3-philipp.tomsich@vrull.eu> In-Reply-To: From: Philipp Tomsich Date: Tue, 14 Jun 2022 13:39:21 +0200 Message-ID: Subject: Re: [PATCH v1 2/3] RISC-V: Split slli+sh[123]add.uw opportunities to avoid zext.w To: Kito Cheng Cc: GCC Patches , Manolis Tsamis , Jim Wilson , Vineet Gupta , Palmer Dabbelt , Andrew Waterman Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 14 Jun 2022 11:39:35 -0000 Thanks, applied to master! For [3/3], I'll submit a new standalone patch with the requested changes. On Tue, 7 Jun 2022 at 12:25, Kito Cheng wrote: > > LGTM, you can commit that without [3/3] if you like :) > > On Wed, May 25, 2022 at 5:47 AM Philipp Tomsich > wrote: > > > > When encountering a prescaled (biased) value as a candidate for > > sh[123]add.uw, the combine pass will present this as shifted by the > > aggregate amount (prescale + shift-amount) with an appropriately > > adjusted mask constant that has fewer than 32 bits set. > > > > E.g., here's the failing expression seen in combine for a prescale of > > 1 and a shift of 2 (note how 0x3fffffff8 >> 3 is 0x7fffffff). > > Trying 7, 8 -> 10: > > 7: r78:SI=r81:DI#0<<0x1 > > REG_DEAD r81:DI > > 8: r79:DI=zero_extend(r78:SI) > > REG_DEAD r78:SI > > 10: r80:DI=r79:DI<<0x2+r82:DI > > REG_DEAD r79:DI > > REG_DEAD r82:DI > > Failed to match this instruction: > > (set (reg:DI 80 [ cD.1491 ]) > > (plus:DI (and:DI (ashift:DI (reg:DI 81) > > (const_int 3 [0x3])) > > (const_int 17179869176 [0x3fffffff8])) > > (reg:DI 82))) > > > > To address this, we introduce a splitter handling these cases. > > > > gcc/ChangeLog: > > > > * config/riscv/bitmanip.md: Add split to handle opportunities > > for slli + sh[123]add.uw > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/riscv/zba-shadd.c: New test. > > > > Signed-off-by: Philipp Tomsich > > Co-developed-by: Manolis Tsamis > > > > --- > > > > gcc/config/riscv/bitmanip.md | 44 ++++++++++++++++++++++ > > gcc/testsuite/gcc.target/riscv/zba-shadd.c | 13 +++++++ > > 2 files changed, 57 insertions(+) > > create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shadd.c > > > > diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md > > index 0ab9ffe3c0b..6c1ccc6f8c5 100644 > > --- a/gcc/config/riscv/bitmanip.md > > +++ b/gcc/config/riscv/bitmanip.md > > @@ -79,6 +79,50 @@ (define_insn "*shNadduw" > > [(set_attr "type" "bitmanip") > > (set_attr "mode" "DI")]) > > > > +;; During combine, we may encounter an attempt to combine > > +;; slli rtmp, rs, #imm > > +;; zext.w rtmp, rtmp > > +;; sh[123]add rd, rtmp, rs2 > > +;; which will lead to the immediate not satisfying the above constraints. > > +;; By splitting the compound expression, we can simplify to a slli and a > > +;; sh[123]add.uw. > > +(define_split > > + [(set (match_operand:DI 0 "register_operand") > > + (plus:DI (and:DI (ashift:DI (match_operand:DI 1 "register_operand") > > + (match_operand:QI 2 "immediate_operand")) > > + (match_operand:DI 3 "consecutive_bits_operand")) > > + (match_operand:DI 4 "register_operand"))) > > + (clobber (match_operand:DI 5 "register_operand"))] > > + "TARGET_64BIT && TARGET_ZBA" > > + [(set (match_dup 5) (ashift:DI (match_dup 1) (match_dup 6))) > > + (set (match_dup 0) (plus:DI (and:DI (ashift:DI (match_dup 5) > > + (match_dup 7)) > > + (match_dup 8)) > > + (match_dup 4)))] > > +{ > > + unsigned HOST_WIDE_INT mask = UINTVAL (operands[3]); > > + /* scale: shift within the sh[123]add.uw */ > > + int scale = 32 - clz_hwi (mask); > > + /* bias: pre-scale amount (i.e. the prior shift amount) */ > > + int bias = ctz_hwi (mask) - scale; > > + > > + /* If the bias + scale don't add up to operand[2], reject. */ > > + if ((scale + bias) != UINTVAL (operands[2])) > > + FAIL; > > + > > + /* If the shift-amount is out-of-range for sh[123]add.uw, reject. */ > > + if ((scale < 1) || (scale > 3)) > > + FAIL; > > + > > + /* If there's no bias, the '*shNadduw' pattern should have matched. */ > > + if (bias == 0) > > + FAIL; > > + > > + operands[6] = GEN_INT (bias); > > + operands[7] = GEN_INT (scale); > > + operands[8] = GEN_INT (0xffffffffULL << scale); > > +}) > > + > > (define_insn "*add.uw" > > [(set (match_operand:DI 0 "register_operand" "=r") > > (plus:DI (zero_extend:DI > > diff --git a/gcc/testsuite/gcc.target/riscv/zba-shadd.c b/gcc/testsuite/gcc.target/riscv/zba-shadd.c > > new file mode 100644 > > index 00000000000..33da2530f3f > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/zba-shadd.c > > @@ -0,0 +1,13 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-O2 -march=rv64gc_zba -mabi=lp64" } */ > > + > > +unsigned long foo(unsigned int a, unsigned long b) > > +{ > > + a = a << 1; > > + unsigned long c = (unsigned long) a; > > + unsigned long d = b + (c<<2); > > + return d; > > +} > > + > > +/* { dg-final { scan-assembler "sh2add.uw" } } */ > > +/* { dg-final { scan-assembler-not "zext" } } */ > > \ No newline at end of file > > -- > > 2.34.1 > >