From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by sourceware.org (Postfix) with ESMTPS id 648FE386DC7C for ; Tue, 14 Jun 2022 11:38:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 648FE386DC7C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-wm1-x335.google.com with SMTP id o37-20020a05600c512500b0039c4ba4c64dso6065558wms.2 for ; Tue, 14 Jun 2022 04:38:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=9GCh9OZG6WxSxuzcsZAyPD8UUxnxVgGMj4LQ4f8T670=; b=hFK0J7ZsXaPn3jHju20oXcHWaC+omyWohxBfUHU+bL4V8V/4tPnXYbhwgBK6MRb5yU ubByFdbugKA/tWQ+ae0Kx1mMp39lMh7b9IiGviQ2uO7Lcgs3uDv2szblRR7JRLzaXgVX ZubjI/IH93G/YuXclu7l5cH5EkcNmNTWYcWvSEQMCKmwuRJ8EIgdxxoXEXDTFgGMsy2c MAq2U1dL5FgffopKzhR1lSJ81r6RrY6UYTN/BKQkRFcBS17e+cPk8auUMbfMWUfxCM8b ouJp0ilPu4QxgVG4BTpoMAD/UQz52svwcnd44nb/YfU3FVtwngXb5r+t/jIW3B1dyAkR u0HA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=9GCh9OZG6WxSxuzcsZAyPD8UUxnxVgGMj4LQ4f8T670=; b=ldUy7hHcxY8hbho2puW8AfYp8xqZPG2xi+0EXv+FvItBfOjcel8uIssWuSm7o2ju5R KrDIX1DMMrQlMTq1LEvyPhc1ai2rnSLsccV4AeQQCGD/opcpXSK58msryFCnR5sWyorj rWwf99riFp4qrXHgiCifld4/9Uwb4UkhJNotDyqst7e47/wO61FGCbhc5pE255IlnSfQ hQbyXXkysrl0s3F3zMSJT615zPX5D8FYrH+yuRYeWLjswEBi6Ty6DvsdjD/fTT55IsJD djnWzMdejT+tv+TVTLutOX7USNs63VcGjpk6m9OevgPLtRoDNSVhVXLGG27ICi3/ay+l MsJw== X-Gm-Message-State: AOAM530neXAVR3y1aU3ExIAVOAovQNNcAdyYziOPPScyfZXJhdUXJAMO 52dhVNSmTTtJErVKSHjvCMG8sQZdUvidhGsX+PfzXQ== X-Google-Smtp-Source: ABdhPJxokdsapgmdLi97n1Iu4X3wpo4V1VJg9ouWGwxTvv+itCF6CByOO19sZAf17lLOCsxtuFw6b6aVWJ3y81zHLuA= X-Received: by 2002:a1c:29c1:0:b0:39d:86c0:3ece with SMTP id p184-20020a1c29c1000000b0039d86c03ecemr3123534wmp.138.1655206724078; Tue, 14 Jun 2022 04:38:44 -0700 (PDT) MIME-Version: 1.0 References: <20220524214703.4022737-1-philipp.tomsich@vrull.eu> <20220524214703.4022737-2-philipp.tomsich@vrull.eu> In-Reply-To: From: Philipp Tomsich Date: Tue, 14 Jun 2022 13:38:33 +0200 Message-ID: Subject: Re: [PATCH v1 1/3] RISC-V: add consecutive_bits_operand predicate To: Kito Cheng Cc: GCC Patches , Andrew Waterman , Vineet Gupta Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 14 Jun 2022 11:38:47 -0000 Thanks, applied to master! On Tue, 7 Jun 2022 at 12:26, Kito Cheng wrote: > > LGTM > > > On Wed, May 25, 2022 at 5:48 AM Philipp Tomsich > wrote: > > > > Provide an easy way to constrain for constants that are a a single, > > consecutive run of ones. > > > > gcc/ChangeLog: > > > > * config/riscv/predicates.md (consecutive_bits_operand): > > Implement new predicate. > > > > Signed-off-by: Philipp Tomsich > > --- > > > > gcc/config/riscv/predicates.md | 11 +++++++++++ > > 1 file changed, 11 insertions(+) > > > > diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md > > index c37caa2502b..90db5dfcdd5 100644 > > --- a/gcc/config/riscv/predicates.md > > +++ b/gcc/config/riscv/predicates.md > > @@ -243,3 +243,14 @@ (define_predicate "const63_operand" > > (define_predicate "imm5_operand" > > (and (match_code "const_int") > > (match_test "INTVAL (op) < 5"))) > > + > > +;; A CONST_INT operand that consists of a single run of consecutive set bits. > > +(define_predicate "consecutive_bits_operand" > > + (match_code "const_int") > > +{ > > + unsigned HOST_WIDE_INT val = UINTVAL (op); > > + if (exact_log2 ((val >> ctz_hwi (val)) + 1) < 0) > > + return false; > > + > > + return true; > > +}) > > -- > > 2.34.1 > >