From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by sourceware.org (Postfix) with ESMTPS id 3EC4E388B68D for ; Tue, 15 Nov 2022 10:36:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 3EC4E388B68D Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lf1-x12e.google.com with SMTP id c1so23749840lfi.7 for ; Tue, 15 Nov 2022 02:36:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=c2hN7feypO4RqCW8/3oh71sKLdSuvcv6yjb+j8szRFU=; b=Vg2Md3IYTw8H92ooPn+6hSRHLZDEfK+8NFUf/4q/9kQlbOOZ4R3h4na5RT5NyT5mAD makWshhNfzbR3cB29lm5+zIyymllcC46sU/do19y5BsNQS1gQHedYBy1mfTn7Fw7yWSf NdqezyeLv5/y4DJ8S9Hocm7oRXJyX/bfgQFXQVN3r/J3avAcD4fYqfDzk2Ns6fRUvhRN yhJ7xUoD9FTf/Fdmq1+HaN1EGqgC05ZDQXiJEgmtxMWU39OVK1MKAKSBDNG++sn620L9 HrUeH5Zx5vSiNB1CiaIgW8vU6EHEkENcV9INPsX2OZm6Gy508N86R7bMk/+TIRhCWAzX o8lA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=c2hN7feypO4RqCW8/3oh71sKLdSuvcv6yjb+j8szRFU=; b=dPiwrMdgeTZrr7UUG/xwrNJHqKRJXaG4ctk23U7Ebh3mrWE0Nwkemdm2sHVNa6pRjC lOjlAvUeJRQc9Zc1om8Lx5TuTR72VC0iBHzsBM5EQclOOQ77gzaEf87NtJCE17ellncf iKY5sYoJCi8741jQMBndsSuurKyE8cDrM8Ubru382Y6GoLLQliB5HOJWzKodDtDnTYiF kLRU4SLXxkdljdf9WGHUrxcVPj8VnN7CDl1+EufWle53W2Mjgg7rebjhGNPKJNSl6Vqa VgT+5gBGud6LT/Fnq63aTNRj4A3qROdO8X5BcZMyogeNmjLudbTfjb0qtfvHhyQDY5bp mkOg== X-Gm-Message-State: ANoB5pkv0WwBnRpppf9VLQ0Vi//UUSg9iA+Y1kIS4PVsYd/xXvQxR+Fs ZSyUQCSRFx1ih+/BD+cZRxYSIay6LbAO+NKscjQz/A== X-Google-Smtp-Source: AA0mqf4cBcAtQKmm76FDPP7mgaxj7x2i7GuXtuB+ovHdlDqjf9UTL01BmB7rT3rGv4mL6DY0SzIBXkZj7XgjTNJbe9U= X-Received: by 2002:a05:6512:3589:b0:4a9:2ca6:c14b with SMTP id m9-20020a056512358900b004a92ca6c14bmr5986918lfr.163.1668508561467; Tue, 15 Nov 2022 02:36:01 -0800 (PST) MIME-Version: 1.0 References: <20221114162918.1563116-1-jiawei@iscas.ac.cn> In-Reply-To: <20221114162918.1563116-1-jiawei@iscas.ac.cn> From: Philipp Tomsich Date: Tue, 15 Nov 2022 11:35:49 +0100 Message-ID: Subject: Re: [PATCH] RISC-V: Optimal RVV epilogue logic. To: jiawei Cc: gcc-patches@gcc.gnu.org, kito.cheng@sifive.com, palmer@rivosinc.com, juzhe.zhong@rivai.ai, christoph.muellner@vrull.eu, wuwei2016@iscas.ac.cn Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, 14 Nov 2022 at 17:29, jiawei wrote: > > Skip add insn generate if the adjust size equal to zero. > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_expand_epilogue): > New if control segement. > > --- > gcc/config/riscv/riscv.cc | 18 ++++++++++-------- > 1 file changed, 10 insertions(+), 8 deletions(-) > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 02a01ca0b7c..af138db7545 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -5186,24 +5186,26 @@ riscv_expand_epilogue (int style) > } > > /* Get an rtx for STEP1 that we can add to BASE. */ > - rtx adjust = GEN_INT (step1.to_constant ()); > - if (!SMALL_OPERAND (step1.to_constant ())) > + if (step1.to_constant () != 0){ > + rtx adjust = GEN_INT (step1.to_constant ()); > + if (!SMALL_OPERAND (step1.to_constant ())) Please take a look at the recent improvements for the add3 expander (recently submitted as https://patchwork.ozlabs.org/project/gcc/patch/20221109230718.3240479-1-philipp.tomsich@vrull.eu/). Maybe you also want to use the test for the addi_operand(...) instead of SMALL_OPERAND? > { > riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust); > adjust = RISCV_PROLOGUE_TEMP (Pmode); > } > > - insn = emit_insn ( > + insn = emit_insn ( > gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust)); > > - rtx dwarf = NULL_RTX; > - rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx, > + rtx dwarf = NULL_RTX; > + rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx, > GEN_INT (step2)); > > - dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf); > - RTX_FRAME_RELATED_P (insn) = 1; > + dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf); > + RTX_FRAME_RELATED_P (insn) = 1; > > - REG_NOTES (insn) = dwarf; > + REG_NOTES (insn) = dwarf; > + } > } > else if (frame_pointer_needed) > { > -- > 2.25.1 >