From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: Kito Cheng <kito.cheng@sifive.com>
Cc: Christoph Muellner <christoph.muellner@vrull.eu>,
gcc-patches@gcc.gnu.org, Jim Wilson <jim.wilson.gcc@gmail.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Andrew Waterman <andrew@sifive.com>,
JuzheZhong <juzhe.zhong@rivai.ai>,
Jojo R <rjiejie@linux.alibaba.com>
Subject: Re: [PATCH] target/109296 - riscv: Add missing mode specifiers for XTheadMemPair
Date: Mon, 27 Mar 2023 20:19:38 +0800 [thread overview]
Message-ID: <CAAeLtUBSEScULtxPr2_9XLD24N6uezhAoC51ALVQ2VmrhP5uDA@mail.gmail.com> (raw)
In-Reply-To: <CALLt3TgxS=4E9V4QkANgpSLvdFs1Umz8qKSNfQQZaYNcE1ANdg@mail.gmail.com>
Applied to master, thanks!
Philipp.
On Mon, 27 Mar 2023 at 19:55, Kito Cheng <kito.cheng@sifive.com> wrote:
>
> OK for trunk, thanks :)
>
> On Mon, Mar 27, 2023 at 7:04 PM Christoph Muellner <christoph.muellner@vrull.eu> wrote:
>>
>> From: Christoph Müllner <christoph.muellner@vrull.eu>
>>
>> This patch adds missing mode specifiers for XTheadMemPair INSNs.
>>
>> gcc/ChangeLog:
>> PR target/109296
>> * config/riscv/thead.md: Add missing mode specifiers.
>>
>> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
>> ---
>> gcc/config/riscv/thead.md | 16 ++++++++--------
>> 1 file changed, 8 insertions(+), 8 deletions(-)
>>
>> diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
>> index 63c4af6f77d..0623607d3dc 100644
>> --- a/gcc/config/riscv/thead.md
>> +++ b/gcc/config/riscv/thead.md
>> @@ -321,10 +321,10 @@ (define_insn "*th_mempair_store_<GPR:mode>2"
>>
>> ;; MEMPAIR load DI extended signed SI
>> (define_insn "*th_mempair_load_extendsidi2"
>> - [(set (match_operand 0 "register_operand" "=r")
>> - (sign_extend:DI (match_operand 1 "memory_operand" "m")))
>> - (set (match_operand 2 "register_operand" "=r")
>> - (sign_extend:DI (match_operand 3 "memory_operand" "m")))]
>> + [(set (match_operand:DI 0 "register_operand" "=r")
>> + (sign_extend:DI (match_operand:SI 1 "memory_operand" "m")))
>> + (set (match_operand:DI 2 "register_operand" "=r")
>> + (sign_extend:DI (match_operand:SI 3 "memory_operand" "m")))]
>> "TARGET_XTHEADMEMPAIR && TARGET_64BIT && reload_completed
>> && th_mempair_operands_p (operands, true, SImode)"
>> { return th_mempair_output_move (operands, true, SImode, SIGN_EXTEND); }
>> @@ -334,10 +334,10 @@ (define_insn "*th_mempair_load_extendsidi2"
>>
>> ;; MEMPAIR load DI extended unsigned SI
>> (define_insn "*th_mempair_load_zero_extendsidi2"
>> - [(set (match_operand 0 "register_operand" "=r")
>> - (zero_extend:DI (match_operand 1 "memory_operand" "m")))
>> - (set (match_operand 2 "register_operand" "=r")
>> - (zero_extend:DI (match_operand 3 "memory_operand" "m")))]
>> + [(set (match_operand:DI 0 "register_operand" "=r")
>> + (zero_extend:DI (match_operand:SI 1 "memory_operand" "m")))
>> + (set (match_operand:DI 2 "register_operand" "=r")
>> + (zero_extend:DI (match_operand:SI 3 "memory_operand" "m")))]
>> "TARGET_XTHEADMEMPAIR && TARGET_64BIT && reload_completed
>> && th_mempair_operands_p (operands, true, SImode)"
>> { return th_mempair_output_move (operands, true, SImode, ZERO_EXTEND); }
>> --
>> 2.39.2
>>
prev parent reply other threads:[~2023-03-27 12:19 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-27 11:04 Christoph Muellner
2023-03-27 11:55 ` Kito Cheng
2023-03-27 12:19 ` Philipp Tomsich [this message]
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