From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by sourceware.org (Postfix) with ESMTPS id BA2B23858D39 for ; Mon, 27 Mar 2023 12:19:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BA2B23858D39 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ed1-x52b.google.com with SMTP id ew6so35278895edb.7 for ; Mon, 27 Mar 2023 05:19:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1679919589; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=PXC0OWWgf6UWcS66VpDq6LVt9SLd/hO14NxVWSVbfdw=; b=gVhvxfpPhQM5QfNsbLEHEXGT44DUbPuqdewAFq67qWoTXCFPQb4BwPRrXFWQ7UZufA unFMNUYeYB5GWu3iqUQNzpVwx+NgJ9yFegk5sQ3MIT18nGxlJkyKixSobJnQvQ3KxxH9 sAhjaNTnueXkGiNZ53MUxtJZZ27jvyxdSFF1vG83BskVPbhV1umu5wZAk9cM9fPZ+Z5Z hALkCCX5MihoeWTJHIUngGupQyn8OajQmRLKzBSW/ULhsFIzWBMsO0gZQF7/9+0i0p35 FmKOU/BA0GpHefc7Xd6ICicevyeUKZ7V8dSlb6FoUpdEpe7JoYAbEvi91WrPZ4tLWzkL uo5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679919589; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PXC0OWWgf6UWcS66VpDq6LVt9SLd/hO14NxVWSVbfdw=; b=7VzsLAWz1ebTZNsiXdkAv6XO9xQkphNNc8Cj+5kdLKYGEQO+RWhPLy4hRBd0r6CTJT aY5WzdY26xI9BFWwQIV9u3xjGG2OWtYj82aa7bq0xsDUdX3YRXtAKGoWJH4sNARDy0Sa mm7ynG/WEkFrzxZFpRnyl+FWpRtmR2zUNtQQ6dJGvFhWhkdvEnYQpKkmYQsgzB4Muq6d WYD1j8fRa2cbklCPKe+TAPMvVG9jK+L6HIj26CeqhllqByH2NzYTlsmSsR7eFGcGXHY8 hQ9r+7q7brXcFLn4IMeWBAmG45Lz0FS5JsM9L0luzYgLex0mIpO8UhDUr4EuL0JqL+zd hmdw== X-Gm-Message-State: AAQBX9dqdXDmg+Jz0xtozlZMNeG2dNsxr1KMZHZceeh1luoYMbBdRqLK gPp175asMDniB0ur/MwFgw8VjQa/MWzje86tOMg5Xg== X-Google-Smtp-Source: AKy350ZscTbv3kjpoMua+bYluS/9HNrS5ZHBKcYPfNssU9dXM12eY8/WEOwmiZ2SPACdKWt3+yYBVTUeBgbf2a6hwOg= X-Received: by 2002:a17:906:4d55:b0:930:af80:5ba6 with SMTP id b21-20020a1709064d5500b00930af805ba6mr5691728ejv.1.1679919589428; Mon, 27 Mar 2023 05:19:49 -0700 (PDT) MIME-Version: 1.0 References: <20230327110422.3353876-1-christoph.muellner@vrull.eu> In-Reply-To: From: Philipp Tomsich Date: Mon, 27 Mar 2023 20:19:38 +0800 Message-ID: Subject: Re: [PATCH] target/109296 - riscv: Add missing mode specifiers for XTheadMemPair To: Kito Cheng Cc: Christoph Muellner , gcc-patches@gcc.gnu.org, Jim Wilson , Palmer Dabbelt , Andrew Waterman , JuzheZhong , Jojo R Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-9.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Applied to master, thanks! Philipp. On Mon, 27 Mar 2023 at 19:55, Kito Cheng wrote: > > OK for trunk, thanks :) > > On Mon, Mar 27, 2023 at 7:04=E2=80=AFPM Christoph Muellner wrote: >> >> From: Christoph M=C3=BCllner >> >> This patch adds missing mode specifiers for XTheadMemPair INSNs. >> >> gcc/ChangeLog: >> PR target/109296 >> * config/riscv/thead.md: Add missing mode specifiers. >> >> Signed-off-by: Christoph M=C3=BCllner >> --- >> gcc/config/riscv/thead.md | 16 ++++++++-------- >> 1 file changed, 8 insertions(+), 8 deletions(-) >> >> diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md >> index 63c4af6f77d..0623607d3dc 100644 >> --- a/gcc/config/riscv/thead.md >> +++ b/gcc/config/riscv/thead.md >> @@ -321,10 +321,10 @@ (define_insn "*th_mempair_store_2" >> >> ;; MEMPAIR load DI extended signed SI >> (define_insn "*th_mempair_load_extendsidi2" >> - [(set (match_operand 0 "register_operand" "=3Dr") >> - (sign_extend:DI (match_operand 1 "memory_operand" "m"))) >> - (set (match_operand 2 "register_operand" "=3Dr") >> - (sign_extend:DI (match_operand 3 "memory_operand" "m")))] >> + [(set (match_operand:DI 0 "register_operand" "=3Dr") >> + (sign_extend:DI (match_operand:SI 1 "memory_operand" "m"))) >> + (set (match_operand:DI 2 "register_operand" "=3Dr") >> + (sign_extend:DI (match_operand:SI 3 "memory_operand" "m")))] >> "TARGET_XTHEADMEMPAIR && TARGET_64BIT && reload_completed >> && th_mempair_operands_p (operands, true, SImode)" >> { return th_mempair_output_move (operands, true, SImode, SIGN_EXTEND)= ; } >> @@ -334,10 +334,10 @@ (define_insn "*th_mempair_load_extendsidi2" >> >> ;; MEMPAIR load DI extended unsigned SI >> (define_insn "*th_mempair_load_zero_extendsidi2" >> - [(set (match_operand 0 "register_operand" "=3Dr") >> - (zero_extend:DI (match_operand 1 "memory_operand" "m"))) >> - (set (match_operand 2 "register_operand" "=3Dr") >> - (zero_extend:DI (match_operand 3 "memory_operand" "m")))] >> + [(set (match_operand:DI 0 "register_operand" "=3Dr") >> + (zero_extend:DI (match_operand:SI 1 "memory_operand" "m"))) >> + (set (match_operand:DI 2 "register_operand" "=3Dr") >> + (zero_extend:DI (match_operand:SI 3 "memory_operand" "m")))] >> "TARGET_XTHEADMEMPAIR && TARGET_64BIT && reload_completed >> && th_mempair_operands_p (operands, true, SImode)" >> { return th_mempair_output_move (operands, true, SImode, ZERO_EXTEND)= ; } >> -- >> 2.39.2 >>