From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by sourceware.org (Postfix) with ESMTPS id 5DFCD3857727 for ; Fri, 14 Apr 2023 09:52:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5DFCD3857727 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ej1-x631.google.com with SMTP id c9so5340682ejz.1 for ; Fri, 14 Apr 2023 02:52:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1681465919; x=1684057919; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=807tTBKRlley0PCqxxhSnF5tcTsZzGkoUytfV2iRW/0=; b=U0+iNF0SE7r1Dks53jEvvYV9XbG246IruMHEScnTB/f5/fCyoXB/rxhJ3pIDKS8IdK d5P7Ky+LlhMmeVl8ZqeIrmXNuVr4/G0FDZ6CKo5NzxrfnSlbyEx9/IWkgYvtTft8nPEE KnX0PubQxkcFdZAvRPPk1WPdcHAzyE+LO/74Jh22VadO8+zzTVk3GKVkioQoawFTm4FO aQWXP6nLjZSq6nZrjSQZENIskDhrFhf/5yloCqjG+9RHcEWBmpWQO5sZg5ufeZBkfPO0 Yfy+EISwzRIUzb3/yk5KvieQZMY8eHwFBalrD6JPLkeXM6sgJFNAPCjlSOYuHyudpGS6 Qgbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681465919; x=1684057919; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=807tTBKRlley0PCqxxhSnF5tcTsZzGkoUytfV2iRW/0=; b=j/lBYWV3UWbZydodc/b08e7WbetnNfjXt1Ale9q3Fx+fJNOJWv9oFAVqM+hVQ7wc+S FMyhwr51jwrzaOd+Gkbj8BdgPJqkstVtFS6iEL1IvbVlLCeLB++cxJIQKfWTMKI/SfxI 97fPI/bagW2Qk0w/J1XGcSle/1Zj0MdhVuhFjISgLER0IgHdUgJ36JWg9RxXzERu5dHV wdUAPxVVBC5ulb3fu7o/fG+1s7Jn/bJUdsXQQT5yW6bAVZ7bw8PvwjZdrgPy6tN/lywU +xo2/P0Acfb9MsFb6rAnGiXUMRNu2GWu/KaB9oiXhSPo0zVGvPzugsW2tQt9fzU0r23P /bWQ== X-Gm-Message-State: AAQBX9foYUnQvq3Yu5Gzy3bKQl5mmw+Gx4V4/u/nfQNgupnZ3tN9Kc3+ od2s8qLrwjZvxjpZfW3AHjfOdfKHpkj703pVNaAG9xiD337jZbPLZyI= X-Google-Smtp-Source: AKy350YCcwyjU+P9lAYASILAI5XGxP6LTnWrPzTgmUZvtoPAnHf5Hlw5c2g/3ItBg5htmLy8NxzsLtZ5taN2aPk03Ms= X-Received: by 2002:a17:906:b1c5:b0:93f:9b4a:12f3 with SMTP id bv5-20020a170906b1c500b0093f9b4a12f3mr6021069ejb.10.1681465918953; Fri, 14 Apr 2023 02:51:58 -0700 (PDT) MIME-Version: 1.0 References: <20230413232157.1487389-1-philipp.tomsich@vrull.eu> In-Reply-To: From: Philipp Tomsich Date: Fri, 14 Apr 2023 11:51:48 +0200 Message-ID: Subject: Re: [PATCH] aarch64: disable LDP via tuning structure for -mcpu=ampere1 To: Kyrylo Tkachov Cc: "gcc-patches@gcc.gnu.org" , Di Zhao Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_NUMSUBJECT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: For phase 1, we plan to replace this with a feature to allow finer-grained control over when to use LDP or STP (i.e., control these independently) with the following scopes and policies: - scopes are: { sched-fusion, mem, pro/epilogue, peephole } - policies are: { default (from tuning), always, never, aligned (to 2x element size) } Happy to get this fuller solution already onto the list, if it helps with forward-progress on the localised change. The current patch tries to be minimally invasive (i.e., it doesn't touch STP). It intentionally avoids modifying the sched-fusion logic (which requires refactoring, as it doesn't differentiate between the load and store cases), pro/epilogue creation and mem* function expansion. Philipp. On Fri, 14 Apr 2023 at 11:31, Philipp Tomsich wrote: > > Kyrylo, > > On Fri, 14 Apr 2023 at 11:21, Kyrylo Tkachov wrote: > > > > Hi Philipp, > > > > > -----Original Message----- > > > From: Philipp Tomsich > > > Sent: Friday, April 14, 2023 12:22 AM > > > To: gcc-patches@gcc.gnu.org > > > Cc: Kyrylo Tkachov ; Philipp Tomsich > > > ; Di Zhao > > > Subject: [PATCH] aarch64: disable LDP via tuning structure for - > > > mcpu=ampere1 > > > > > > AmpereOne (-mcpu=ampere1) breaks LDP instructions into two uops. > > > Given the chance that this causes instructions to slip into the next > > > decoding cycle and the additional overheads when handling > > > cacheline-crossing LDP instructions, we disable the generation of LDP > > > isntructions through the tuning structure from instruction combining > > > (such as in peephole2). > > > > > > Given the code-density benefits in builtins and prologue/epilogue > > > expansion, we allow LDPs there. > > > > LDPs are indeed quite an important part of the ISA for code density and there are, in principle, second-order benefits from using them, like keeping the instruction cache footprint low (which can be important for large workloads). > > Did you gather some benchmarks showing a benefit of disabling them in this manner? > > > This has been benchmark-driven, but I need to follow up separately (as > I the final numbers are with the folks that have access to the > benchmark machines).. > > > > > > This commit: > > > * adds a new tuning option AARCH64_EXTRA_TUNE_NO_LDP_COMBINE > > > * allows -moverride=tune=... to override this > > > > > > Signed-off-by: Philipp Tomsich > > > Co-Authored-By: Di Zhao > > > > > > gcc/ChangeLog: > > > > > > * config/aarch64/aarch64-tuning-flags.def > > > (AARCH64_EXTRA_TUNING_OPTION): > > > Add AARCH64_EXTRA_TUNE_NO_LDP_COMBINE. > > > * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp): > > > Check for the above tuning option when processing loads. > > > > > > --- > > > > > > gcc/config/aarch64/aarch64-tuning-flags.def | 3 +++ > > > gcc/config/aarch64/aarch64.cc | 8 +++++++- > > > 2 files changed, 10 insertions(+), 1 deletion(-) > > > > > > diff --git a/gcc/config/aarch64/aarch64-tuning-flags.def > > > b/gcc/config/aarch64/aarch64-tuning-flags.def > > > index 712895a5263..52112ba7c48 100644 > > > --- a/gcc/config/aarch64/aarch64-tuning-flags.def > > > +++ b/gcc/config/aarch64/aarch64-tuning-flags.def > > > @@ -44,6 +44,9 @@ AARCH64_EXTRA_TUNING_OPTION > > > ("cheap_shift_extend", CHEAP_SHIFT_EXTEND) > > > /* Disallow load/store pair instructions on Q-registers. */ > > > AARCH64_EXTRA_TUNING_OPTION ("no_ldp_stp_qregs", > > > NO_LDP_STP_QREGS) > > > > > > +/* Disallow load-pair instructions to be formed in combine/peephole. */ > > > +AARCH64_EXTRA_TUNING_OPTION ("no_ldp_combine", > > > NO_LDP_COMBINE) > > > + > > > AARCH64_EXTRA_TUNING_OPTION ("rename_load_regs", > > > RENAME_LOAD_REGS) > > > > > > AARCH64_EXTRA_TUNING_OPTION ("cse_sve_vl_constants", > > > CSE_SVE_VL_CONSTANTS) > > > diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc > > > index f4ef22ce02f..8dc1a9ceb17 100644 > > > --- a/gcc/config/aarch64/aarch64.cc > > > +++ b/gcc/config/aarch64/aarch64.cc > > > @@ -1971,7 +1971,7 @@ static const struct tune_params ampere1a_tunings > > > = > > > 2, /* min_div_recip_mul_df. */ > > > 0, /* max_case_values. */ > > > tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ > > > - (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ > > > + (AARCH64_EXTRA_TUNE_NO_LDP_COMBINE), /* tune_flags. */ > > > &ere1_prefetch_tune > > > }; > > > > > > @@ -26053,6 +26053,12 @@ aarch64_operands_ok_for_ldpstp (rtx > > > *operands, bool load, > > > enum reg_class rclass_1, rclass_2; > > > rtx mem_1, mem_2, reg_1, reg_2; > > > > > > + /* Allow the tuning structure to disable LDP instruction formation > > > + from combining instructions (e.g., in peephole2). */ > > > + if (load && (aarch64_tune_params.extra_tuning_flags > > > + & AARCH64_EXTRA_TUNE_NO_LDP_COMBINE)) > > > + return false; > > > > If we do decide to do this, I think this is not a complete approach. See the similar tuning flag AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS. > > There's various other places in the backend that would need to be adjusted to avoid bringing loads together for the peephole2s to merge (the sched_fusion stuff). > > Plus there's the cpymem expansions that would generate load pairs too... > > I have add-on patches for these, but given that I don't have direct > access to the benchmarking machine and the benchmarks have been run > with this functionality only, I didn't submit them for the time being. > Do you see a path to get this in during the current cycle and defer > the add-on patches (happy to resubmit as a series) only? > > > We'd want some testcases added to check that LDPs are blocked too... > > > > Thanks, > > Kyrill > > > > > + > > > if (load) > > > { > > > mem_1 = operands[1]; > > > -- > > > 2.34.1 > >