From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by sourceware.org (Postfix) with ESMTPS id 563453852C53 for ; Thu, 17 Nov 2022 18:57:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 563453852C53 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lf1-x12b.google.com with SMTP id a29so4300728lfj.9 for ; Thu, 17 Nov 2022 10:57:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=vzRhRNNrJSdjTI894s6ytv8kya/E0OJOsonQPjAKrEk=; b=k10MWXDFqIys9vC80D92HRGBK3GUv5ZoEoJKrCNFGEk8xaQw33njJe/B2u/2pVqucP a1Z0DoXBmpzva9zwkXqjbywdU2OtQ+c4HhhZYD00qHcuPIUgUZ2k8CNeaQUqivFCBJpH gqxrflpYOjHFxwok8bZOaXXTNpiJBV4dMcGu3TereiAO/Fj6KD0DfCmFZilWK+oaby8k 5uouI5gtJXKHgVOTuvr0XSr+XnpXoxMsBii/mmAhSzdpw01dGFUTokTdc5uQy3ekrXEw 1MQ0XUK9aKKAksa4BUJdVIGoCOlgTHjtwJnzbZXtUdpp1kjjlMlXt0Kyc2yv1eWxE65/ 3Zaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=vzRhRNNrJSdjTI894s6ytv8kya/E0OJOsonQPjAKrEk=; b=JOg8358rr7HGQSUwZ9yf/SK+vlwdj0VyoSJAejnYbCQ2JCxfsNB5fQ7yGw/z1WCT5u 9EXG29m6QWXnbfxtN8gs5fhHNiYVpHwgOlwXXK4f5HThf5vC80z+Z4QqnWGvOuj+MUg0 GZG/+vGEkeD5yl+jyvafauMiITfnW97Ml6Lw/mh0qykJr4pmMJJhxV0kCL2LlQN4MEXs WO6dvIcl0GTYlpz2JZJn54/ti833xtdlDyRqldSHaYtPPY922JMiRDNxN9Om9ZHCvKqq mb0DEoZkiQMoT3RN98xzF/OURMGwe+SCNgxEQ2wsMOlKiV6vvm43i6dA64zXkQ+WgCJP PoRg== X-Gm-Message-State: ANoB5pmiZVfsMN4RJvRehq8fI5akyiEi+dQ7dF6AaRYCdrE1ouaXj1Lf 7jST6L3ejmhhupvbwoAc+JOxs/gofg4S3qTdemxu+w== X-Google-Smtp-Source: AA0mqf5BUsUFFVsk40GthE0vFMP4dch9mqdNz9VU+kaTffaQfQK8XDdrZKMbP1FNw1zm9JnkyCSsycC3362D61fmHrM= X-Received: by 2002:a05:6512:3b85:b0:4b1:753b:e671 with SMTP id g5-20020a0565123b8500b004b1753be671mr1290761lfv.441.1668711445744; Thu, 17 Nov 2022 10:57:25 -0800 (PST) MIME-Version: 1.0 References: <20221113204858.4062163-1-philipp.tomsich@vrull.eu> In-Reply-To: From: Philipp Tomsich Date: Thu, 17 Nov 2022 19:57:14 +0100 Message-ID: Subject: Re: [PATCH] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs To: Andrew Pinski Cc: gcc-patches@gcc.gnu.org, Christoph Muellner , Kito Cheng , Vineet Gupta , Jeff Law , Palmer Dabbelt Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, 17 Nov 2022 at 19:28, Andrew Pinski wrote: > > On Thu, Nov 17, 2022 at 10:25 AM Andrew Pinski wrote: > > > > On Sun, Nov 13, 2022 at 12:51 PM Philipp Tomsich > > wrote: > > > > > > Use Zbs when generating a sequence for "if ((a & twobits) == singlebit) ..." > > > that can be expressed as bexti + bexti + andn. > > > > Can't you also handle if ((a & twobits) == 0) case doing a similar thing. > > That is: > > two bexti + and and then compare against zero which is exactly the > > same # of instructions as the above case. We can form any 2-bit constant with BSETI + BSETI (no OR required). So no explicit support for that case will be required (as a AND + BEQ will be formed anyway). > > > > > > > > > > gcc/ChangeLog: > > > > > > * config/riscv/bitmanip.md (*branch_mask_twobits_equals_singlebit): > > > Handle "if ((a & T) == C)" using Zbs, when T has 2 bits set and C has one > > > of these tow bits set. > > > * config/riscv/predicates.md (const_twobits_operand): New predicate. > > > > > > gcc/testsuite/ChangeLog: > > > > > > * gcc.target/riscv/zbs-if_then_else-01.c: New test. > > > > > > Signed-off-by: Philipp Tomsich > > > --- > > > > > > gcc/config/riscv/bitmanip.md | 42 +++++++++++++++++++ > > > gcc/config/riscv/predicates.md | 5 +++ > > > .../gcc.target/riscv/zbs-if_then_else-01.c | 20 +++++++++ > > > 3 files changed, 67 insertions(+) > > > create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-if_then_else-01.c > > > > > > diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md > > > index 7a8f4e35880..2cea394671f 100644 > > > --- a/gcc/config/riscv/bitmanip.md > > > +++ b/gcc/config/riscv/bitmanip.md > > > @@ -690,3 +690,45 @@ > > > "TARGET_ZBS" > > > [(set (match_dup 0) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2))) > > > (set (match_dup 0) (xor:X (match_dup 0) (const_int 1)))]) > > > + > > > +;; IF_THEN_ELSE: test for 2 bits of opposite polarity > > > +(define_insn_and_split "*branch_mask_twobits_equals_singlebit" > > > + [(set (pc) > > > + (if_then_else (match_operator 1 "equality_operator" > > > + [(and:X (match_operand:X 2 "register_operand" "r") > > > + (match_operand:X 3 "const_twobits_operand" "i")) > > > + (match_operand:X 4 "single_bit_mask_operand" "i")]) > > > + (label_ref (match_operand 0 "" "")) > > > + (pc))) > > > + (clobber (match_scratch:X 5 "=&r")) > > > + (clobber (match_scratch:X 6 "=&r"))] > > > + "TARGET_ZBS && TARGET_ZBB && !SMALL_OPERAND (INTVAL (operands[3]))" > > Is there a reason why you can't do this at expand time? I think there > are recent patches floating around which is supposed to help with that > case and the RISCV backend just needs to plug into that infrastructure > too. I may have missed the specific patches you refer to (pointer to the relevant series appreciated). However, if we move this to expand-time, then ifcvt.cc will run after (and may form this case once our support for polarity-reversed bit tests is merged). So there is good reason to have this pattern. > Thanks, > Andrew Pinski > > > > + "#" > > > + "&& reload_completed" > > > + [(set (match_dup 5) (zero_extract:X (match_dup 2) > > > + (const_int 1) > > > + (match_dup 8))) > > > + (set (match_dup 6) (zero_extract:X (match_dup 2) > > > + (const_int 1) > > > + (match_dup 9))) > > > + (set (match_dup 6) (and:X (not:X (match_dup 6)) (match_dup 5))) > > > + (set (pc) (if_then_else (match_op_dup 1 [(match_dup 6) (const_int 0)]) > > > + (label_ref (match_dup 0)) > > > + (pc)))] > > > +{ > > > + unsigned HOST_WIDE_INT twobits_mask = UINTVAL (operands[3]); > > > + unsigned HOST_WIDE_INT singlebit_mask = UINTVAL (operands[4]); > > > + > > > + /* Make sure that the reference value has one of the bits of the mask set */ > > > + if ((twobits_mask & singlebit_mask) == 0) > > > + FAIL; > > > + > > > + int setbit = ctz_hwi (singlebit_mask); > > > + int clearbit = ctz_hwi (twobits_mask & ~singlebit_mask); > > > + > > > + operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == NE ? EQ : NE, > > > + mode, operands[6], GEN_INT(0)); > > > + > > > + operands[8] = GEN_INT (setbit); > > > + operands[9] = GEN_INT (clearbit); > > > +}) > > > diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md > > > index 490bff688a7..6e34829a59b 100644 > > > --- a/gcc/config/riscv/predicates.md > > > +++ b/gcc/config/riscv/predicates.md > > > @@ -321,6 +321,11 @@ > > > (and (match_code "const_int") > > > (match_test "popcount_hwi (~UINTVAL (op)) == 2"))) > > > > > > +;; A CONST_INT operand that has exactly two bits set. > > > +(define_predicate "const_twobits_operand" > > > + (and (match_code "const_int") > > > + (match_test "popcount_hwi (UINTVAL (op)) == 2"))) > > > + > > > ;; A CONST_INT operand that fits into the unsigned half of a > > > ;; signed-immediate after the top bit has been cleared. > > > (define_predicate "uimm_extra_bit_operand" > > > diff --git a/gcc/testsuite/gcc.target/riscv/zbs-if_then_else-01.c b/gcc/testsuite/gcc.target/riscv/zbs-if_then_else-01.c > > > new file mode 100644 > > > index 00000000000..d249a841ff9 > > > --- /dev/null > > > +++ b/gcc/testsuite/gcc.target/riscv/zbs-if_then_else-01.c > > > @@ -0,0 +1,20 @@ > > > +/* { dg-do compile } */ > > > +/* { dg-options "-march=rv64gc_zbb_zbs -mabi=lp64" } */ > > > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */ > > > > It would be useful to add a rv32 testcase too. > > > > Thanks, > > Andrew Pinski > > > > > + > > > +void g(); > > > + > > > +void f1 (long a) > > > +{ > > > + if ((a & ((1ul << 33) | (1 << 4))) == (1ul << 33)) > > > + g(); > > > +} > > > + > > > +void f2 (long a) > > > +{ > > > + if ((a & 0x12) == 0x10) > > > + g(); > > > +} > > > + > > > +/* { dg-final { scan-assembler-times "bexti\t" 2 } } */ > > > +/* { dg-final { scan-assembler-times "andn\t" 1 } } */ > > > -- > > > 2.34.1 > > >