From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by sourceware.org (Postfix) with ESMTPS id 29D3D3857B8B for ; Wed, 15 Jun 2022 08:56:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 29D3D3857B8B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-wm1-x331.google.com with SMTP id i81-20020a1c3b54000000b0039c76434147so744791wma.1 for ; Wed, 15 Jun 2022 01:56:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=6WJ19CC5fsj32e0VCkM5Xkr0VdmJjr372wP+Ui2HLsI=; b=l9QeQCqgTF7MTyfQ5F9looxLuKhFSz2+55GLOFn1w5ENTTmQuqAN8FvPc0x8nRPOI1 Bp1vlyJJsAFuzoROplBYys3uhfopCIBrGTbCqf0i3R+QN92P+BEkS63pTFvi1NeU8xBy 4EMcTlV22jVlUy2Ish2DnFIQEPcBZiY5GZjtrUjxZmLSYLdHeSjB2XY2INPcQpo/UX3b PDe6k3Yw7z0vszaOoGp6X/HHniarrLDzHVjmMNckV19cwz2cXTda/dKgodRZnDkOVqMa Zpa9KriK7o4o7pJZfmaMW/NvYci7tturgsa7UKsiNmILFHU2SPnBd4Bec/+BMu3QeygO 4UJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=6WJ19CC5fsj32e0VCkM5Xkr0VdmJjr372wP+Ui2HLsI=; b=GrFdcwP6Srd1uqWHzVwfob6rebrP0+Di7CJ/KzKUItikp5IkUX3wybMAJTk9d3Q2pr KQFVRgQCss/FfyqwSxi6fmqdTeCNy5zcxsPcvnRtDRaR5D1PoL/2hKHh4hQ8fQPNxIfx tjqMyU0Nni/+bhqyE19DqWTP/7mXfj4vOpWCIqiKwJvWfMPDrQFcofi0T2jZmDKM43p8 E8MGC6CKUCzMqNHvy9EQDwbqv+RVB2paKKD5jCsKWNRt2i7iHjWWK4QRTqIL+CS+PG/E O2td0l7Rq+1D6AA0nk2PP+g8hAW931nSI4dLkCnubYOxJrtnYhSFf85gpCPeFu3+l+3Z f0WA== X-Gm-Message-State: AOAM530+VzJv9w5vVlJDrxjHB1Io6mmRU35tZvorMGcQ72sAfQ7ktEFt iqKJuqOAXsEVF83CcitKftXC45S2CKyH0+Afb8bhSg== X-Google-Smtp-Source: ABdhPJxNkixDF8XpMaEQiPNWuDMx3rPpu3imn7YbcK3SyySAc/hRxKLzUuqdYkhXk/i08wl92zoRC51SOQyJ0bxeZZI= X-Received: by 2002:a7b:c456:0:b0:39c:5d1e:661d with SMTP id l22-20020a7bc456000000b0039c5d1e661dmr8628148wmi.15.1655283409918; Wed, 15 Jun 2022 01:56:49 -0700 (PDT) MIME-Version: 1.0 References: <20220613132042.2972081-1-christoph.muellner@vrull.eu> <20220613132042.2972081-2-christoph.muellner@vrull.eu> In-Reply-To: From: Philipp Tomsich Date: Wed, 15 Jun 2022 10:56:38 +0200 Message-ID: Subject: Re: [PATCH 2/2] riscv-cores.def: Add Allwinner D1 core To: =?UTF-8?Q?Christoph_M=C3=BCllner?= Cc: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Andrew Waterman Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-10.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Jun 2022 08:56:52 -0000 Please update the commit message to reflect this. On Wed, 15 Jun 2022 at 10:56, Christoph M=C3=BCllner wrote: > > On Wed, Jun 15, 2022 at 10:39 AM Philipp Tomsich > wrote: > > > > On Wed, 15 Jun 2022 at 10:30, Christoph M=C3=BCllner > > wrote: > > > > > > On Mon, Jun 13, 2022 at 3:20 PM Christoph Muellner > > > wrote: > > > > > > > > From: Christoph M=C3=BCllner > > > > > > > > This adds Allwinner's D1 to the list of known cores. > > > > The Allwinner includes a single-core XuanTie C906 and is available > > > > for quite some time. Note, that the tuning struct for the C906 > > > > is already part of GCC. > > > > > > > > gcc/ChangeLog: > > > > > > > > * config/riscv/riscv-cores.def (RISCV_CORE): Add "allwinner= -d1". > > > > > > > > Signed-off-by: Christoph M=C3=BCllner > > > > --- > > > > gcc/config/riscv/riscv-cores.def | 2 ++ > > > > 1 file changed, 2 insertions(+) > > > > > > > > diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/ri= scv-cores.def > > > > index 60bcadbb034..dd97ece376f 100644 > > > > --- a/gcc/config/riscv/riscv-cores.def > > > > +++ b/gcc/config/riscv/riscv-cores.def > > > > @@ -44,4 +44,6 @@ RISCV_CORE("sifive-s76", "rv64imafdc", "sifi= ve-7-series") > > > > RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series") > > > > RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series") > > > > > > > > +RISCV_CORE("thead-c906", "rv64imafdc", "thead-c906") > > > > > > > > > I just realized that this lacks a test case (other -mcpu=3D... entrie= s have one). > > > And the core string is wrong (s/thead-c906/allwinner-d1). > > > I will send a v2. > > > > Is the D1 different from the C906? I thought the D1 was using the C906 = core? > > Yes, that's the case. > I'll stick with "thead-c906" as core name for the v2. > Thanks!