From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yb1-xb2c.google.com (mail-yb1-xb2c.google.com [IPv6:2607:f8b0:4864:20::b2c]) by sourceware.org (Postfix) with ESMTPS id A59F33854164 for ; Thu, 6 Oct 2022 10:40:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A59F33854164 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-yb1-xb2c.google.com with SMTP id b145so1787386yba.0 for ; Thu, 06 Oct 2022 03:40:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=to:subject:message-id:date:from:in-reply-to:references:mime-version :from:to:cc:subject:date; bh=HR5G6aeV9cfMN0FS0kvYhEub3lreIHK2TwE/wli0W08=; b=Z0JzaxzkcKRs77iZozTlj8+5lbSHBLTkrbbNtB5un7ZJXPAyqi9wwAa0frlpDLzp6g bzvt//N9tDd/d6kfznlNLQCMi86aVl/4TIrM5reuXxhWD3UKjNtlbkqi2PCS3bH1NtIf wrYuhKvfVd/sM52HJUqZpn7n7Ony0WZLj4CXd3tc9zTG+HTqtQ783gkyKj2iGZGZeaYT xGx/SXtWX8HnK+8bTkktgUvJQyuo5/ZatE5Rg7wQsV3MWzvvzFfGC1JRea1nrzYPcir2 P2cOSit02mi8xfA4qT0tsR8MswFm+9Ip5xEIH2FdEgauyQFB159X8EOi1YMrk0A3jJ2g AKyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=to:subject:message-id:date:from:in-reply-to:references:mime-version :x-gm-message-state:from:to:cc:subject:date; bh=HR5G6aeV9cfMN0FS0kvYhEub3lreIHK2TwE/wli0W08=; b=YerG/l8qSKi+vzTMdTPitAvHoyYBMgdwwNy3rFjeha3RTrxyCtgS2HK9yMMWKKllIN 1hZWN6cMpf8AAQocONRgWGmEMUdCib2Ep53S7QjXcJcUhCvQ2SsH4t7RJBlxcUQs72vc m+c5Z6vreeLAv55OEAIcqqAdWuxVjtiiqr2GpZ+gOPThf1O48eqfsGOR2Lp9cRYvtNT7 +WpjouS8dtuUOsBhq8Ugm8mlu/3p2k4k1xY47j+vgxDqZvyAtJRXWAkgG9uQShPkLksP Yh0F14Yc16xcI3TP536nGAWKjpr3TD7V/6kwWpqz1bQK2loMafrKXhq5gw8PMTnPuhuM tjrw== X-Gm-Message-State: ACrzQf1RziOxVidFspH3oJCuxMZCMUvEc89YX9XRvsKpSrlOSL6pNwd9 e5CLQsU67g1R0hhP6lyP7aVs218Cayfp+6SZXiCPUw== X-Google-Smtp-Source: AMsMyM59meJMauaL2dNm+ZSobjJfGX1fEPF6mx17wDZDNotjK8d74LNZI5A2I83u4bzWhmBEYsRviYcPDpVvDlFtRy0= X-Received: by 2002:a25:dcc9:0:b0:6be:3139:c32f with SMTP id y192-20020a25dcc9000000b006be3139c32fmr4191303ybe.517.1665052806022; Thu, 06 Oct 2022 03:40:06 -0700 (PDT) MIME-Version: 1.0 References: <20221006092951.607412-1-philipp.tomsich@vrull.eu> In-Reply-To: From: Philipp Tomsich Date: Thu, 6 Oct 2022 12:39:55 +0200 Message-ID: Subject: Re: [PATCH v2] aarch64: update Ampere-1 core definition To: Philipp Tomsich , gcc-patches@gcc.gnu.org, Tamar Christina , Christoph Muellner , richard.sandiford@arm.com Content-Type: multipart/alternative; boundary="000000000000091f1705ea5b5195" X-Spam-Status: No, score=-8.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,HTML_MESSAGE,JMQ_SPF_NEUTRAL,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000091f1705ea5b5195 Content-Type: text/plain; charset="UTF-8" Applied to master. Thanks! Philipp. On Thu, 6 Oct 2022 at 12:07, Richard Sandiford wrote: > Philipp Tomsich writes: > > This brings the extensions detected by -mcpu=native on Ampere-1 systems > > in sync with the defaults generated for -mcpu=ampere1. > > > > Note that some early kernel versions on Ampere1 may misreport the > > presence of PAUTH and PREDRES (i.e., -mcpu=native will add 'nopauth' > > and 'nopredres'). > > > > gcc/ChangeLog: > > > > * config/aarch64/aarch64-cores.def (AARCH64_CORE): Update > > Ampere-1 core entry. > > > > Signed-off-by: Philipp Tomsich > > OK, thanks. > > > Ok for backport? > > Yeah. I'll try to backport the RCPC change soon -- think it would > be best to get that in first. > > Richard > > > > > Changes in v2: > > - Removed explicit RCPC, as the feature is now implicitly included > > in the 8.3 feature definition. > > > > gcc/config/aarch64/aarch64-cores.def | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/gcc/config/aarch64/aarch64-cores.def > b/gcc/config/aarch64/aarch64-cores.def > > index b50628d6b51..e9a4b622be0 100644 > > --- a/gcc/config/aarch64/aarch64-cores.def > > +++ b/gcc/config/aarch64/aarch64-cores.def > > @@ -69,7 +69,7 @@ AARCH64_CORE("thunderxt81", thunderxt81, > thunderx, V8A, (CRC, CRYPTO), thu > > AARCH64_CORE("thunderxt83", thunderxt83, thunderx, V8A, (CRC, > CRYPTO), thunderx, 0x43, 0x0a3, -1) > > > > /* Ampere Computing ('\xC0') cores. */ > > -AARCH64_CORE("ampere1", ampere1, cortexa57, V8_6A, (), ampere1, 0xC0, > 0xac3, -1) > > +AARCH64_CORE("ampere1", ampere1, cortexa57, V8_6A, (F16, RNG, AES, > SHA3), ampere1, 0xC0, 0xac3, -1) > > /* Do not swap around "emag" and "xgene1", > > this order is required to handle variant correctly. */ > > AARCH64_CORE("emag", emag, xgene1, V8A, (CRC, CRYPTO), > emag, 0x50, 0x000, 3) > --000000000000091f1705ea5b5195--