From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by sourceware.org (Postfix) with ESMTPS id 1E7F13858D3C for ; Mon, 14 Nov 2022 21:14:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 1E7F13858D3C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lf1-x12b.google.com with SMTP id bp15so21368001lfb.13 for ; Mon, 14 Nov 2022 13:14:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=+t1PL+Pjv0+evCvNGkLhr2NwKKYT4iC9jBqYyJDZM1I=; b=LhFHQw6iUtyZLuOZrpHd2VlaoUyasJKCHdU0UxKKCRFJk2vLURnOlqzoaPhgaPjJJ6 f4w43ibgIxC0uyetNJjASVyjELgAvp3IqDnbGnH4kVnHVyhcsP5kfveAhcwS8qad0RsZ eSaoLvrhpRVQWcE2WQz3ytXGnNy+SJGiBgs+z6a3byjzC6WOxHMOwv70t8BayIbWmR0y bWR4bMVuRfTpoSe4Ecoybi2CynppwSnPNm/YVWHX9gNsoi1VKBrxy0kKDE7wxZ26sZac DisfWZfDbbmmM0jbCJWWpZqI5Hf6UbedJmJg4C+LK4S5V5LNhAh+hblgY9Fdu8eiU+dW 3ccQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+t1PL+Pjv0+evCvNGkLhr2NwKKYT4iC9jBqYyJDZM1I=; b=F0rbPlTNqikyCcQGo8JlAE60vS1bfZbvxaAziTQey2S1eJCoNfT/BhCNJm1K6zbuLr ANbaT2Rm3WWeBHU2UWMK9vzEFaUMjwR7aajhcaFBYuZKiZ3EWAYtEdXUKjcVNyWtCT4s eYSm4gGNdLnZedi/t1y3mNo4/GudKDweHHgbpVf9x98TtLPo666qoctC9fsw0XHsPXoS JBjtrnU4StMVr3wo6hLS23rEqEfMPOiSTylvyNiGZ7lYLMcU4hnlCqxAceS/dBz9rvvw dwG1nkCAorl+q8hrDdJyjg91I73P3srn8/PoH4oCdHvNR7YNgs0oBMUSmvE625D6susk wWYA== X-Gm-Message-State: ANoB5pmNHNIj1VPeqmsw7lWnB2qkHiZQfrFBkBc8qGYkk9Ab6FOkRmOM LCCk5BDjr3k2aPOizXpnZ4XDMizwU3QaOgXmPSwpYw== X-Google-Smtp-Source: AA0mqf6wSo19dG5deiZYBhOeYQ4emen1OkxadkwAP806vGLRzR4vaqVPEWbZ44g45GcxZVqkpM31AINYxdL07s7tTns= X-Received: by 2002:ac2:47ea:0:b0:4b4:1324:6ed3 with SMTP id b10-20020ac247ea000000b004b413246ed3mr4540561lfp.19.1668460487530; Mon, 14 Nov 2022 13:14:47 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Philipp Tomsich Date: Mon, 14 Nov 2022 22:14:35 +0100 Message-ID: Subject: Re: [PATCH v2 0/2] Basic support for the Ventana VT1 w/ instruction fusion To: Palmer Dabbelt Cc: gcc-patches@gcc.gnu.org, Vineet Gupta , jlaw@ventanamicro.com, Kito Cheng , christoph.muellner@vrull.eu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,JMQ_SPF_NEUTRAL,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, 14 Nov 2022 at 21:58, Palmer Dabbelt wrote: > > On Mon, 14 Nov 2022 12:03:38 PST (-0800), philipp.tomsich@vrull.eu wrote: > > On Mon, 14 Nov 2022 at 21:00, Palmer Dabbelt wrot= e: > >> > >> On Sun, 13 Nov 2022 12:48:22 PST (-0800), philipp.tomsich@vrull.eu wro= te: > >> > > >> > This series provides support for the Ventana VT1 (a 4-way superscala= r > >> > rv64gc_zba_zbb_zbc_zbs_zifenci_xventanacondops core) including suppo= rt > >> > for the supported instruction fusion patterns. > >> > > >> > This includes the addition of the fusion-aware scheduling > >> > infrastructure for RISC-V and implements idiom recognition for the > >> > fusion patterns supported by VT1. > >> > > >> > Note that we don't signal support for XVentanaCondOps at this point, > >> > as the XVentanaCondOps support is in-flight separately. Changing th= e > >> > defaults for VT1 can happen late in the cycle, so no need to link th= e > >> > two different changesets. > >> > > >> > Changes in v2: > >> > - Rebased and changed over to .rst-based documentation > >> > - Updated to catch more fusion cases > >> > - Signals support for Zifencei > >> > > >> > Philipp Tomsich (2): > >> > RISC-V: Add basic support for the Ventana-VT1 core > >> > RISC-V: Add instruction fusion (for ventana-vt1) > >> > > >> > gcc/config/riscv/riscv-cores.def | 3 + > >> > gcc/config/riscv/riscv-opts.h | 2 +- > >> > gcc/config/riscv/riscv.cc | 233 +++++++++++++++= +++ > >> > .../risc-v-options.rst | 5 +- > >> > 4 files changed, 240 insertions(+), 3 deletions(-) > >> > >> I guess we never really properly talked about this on the GCC mailing > >> lists, but IMO it's fine to start taking code for designs that have be= en > >> announced under the assumption that if the hardware doesn't actually > >> show up according to those timelines that it will be assumed to have > >> never existed and thus be removed more quickly than usual. > >> > >> That said, I can't find anything describing that the VT-1 exists aside > >> from these patches. Is there anything that describes this design and > >> when it's expected to be available? > > > > I have to defer to Jeff on this one. > > Looks like you already committed it, though: > > 991cfe5b30c ("RISC-V: Add instruction fusion (for ventana-vt1)") > b4fca4fc70d ("RISC-V: Add basic support for the Ventana-VT1 core") > > We talked about this multiple times and I thought you were on board with > the proposed "hardware needs to be announced" changes, did I > misunderstand that? Sorry =E2=80=94 I had assumed that the "basic support" changes were agreed upon between you and Jeff, given that Jeff had given the OK. My position is still the same as discussed at LPC that "hardware needs to be announced". Thanks, Philipp.