From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by sourceware.org (Postfix) with ESMTPS id 448F43858409 for ; Fri, 21 Jul 2023 18:15:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 448F43858409 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ed1-x52f.google.com with SMTP id 4fb4d7f45d1cf-51e2a6a3768so2933101a12.0 for ; Fri, 21 Jul 2023 11:15:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1689963353; x=1690568153; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=GzF6jGErGGWuecHkm2ZdHQnFV3zkbaF3S+i3DotRtL4=; b=pNYjTsXEG71ivQhUAR6B073pim8RK3jyP1BLhzJ55VGODn+uL7O5cYyz1GyXoUgtIW cFs9A7XPl9S42tOAAzc6Cxbgi12mbLu1TFEDxdDWYtzO1WsWcaWIZ5qusUVS18t7axO+ 2ZyAKRyEn3DeGR25jaFGpy9uQEeux7nC+kB+a5gfv5ucVLlFRJetm1Zo0T+qzJMqaCGg QZSD2fCA0PwS85sFsA/rJH3LMAHzihqofn5xr5hXWZUgodP2okKvEStQeUFb15dI0DUa YYGvYgZHTOehfB5jnWOLPtM/yrDqv92aYUuakBrNI2f+Ddc+j34RsGeopX9rXdPlNw8p 0gUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689963353; x=1690568153; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=GzF6jGErGGWuecHkm2ZdHQnFV3zkbaF3S+i3DotRtL4=; b=LfcZW48hEdkbEeaRAybBQqlZVaRE99oNZY2xXL4F7wvPpBPOp/YYH+i5/bh6iBUsHZ XFxRbsfdJhSlQr+y1YsMGIG2nkic2SHjx4QSkRKVsn3VksWKZnnfQ5m8U/VF1Ey+2zqs 0SzyyPdOYvqSm4mHNKFWkW81o8WicPZPbsrqfl/xdfn1h6m6S7fVi32Xefx8yHHBA8Vc 7bMiRXedccIQ1HQ18lPYztoGRpNc7ckxnqaDezo7/5WSVYfOM6/kd4hyzrzFY+HzUdTR PQ+M34seiHzbMAlWrziYmBqcClA3p3kfclaB7sgAt1iz1Q8DKQH4omKNIvUxvBjq1sYk LyJA== X-Gm-Message-State: ABy/qLaAs8tqi88fAseUNgYWjhTlJklNnEqdgBtrhbhtr7B366coYkSy SzTjJQurQuxEfg2/cy2FCPZhJ0qigW1BD9pKJBuv9w== X-Google-Smtp-Source: APBJJlGBO+Tz/JDFdCyb324hWzHcTRGVxvycmx8Cog+bCM65lZya0VLSTn7DSYuwrNKIsgi6i5eDGA/YjYRnS48H29E= X-Received: by 2002:a50:fa8d:0:b0:51d:a02d:f8fe with SMTP id w13-20020a50fa8d000000b0051da02df8femr2057059edr.29.1689963353084; Fri, 21 Jul 2023 11:15:53 -0700 (PDT) MIME-Version: 1.0 References: <20230721175552.2693295-1-vineetg@rivosinc.com> In-Reply-To: <20230721175552.2693295-1-vineetg@rivosinc.com> From: Philipp Tomsich Date: Fri, 21 Jul 2023 20:15:41 +0200 Message-ID: Subject: Re: [PATCH] RISC-V: optim const DF +0.0 store to mem [PR/110748] To: Vineet Gupta Cc: gcc-patches@gcc.gnu.org, Manolis Tsamis , kito.cheng@gmail.com, Jeff Law , Palmer Dabbelt , gnu-toolchain@rivosinc.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Fri, 21 Jul 2023 at 19:56, Vineet Gupta wrote: > > DF +0.0 is bitwise all zeros so int x0 store to mem can be used to optimize it. > > void zd(double *) { *d = 0.0; } > > currently: > > | fmv.d.x fa5,zero > | fsd fa5,0(a0) > | ret > > With patch > > | sd zero,0(a0) > | ret > This came to light when testing the in-flight f-m-o patch where an ICE > was gettinh triggered due to lack of this pattern but turns out this typo: "gettinh" -> "getting" > is an independent optimization of its own [1] > > [1] https://gcc.gnu.org/pipermail/gcc-patches/2023-July/624857.html > > Apparently this is a regression in gcc-13, introduced by commit > ef85d150b5963 ("RISC-V: Enable TARGET_SUPPORTS_WIDE_INT") and the fix > thus is a partial revert of that change. Should we add a "Fixes: "? > Ran thru full multilib testsuite, there was 1 false failure due to > random string "lw" appearing in lto build assembler output, > which is also fixed in the patch. > > gcc/Changelog: PR target/110748 > > * config/riscv/predicates.md (const_0_operand): Add back > const_double. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/pr110748-1.c: New Test. > * gcc.target/riscv/xtheadfmv-fmv.c: Add '\t' around test > patterns to avoid random string matches. > > Signed-off-by: Vineet Gupta > --- > gcc/config/riscv/predicates.md | 2 +- > gcc/testsuite/gcc.target/riscv/pr110748-1.c | 10 ++++++++++ > gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c | 8 ++++---- > 3 files changed, 15 insertions(+), 5 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/pr110748-1.c > > diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md > index 5a22c77f0cd0..9db28c2def7e 100644 > --- a/gcc/config/riscv/predicates.md > +++ b/gcc/config/riscv/predicates.md > @@ -58,7 +58,7 @@ > (match_test "INTVAL (op) + 1 != 0"))) > > (define_predicate "const_0_operand" > - (and (match_code "const_int,const_wide_int,const_vector") > + (and (match_code "const_int,const_wide_int,const_double,const_vector") > (match_test "op == CONST0_RTX (GET_MODE (op))"))) > > (define_predicate "const_1_operand" > diff --git a/gcc/testsuite/gcc.target/riscv/pr110748-1.c b/gcc/testsuite/gcc.target/riscv/pr110748-1.c > new file mode 100644 > index 000000000000..2f5bc08aae72 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/pr110748-1.c > @@ -0,0 +1,10 @@ > +/* { dg-do compile } */ > +/* { dg-require-effective-target hard_float } */ > +/* { dg-options "-march=rv64g -mabi=lp64d -O2" } */ > + > + > +void zd(double *d) { *d = 0.0; } > +void zf(float *f) { *f = 0.0; } > + > +/* { dg-final { scan-assembler-not "\tfmv\\.d\\.x\t" } } */ > +/* { dg-final { scan-assembler-not "\tfmv\\.s\\.x\t" } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c > index 1036044291e7..89eb48bed1b9 100644 > --- a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c > +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c > @@ -18,7 +18,7 @@ d2ll (double d) > /* { dg-final { scan-assembler "th.fmv.hw.x" } } */ > /* { dg-final { scan-assembler "fmv.x.w" } } */ > /* { dg-final { scan-assembler "th.fmv.x.hw" } } */ > -/* { dg-final { scan-assembler-not "sw" } } */ > -/* { dg-final { scan-assembler-not "fld" } } */ > -/* { dg-final { scan-assembler-not "fsd" } } */ > -/* { dg-final { scan-assembler-not "lw" } } */ > +/* { dg-final { scan-assembler-not "\tsw\t" } } */ > +/* { dg-final { scan-assembler-not "\tfld\t" } } */ > +/* { dg-final { scan-assembler-not "\tfsd\t" } } */ > +/* { dg-final { scan-assembler-not "\tlw\t" } } */ > -- > 2.34.1 >