From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by sourceware.org (Postfix) with ESMTPS id 70EEA3858D1E for ; Mon, 14 Nov 2022 21:28:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 70EEA3858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lf1-x135.google.com with SMTP id be13so21497424lfb.4 for ; Mon, 14 Nov 2022 13:28:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=ZIs0gnG2MkItcYFucLAC+hHfvRE8bdfxHm9Adb+UD/8=; b=b+M6pv6C38tBlilJRqr5OuqzIGNQa93n7RKOPuEksmCHQ2PCRYHgK5cGDD7GJuF6jx KsP1/HX5gbBFC/ey7DEtmX/eUMqXXrfHfgkiuPwXG9zDx9lHJiQ+7BPdGovO9i4SBnKX Tn3W5PzIhAtKk2cKEPup1UDvbz4bZdaBoxoG4tppQwBmiHx3etHYDVHG69eKJa5SGQfZ iqUA9uBBY2m4gGU3UnvN/hdhk1POsSNiOPpcd/drlz1GZuGi2ZG5Ep6JPUv7pSw4bhG5 L4vmrCKQuKdpWKehzv8u3ZLnUGlQ+X9dPDCcwbxzyykwcVM7eCuGrj80ZDhfi7d1fKy+ Cy/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=ZIs0gnG2MkItcYFucLAC+hHfvRE8bdfxHm9Adb+UD/8=; b=lbbaF86IgVx6THzB4l9XExS/+quD9aUwRuOc9CJkenoqmaR3UzCXZe3oV1FFn/WFqr nUJ2UGEYCDy5yCkSnWyGwm7L67br9Qa7DHw1TBrOFfH0dp5cM9AkwpCZ3FqCoXo1sM10 74HHGn/t3qArJzpyGLyR2tuDjTnuYzInLR7SO+YQfxyJpyt9NU6OIzvvNvbIWf1LTikl WM6DOZRzyONWWo5159ZCrBgFiTHzds6OW2SKyJmV+9WUVFv9q3CKEpBFG9kQkgo4mb+P ydhNSRRYFxO2ljNekoTMnTS9yMqjk7fFj+Jcy50/aYADqACRwKd+eQLwmaZxsUCiPNGD SsbA== X-Gm-Message-State: ANoB5pkthiEXugRGGJQG09QXe4fapIKHHmzZKO9z7QQM0tNEP40RbeM8 o8K6yTNvk+M6exi6orBEggOXuS6NNfd7j//IhdAlhw== X-Google-Smtp-Source: AA0mqf5WPS9Gv7RiA8MHRChfoQNw1/QjRnzVke6Dz8tN0DU6c6RlLDrV+EBP/0hHgvfFY/PvdciXMVwauip90tRRCiM= X-Received: by 2002:a05:6512:3497:b0:4b1:753b:e671 with SMTP id v23-20020a056512349700b004b1753be671mr4447590lfr.441.1668461314385; Mon, 14 Nov 2022 13:28:34 -0800 (PST) MIME-Version: 1.0 References: <9161a76a-4181-e5f9-620e-c1c1195c9954@gmail.com> In-Reply-To: <9161a76a-4181-e5f9-620e-c1c1195c9954@gmail.com> From: Philipp Tomsich Date: Mon, 14 Nov 2022 22:28:23 +0100 Message-ID: Subject: Re: [PATCH v2 0/2] Basic support for the Ventana VT1 w/ instruction fusion To: Jeff Law Cc: Palmer Dabbelt , gcc-patches@gcc.gnu.org, Vineet Gupta , jlaw@ventanamicro.com, Kito Cheng , christoph.muellner@vrull.eu Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,JMQ_SPF_NEUTRAL,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Jeff, On Mon, 14 Nov 2022 at 22:23, Jeff Law wrote: > > > On 11/14/22 13:00, Palmer Dabbelt wrote: > > On Sun, 13 Nov 2022 12:48:22 PST (-0800), philipp.tomsich@vrull.eu wrote: > >> > >> This series provides support for the Ventana VT1 (a 4-way superscalar > >> rv64gc_zba_zbb_zbc_zbs_zifenci_xventanacondops core) including support > >> for the supported instruction fusion patterns. > >> > >> This includes the addition of the fusion-aware scheduling > >> infrastructure for RISC-V and implements idiom recognition for the > >> fusion patterns supported by VT1. > >> > >> Note that we don't signal support for XVentanaCondOps at this point, > >> as the XVentanaCondOps support is in-flight separately. Changing the > >> defaults for VT1 can happen late in the cycle, so no need to link the > >> two different changesets. > >> > >> Changes in v2: > >> - Rebased and changed over to .rst-based documentation > >> - Updated to catch more fusion cases > >> - Signals support for Zifencei > >> > >> Philipp Tomsich (2): > >> RISC-V: Add basic support for the Ventana-VT1 core > >> RISC-V: Add instruction fusion (for ventana-vt1) > >> > >> gcc/config/riscv/riscv-cores.def | 3 + > >> gcc/config/riscv/riscv-opts.h | 2 +- > >> gcc/config/riscv/riscv.cc | 233 ++++++++++++++++++ > >> .../risc-v-options.rst | 5 +- > >> 4 files changed, 240 insertions(+), 3 deletions(-) > > > > I guess we never really properly talked about this on the GCC mailing > > lists, but IMO it's fine to start taking code for designs that have > > been announced under the assumption that if the hardware doesn't > > actually show up according to those timelines that it will be assumed > > to have never existed and thus be removed more quickly than usual. > Absolutely. I have zero interest in carrying around code for > nonexistent or dead variants. > > > > That said, I can't find anything describing that the VT-1 exists aside > > from these patches. Is there anything that describes this design and > > when it's expected to be available? > > What do you need? I can give some broad overview information on the > design, but it would likely just mirror what's already been mentioned in > these patches. > > > As far as schedules. I'm not sure what I can say. I'll check on that. > > > It was never my intention to bypass any process/procedures here. So if I > did, my apologies. The controversial part is XVentanaCondOps (as it is a vendor-defined extension), so I'll certainly hold off on that until both you and Palmer are in agreement on how to proceed there. Thanks, Philipp. > jeff >