From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by sourceware.org (Postfix) with ESMTPS id 645933858C50 for ; Mon, 17 Apr 2023 10:22:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 645933858C50 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ej1-x62e.google.com with SMTP id a640c23a62f3a-94f910ea993so25369266b.3 for ; Mon, 17 Apr 2023 03:22:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1681726952; x=1684318952; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=Jc3FxGHYWZULC/we0HiStddsGK7PpMSWWtJhL9a5HvA=; b=RhtCpVVRg6YV1krVCOZdEADTLGQgtUm5Fysn3LPa0umy2QnOzkzV0BvBQb1+rtZ22h snA3Ud9cXa7D/0AmLPeOfI/+6vKoS8bPcP8nZlelKh4cevbe1EtOXdtBRQjEzEtswEul ceWZFvlEVbFWX4H1Ra6W5Kpbpg56taLDGK+TlH7AQH55rv11mbV3aId0oAvOzib8Llxn Kli/OW+IwljXKlLQhCqSbIBNjKkzg7beCeutJa4AQVZnZyDIxr6xr8XAL+SK4eZP9CXE Z6LHUhgKeMIwTJ266GkE0gxAKiNbXQe7d+F2MCs+l6t4glDnkRQiF9IqzWVA/K3fD3hB Wg1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681726952; x=1684318952; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Jc3FxGHYWZULC/we0HiStddsGK7PpMSWWtJhL9a5HvA=; b=Fa1Yr3nP7JTrHcMCOl0bUJzD2iAf4Of+xIZ1Cr0vUVOgFZO5wABwQsXynToCfIewM0 7i74AOUT59i8oijUKs1HQATQRlpOn9yKTWvFZtpDTIvjc2o/uE/RXrpJe7HlzSczhu5S X+TOdawFx+4TyiLKDUGov9sFiRZ336hhexYc5vPqG77OGcyAIpUABKe7UlQmvc1DvmHy WH0hCx7P9A7eB3hq28dhk1mz7dGds4yGEjVjswNn6tggCUvUo8N5odhxWYD3nzwHdnOg VhSJ+K9xJRmb9liCq8GZP855LNDq0r3/zaqEDeYSPR/CLYkT7ybbPS3ad/sf0/ODwIgz XQpg== X-Gm-Message-State: AAQBX9fIObNYaTUZLq6NYjAuJby7RuK98lD5diXfEq3Dz8SMIYLKLAKB yzFaif1Tal5xAEclvssY545c19H1GuuuGgpLtbB4ApDCr/Roxe+x X-Google-Smtp-Source: AKy350a51DZkvVCBr72+I4xgInGftbCaUInv6a0J84md4AsR97UYvOH3IGozYGBo6HboZNkaf6PxVUw2eahE5aRwqKg= X-Received: by 2002:a05:6402:202f:b0:504:92c0:1732 with SMTP id ay15-20020a056402202f00b0050492c01732mr13553640edb.2.1681726951890; Mon, 17 Apr 2023 03:22:31 -0700 (PDT) MIME-Version: 1.0 References: <20230414180543.1497603-1-philipp.tomsich@vrull.eu> In-Reply-To: From: Philipp Tomsich Date: Mon, 17 Apr 2023 12:22:20 +0200 Message-ID: Subject: Re: [PATCH v2] aarch64: disable LDP via tuning structure for -mcpu=ampere1/1a To: Kyrylo Tkachov Cc: "gcc-patches@gcc.gnu.org" , Di Zhao Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: OK for backport? This will be all the way down to GCC10, as I just realized that we need to backport the entire ampere1/1a support to GCC10 (we stopped at GCC11 for some unexplainable reason)... Philipp. On Mon, 17 Apr 2023 at 12:20, Philipp Tomsich wrote: > > Applied to master, thanks! > Philipp. > > On Mon, 17 Apr 2023 at 11:56, Kyrylo Tkachov wrote: >> >> >> >> > -----Original Message----- >> > From: Philipp Tomsich >> > Sent: Friday, April 14, 2023 7:06 PM >> > To: gcc-patches@gcc.gnu.org >> > Cc: Kyrylo Tkachov ; Philipp Tomsich >> > ; Di Zhao >> > Subject: [PATCH v2] aarch64: disable LDP via tuning structure for - >> > mcpu=ampere1/1a >> > >> > AmpereOne (-mcpu=ampere1) breaks LDP instructions into two uops. >> > Given the chance that this causes instructions to slip into the next >> > decoding cycle and the additional overheads when handling >> > cacheline-crossing LDP instructions, we disable the generation of LDP >> > isntructions through the tuning structure from instruction combining >> > (such as in peephole2). >> > >> > Given the code-density benefits in builtins and prologue/epilogue >> > expansion, we allow LDPs there. >> > >> > This commit: >> > * adds a new tuning option AARCH64_EXTRA_TUNE_NO_LDP_COMBINE >> > * allows -moverride=tune=... to override this >> > >> > These changes are benchmark-driven, yielding the following changes >> > (with a net-overall improvement): >> > 503.bwaves_r. -0.88% >> > 507.cactuBSSN_r 0.35% >> > 508.namd_r 3.09% >> > 510.parest_r -2.99% >> > 511.povray_r 5.54% >> > 519.lbm_r 15.83% >> > 521.wrf_r 0.56% >> > 526.blender_r 2.47% >> > 527.cam4_r 0.70% >> > 538.imagick_r 0.00% >> > 544.nab_r -0.33% >> > 549.fotonik3d_r. -0.42% >> > 554.roms_r 0.00% >> > ------------------------- >> > = total 1.79% >> > >> > Signed-off-by: Philipp Tomsich >> > Co-Authored-By: Di Zhao >> >> Ok. >> Thanks, >> Kyrill >> >> > >> > gcc/ChangeLog: >> > >> > * config/aarch64/aarch64-tuning-flags.def >> > (AARCH64_EXTRA_TUNING_OPTION): >> > Add AARCH64_EXTRA_TUNE_NO_LDP_COMBINE. >> > * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp): >> > Check for the above tuning option when processing loads. >> > >> > gcc/testsuite/ChangeLog: >> > >> > * gcc.target/aarch64/ampere1-no_ldp_combine.c: New test. >> > >> > --- >> > >> > Changes in v2: >> > - apply both to -mcpu=ampere1 and -mcpu=ampere1a >> > - add TODO: tag, per discussions on the mailing list >> > - add testcase >> > >> > gcc/config/aarch64/aarch64-tuning-flags.def | 3 +++ >> > gcc/config/aarch64/aarch64.cc | 18 ++++++++++++++++-- >> > .../aarch64/ampere1-no_ldp_combine.c | 11 +++++++++++ >> > 3 files changed, 30 insertions(+), 2 deletions(-) >> > create mode 100644 gcc/testsuite/gcc.target/aarch64/ampere1- >> > no_ldp_combine.c >> > >> > diff --git a/gcc/config/aarch64/aarch64-tuning-flags.def >> > b/gcc/config/aarch64/aarch64-tuning-flags.def >> > index 712895a5263..52112ba7c48 100644 >> > --- a/gcc/config/aarch64/aarch64-tuning-flags.def >> > +++ b/gcc/config/aarch64/aarch64-tuning-flags.def >> > @@ -44,6 +44,9 @@ AARCH64_EXTRA_TUNING_OPTION >> > ("cheap_shift_extend", CHEAP_SHIFT_EXTEND) >> > /* Disallow load/store pair instructions on Q-registers. */ >> > AARCH64_EXTRA_TUNING_OPTION ("no_ldp_stp_qregs", >> > NO_LDP_STP_QREGS) >> > >> > +/* Disallow load-pair instructions to be formed in combine/peephole. */ >> > +AARCH64_EXTRA_TUNING_OPTION ("no_ldp_combine", >> > NO_LDP_COMBINE) >> > + >> > AARCH64_EXTRA_TUNING_OPTION ("rename_load_regs", >> > RENAME_LOAD_REGS) >> > >> > AARCH64_EXTRA_TUNING_OPTION ("cse_sve_vl_constants", >> > CSE_SVE_VL_CONSTANTS) >> > diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc >> > index f4ef22ce02f..0f04ab9fba0 100644 >> > --- a/gcc/config/aarch64/aarch64.cc >> > +++ b/gcc/config/aarch64/aarch64.cc >> > @@ -1933,7 +1933,7 @@ static const struct tune_params ampere1_tunings = >> > 2, /* min_div_recip_mul_df. */ >> > 0, /* max_case_values. */ >> > tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ >> > - (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ >> > + (AARCH64_EXTRA_TUNE_NO_LDP_COMBINE), /* tune_flags. */ >> > &ere1_prefetch_tune >> > }; >> > >> > @@ -1971,7 +1971,7 @@ static const struct tune_params ampere1a_tunings >> > = >> > 2, /* min_div_recip_mul_df. */ >> > 0, /* max_case_values. */ >> > tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ >> > - (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ >> > + (AARCH64_EXTRA_TUNE_NO_LDP_COMBINE), /* tune_flags. */ >> > &ere1_prefetch_tune >> > }; >> > >> > @@ -26053,6 +26053,20 @@ aarch64_operands_ok_for_ldpstp (rtx >> > *operands, bool load, >> > enum reg_class rclass_1, rclass_2; >> > rtx mem_1, mem_2, reg_1, reg_2; >> > >> > + /* Allow the tuning structure to disable LDP instruction formation >> > + from combining instructions (e.g., in peephole2). >> > + TODO: Implement fine-grained tuning control for LDP and STP: >> > + 1. control policies for load and store separately; >> > + 2. support the following policies: >> > + - default (use what is in the tuning structure) >> > + - always >> > + - never >> > + - aligned (only if the compiler can prove that the >> > + load will be aligned to 2 * element_size) */ >> > + if (load && (aarch64_tune_params.extra_tuning_flags >> > + & AARCH64_EXTRA_TUNE_NO_LDP_COMBINE)) >> > + return false; >> > + >> > if (load) >> > { >> > mem_1 = operands[1]; >> > diff --git a/gcc/testsuite/gcc.target/aarch64/ampere1-no_ldp_combine.c >> > b/gcc/testsuite/gcc.target/aarch64/ampere1-no_ldp_combine.c >> > new file mode 100644 >> > index 00000000000..bc871f4481d >> > --- /dev/null >> > +++ b/gcc/testsuite/gcc.target/aarch64/ampere1-no_ldp_combine.c >> > @@ -0,0 +1,11 @@ >> > +/* { dg-options "-O3 -mtune=ampere1" } */ >> > + >> > +long >> > +foo (long a[]) >> > +{ >> > + return a[0] + a[1]; >> > +} >> > + >> > +/* We should see two ldrs instead of one ldp. */ >> > +/* { dg-final { scan-assembler {\tldr\t} } } */ >> > +/* { dg-final { scan-assembler-not {\tldp\t} } } */ >> > -- >> > 2.34.1 >>