From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by sourceware.org (Postfix) with ESMTPS id 53C533857838 for ; Fri, 18 Nov 2022 00:10:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 53C533857838 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lj1-x236.google.com with SMTP id s24so4790288ljs.11 for ; Thu, 17 Nov 2022 16:10:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=AZlGHHvEa8dE0liiOScVjmWZBIhPIwRvtzMj8eJnn7s=; b=c3D1uCym5PVs2epu8eNM/JB3AdVnbHeJ7AKj9AEoQimtjaTJlktvqbPzb0Oh3RXNCI DYeZNhv+EiLjT57H4BBPhnZHZSLWovVqRLKmn1fSv+JHQcF+sC/lylBFwKCK0ANekP9/ HdDySp4LC32n24QSODLVcoENlNxVQT4Wa07lK7kruaUiGP9i6FtungeGoza3FzN+rP/U 9EwRzaYHFZAVUcEDcIQ4iIJyXpt8M1H2G/vYzVCU7K1kBuIuHppBxJV0G3MYHu4DN+ZB z9/hul/TjQaQ9bC9Ji19H8SZ4pNpfYyvSnHjShmdig7ajcjptNchIl49Hiir1IK57N3X htPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=AZlGHHvEa8dE0liiOScVjmWZBIhPIwRvtzMj8eJnn7s=; b=GOCxKj/N2Eg4Loer6bXVzAYDoguLDarnl0+j2Uj7bz/YA3/YdWbStRBxPVXqVmM/zb SaQ5Ns7R1HVGAx2R7S688Hhfl3VRcRPKMg8qXOD93I+oNFVtSPNNw+yPlb9LEQpvjN6/ HoPMpTQWVDE7KV4mKAYg+YQp0hvLu9pm+aUsn9XLsntHULmM+F72uEj3GxyqS4E2Kb5F ysZjpeSTZkmzSo539xPqN7hc41r8H7C15K5fQaxJ5AJ6myWuH/gev3pBfIYiOvEBQqzk 5pjsT+FQhe38/r485xXjZzlF8GDXmvDgQNZabruh9YNlCEt14pfSGi0GUrd1PcyVhFm1 6OvQ== X-Gm-Message-State: ANoB5pluorUBUuaXb7KHEV3xq0Cr01Bnz7bAnMBv6MgjKBL/Nm4ZXTYL 4Weea13VkSY+kceyWrzboiDTT2AAodXPUC5wLXDWtg== X-Google-Smtp-Source: AA0mqf4Y1niQmYqrilv1JzozsCgsfbEEu3du4iopS8ZgUDh2QaLhDHRgtwjQmTzd69JPl+0Ugg9cBeQ87qulOwJ8uK4= X-Received: by 2002:a2e:9c51:0:b0:277:e8e:8d90 with SMTP id t17-20020a2e9c51000000b002770e8e8d90mr1849185ljj.243.1668730237695; Thu, 17 Nov 2022 16:10:37 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Philipp Tomsich Date: Fri, 18 Nov 2022 01:10:26 +0100 Message-ID: Subject: Re: [PATCH 4/7] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps To: Palmer Dabbelt Cc: gcc-patches@gcc.gnu.org, Vineet Gupta , christoph.muellner@vrull.eu, Kito Cheng , jlaw@ventanamicro.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Fri, 18 Nov 2022 at 00:56, Palmer Dabbelt wrote: > > On Thu, 17 Nov 2022 15:41:26 PST (-0800), gcc-patches@gcc.gnu.org wrote: > > > > On 11/12/22 14:29, Philipp Tomsich wrote: > >> Users might use explicit arithmetic operations to create a mask and > >> then and it, in a sequence like > >> cond = (bits >> SHIFT) & 1; > >> mask = ~(cond - 1); > >> val &= mask; > >> which will present as a single-bit sign-extract. > >> > >> Dependening on what combination of XVentanaCondOps and Zbs are > >> available, this will map to the following sequences: > >> - bexti + vt.maskc, if both Zbs and XVentanaCondOps are present > >> - andi + vt.maskc, if only XVentanaCondOps is available and the > >> sign-extract is operating on bits 10:0 (bit > >> 11 can't be reached, as the immediate is > >> sign-extended) > >> - slli + srli + and, otherwise. > >> > >> gcc/ChangeLog: > >> > >> * config/riscv/xventanacondops.md: Recognize SIGN_EXTRACT > >> of a single-bit followed by AND for XVentanaCondOps. > >> > >> Signed-off-by: Philipp Tomsich > >> --- > >> > >> gcc/config/riscv/xventanacondops.md | 46 +++++++++++++++++++++++++++++ > >> 1 file changed, 46 insertions(+) > >> > >> diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md > >> index 7930ef1d837..3e9d5833a4b 100644 > >> --- a/gcc/config/riscv/xventanacondops.md > >> +++ b/gcc/config/riscv/xventanacondops.md > >> @@ -73,3 +73,49 @@ > >> "TARGET_XVENTANACONDOPS" > >> [(set (match_dup 5) (match_dup 1)) > >> (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 5) (const_int 0))) > >> + > >> +;; Users might use explicit arithmetic operations to create a mask and > >> +;; then and it, in a sequence like > > > > Nit. Seems like a word is missing. "make and then and it"?? > > > > > > Do we really care about TARGET_XVENTANACONDOPS && ! TARGET_ZBS? > > I guess that's really more of a question for the Ventana folks, but > assuming all the Ventana widgets have Zbs then it seems reasonable to > just couple them -- there's already enough options in RISC-V land to > test everything, might as well make sure what slips through the cracks > isn't being built. > > Probably best to have a comment saying why here, and then something to > enforce the dependency in -march (either as an implict extension > dependency, or just a warning/error) so users don't get tripped up on > configs that aren't expected to work. With an eye to (the proposed) ZiCondOps, I'd rather pull this in once XVentanaCondOps is applied. That said, we'll need to add a test-case for these. > > If there's a good reason to care about the !TARGET_ZBS case, then OK > > with the nit fixed. If we agree that the !TARGET_ZBS case isn't all > > that important, then obviously OK with that pattern removed too. > > > > I'm about out of oomph today. I may take a look at 7/7 tonight though. > > Given it hits target independent code we probably want to get resolution > > on that patch sooner rather than later. > > Thanks, there's no way we would have gotten this all sorted out so fast > without the help!