From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by sourceware.org (Postfix) with ESMTPS id 926D0384F480 for ; Thu, 17 Nov 2022 18:59:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 926D0384F480 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lf1-x12d.google.com with SMTP id c1so4334841lfi.7 for ; Thu, 17 Nov 2022 10:59:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=d5u5EiBh7NqSacoj3OIx8hEnWjkpQciz+wD190o0G20=; b=pqFk6+PNlXlZMA1qYr5Lepa+CYvRVQPXiyDpUvuBNVAWyOjGfG99BVUhL+hqD01uHC brhEok/s5v33rHoxyUlt0RzRYA+5GDrk0inrQKRcFDgZSCRT2vGBkrV/mv2rCzf5jde/ MNUIfM1QAHtqNSgYf0H4tCDunA/dy9BFDCEjzQwszrqJ/R/IRL0RNzcrYl/kGetgiRVW Bq5fb4OnblFyGP2nlVsBI6rKjXfv2l0u0eszuSfwWp22bz+gXt1fkEqyaMdAL5UYtHZV MgSyLLrm1zRW23iFyDJTPfEG3o8b0rbF57cXKCdtCvJYf8SY+lx+jCSuRSWVodhqzf4t 63Dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=d5u5EiBh7NqSacoj3OIx8hEnWjkpQciz+wD190o0G20=; b=ZBgC9GSXDhMjCV3fxhHmsxAY+bpUCRqtGNfeRHJAZrwUxI94kfMKaqR7mKYSBFEyLU VqqZxObly1W+KqcMehmt4agE392qFCrbmEoI855N0yt8iCrNTK8scFPXQSjN6Kdpfuqr dcEX2X0jO4xgBEjHyYrYnZ/y9rF5ugEVn9JfFFcWhwkuAJfsHoXqy7CLHBJOLEW+F3i9 otu4LITvmMDrjnO9/4NkPRys4mO94Y6OImHopOrJsRTi3dWbmxaT3KUh0e/bjROsubdV IS9p/zXBko7dp/9AvRYw2NXjWv4WBG3ZF/YqjkaACh3LuLiCEaCS7RQ0hYPvzR91sF8c 1Rog== X-Gm-Message-State: ANoB5pmcSF8lUgXAceitaqKcoIW5bunRa/h/Nkt6vBgjw24/jwtWwz+l eFK1KMau9c0x93iBro8p2LUUASoT+jiwAyuLUfJNGg== X-Google-Smtp-Source: AA0mqf4Ca7z5B98NgbMeYv8wDYoAl2pRQLFpsrnXKlFUujhpTkudPghTJHgvcVnBn2eVo3qWGZ7AEifmqMIgyVA2/G8= X-Received: by 2002:a19:5f03:0:b0:4a2:67ea:a06 with SMTP id t3-20020a195f03000000b004a267ea0a06mr1298788lfb.580.1668711584109; Thu, 17 Nov 2022 10:59:44 -0800 (PST) MIME-Version: 1.0 References: <20221113204858.4062163-1-philipp.tomsich@vrull.eu> In-Reply-To: From: Philipp Tomsich Date: Thu, 17 Nov 2022 19:59:32 +0100 Message-ID: Subject: Re: [PATCH] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs To: Andrew Waterman Cc: gcc-patches@gcc.gnu.org, Christoph Muellner , Kito Cheng , Vineet Gupta , Jeff Law , Palmer Dabbelt Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, 17 Nov 2022 at 19:56, Andrew Waterman wrote: > > On Thu, Nov 17, 2022 at 10:52 AM Philipp Tomsich > wrote: > > > > On Thu, 17 Nov 2022 at 19:33, Andrew Waterman wrote: > > > > > > Am I wrong to worry that this will increase dynamic instruction count > > > when used in a loop? The obvious code is more efficient when the > > > constant loads can be hoisted out of a loop. Or does the cost model > > > account for this somehow? > > > > With this change merged, GCC still hoists the constants out of the > > loop (just checked with a quick test case). > > So the cost model seems correct (whether intentionally or accidentally). > > Cool, thanks for checking. We have an updated cost-model for IF_THEN_ELSE brewing, but it didn't make the cut (and will need some more adjustments and a lot more testing). It seems to make a difference on some SPEC workloads. I don't have a timeline on finalizing that cost-model improvement yet. > > > > > Thanks, > > Philipp. > > > > > > > > > > > On Sun, Nov 13, 2022 at 12:50 PM Philipp Tomsich > > > wrote: > > > > > > > > Use Zbs when generating a sequence for "if ((a & twobits) == singlebit) ..." > > > > that can be expressed as bexti + bexti + andn. > > > > > > > > gcc/ChangeLog: > > > > > > > > * config/riscv/bitmanip.md (*branch_mask_twobits_equals_singlebit): > > > > Handle "if ((a & T) == C)" using Zbs, when T has 2 bits set and C has one > > > > of these tow bits set. > > > > * config/riscv/predicates.md (const_twobits_operand): New predicate. > > > > > > > > gcc/testsuite/ChangeLog: > > > > > > > > * gcc.target/riscv/zbs-if_then_else-01.c: New test. > > > > > > > > Signed-off-by: Philipp Tomsich > > > > --- > > > > > > > > gcc/config/riscv/bitmanip.md | 42 +++++++++++++++++++ > > > > gcc/config/riscv/predicates.md | 5 +++ > > > > .../gcc.target/riscv/zbs-if_then_else-01.c | 20 +++++++++ > > > > 3 files changed, 67 insertions(+) > > > > create mode 100644 gcc/testsuite/gcc.target/riscv/zbs-if_then_else-01.c > > > > > > > > diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md > > > > index 7a8f4e35880..2cea394671f 100644 > > > > --- a/gcc/config/riscv/bitmanip.md > > > > +++ b/gcc/config/riscv/bitmanip.md > > > > @@ -690,3 +690,45 @@ > > > > "TARGET_ZBS" > > > > [(set (match_dup 0) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2))) > > > > (set (match_dup 0) (xor:X (match_dup 0) (const_int 1)))]) > > > > + > > > > +;; IF_THEN_ELSE: test for 2 bits of opposite polarity > > > > +(define_insn_and_split "*branch_mask_twobits_equals_singlebit" > > > > + [(set (pc) > > > > + (if_then_else (match_operator 1 "equality_operator" > > > > + [(and:X (match_operand:X 2 "register_operand" "r") > > > > + (match_operand:X 3 "const_twobits_operand" "i")) > > > > + (match_operand:X 4 "single_bit_mask_operand" "i")]) > > > > + (label_ref (match_operand 0 "" "")) > > > > + (pc))) > > > > + (clobber (match_scratch:X 5 "=&r")) > > > > + (clobber (match_scratch:X 6 "=&r"))] > > > > + "TARGET_ZBS && TARGET_ZBB && !SMALL_OPERAND (INTVAL (operands[3]))" > > > > + "#" > > > > + "&& reload_completed" > > > > + [(set (match_dup 5) (zero_extract:X (match_dup 2) > > > > + (const_int 1) > > > > + (match_dup 8))) > > > > + (set (match_dup 6) (zero_extract:X (match_dup 2) > > > > + (const_int 1) > > > > + (match_dup 9))) > > > > + (set (match_dup 6) (and:X (not:X (match_dup 6)) (match_dup 5))) > > > > + (set (pc) (if_then_else (match_op_dup 1 [(match_dup 6) (const_int 0)]) > > > > + (label_ref (match_dup 0)) > > > > + (pc)))] > > > > +{ > > > > + unsigned HOST_WIDE_INT twobits_mask = UINTVAL (operands[3]); > > > > + unsigned HOST_WIDE_INT singlebit_mask = UINTVAL (operands[4]); > > > > + > > > > + /* Make sure that the reference value has one of the bits of the mask set */ > > > > + if ((twobits_mask & singlebit_mask) == 0) > > > > + FAIL; > > > > + > > > > + int setbit = ctz_hwi (singlebit_mask); > > > > + int clearbit = ctz_hwi (twobits_mask & ~singlebit_mask); > > > > + > > > > + operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == NE ? EQ : NE, > > > > + mode, operands[6], GEN_INT(0)); > > > > + > > > > + operands[8] = GEN_INT (setbit); > > > > + operands[9] = GEN_INT (clearbit); > > > > +}) > > > > diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md > > > > index 490bff688a7..6e34829a59b 100644 > > > > --- a/gcc/config/riscv/predicates.md > > > > +++ b/gcc/config/riscv/predicates.md > > > > @@ -321,6 +321,11 @@ > > > > (and (match_code "const_int") > > > > (match_test "popcount_hwi (~UINTVAL (op)) == 2"))) > > > > > > > > +;; A CONST_INT operand that has exactly two bits set. > > > > +(define_predicate "const_twobits_operand" > > > > + (and (match_code "const_int") > > > > + (match_test "popcount_hwi (UINTVAL (op)) == 2"))) > > > > + > > > > ;; A CONST_INT operand that fits into the unsigned half of a > > > > ;; signed-immediate after the top bit has been cleared. > > > > (define_predicate "uimm_extra_bit_operand" > > > > diff --git a/gcc/testsuite/gcc.target/riscv/zbs-if_then_else-01.c b/gcc/testsuite/gcc.target/riscv/zbs-if_then_else-01.c > > > > new file mode 100644 > > > > index 00000000000..d249a841ff9 > > > > --- /dev/null > > > > +++ b/gcc/testsuite/gcc.target/riscv/zbs-if_then_else-01.c > > > > @@ -0,0 +1,20 @@ > > > > +/* { dg-do compile } */ > > > > +/* { dg-options "-march=rv64gc_zbb_zbs -mabi=lp64" } */ > > > > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */ > > > > + > > > > +void g(); > > > > + > > > > +void f1 (long a) > > > > +{ > > > > + if ((a & ((1ul << 33) | (1 << 4))) == (1ul << 33)) > > > > + g(); > > > > +} > > > > + > > > > +void f2 (long a) > > > > +{ > > > > + if ((a & 0x12) == 0x10) > > > > + g(); > > > > +} > > > > + > > > > +/* { dg-final { scan-assembler-times "bexti\t" 2 } } */ > > > > +/* { dg-final { scan-assembler-times "andn\t" 1 } } */ > > > > -- > > > > 2.34.1 > > > >