Re: [PATCH] RISC-V: Add Zawrs ISA extension support

[Philipp Tomsich <philipp.tomsich@vrull.eu>]

On Wed, 2 Nov 2022 at 15:21, Christoph Müllner
<christoph.muellner@vrull.eu> wrote:
>
>
>
> On Thu, Oct 27, 2022 at 10:51 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>>
>> On Thu, 27 Oct 2022 11:23:17 PDT (-0700), christoph.muellner@vrull.eu wrote:
>> > On Thu, Oct 27, 2022 at 8:11 PM Christoph Muellner <
>> > christoph.muellner@vrull.eu> wrote:
>> >
>> >> From: Christoph Muellner <cmuellner@gcc.gnu.org>
>> >>
>> >> This patch adds support for the Zawrs ISA extension.
>> >> The patch depends on the corresponding Binutils patch
>> >> to be usable (see [1])
>> >>
>> >> The specification can be found here:
>> >> https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc
>> >>
>> >> Note, that the Zawrs extension is not frozen or ratified yet.
>> >> Therefore this patch is an RFC and not intended to get merged.
>> >>
>> >
>> > Sorry, forgot to update this part:
>> > The Zawrs extension is frozen but not ratified.
>> > Let me know if I should send a v2 for this change of the commit msg.
>>
>> IMO it's fine to just fix it up at commit time.  This LGTM, we just need
>> the NEWS entry too.  I also don't see any build/test results.
>
>
> I ran the GCC regression test suite with rv32 and rv64 toolchains
> using the riscv-gnu-toolchain repo and did not see any regressions.
>
> Where can I create the news entry?

News are generated from
  git://gcc.gnu.org/git/gcc-wwwdocs.git

You'll want to add to
  htdocs/gcc-13/changes.html

Thanks,
Philipp.

>>
>>
>> Thanks!
>>
>> > Binuitls support has been merged recently:
>> >
>> > https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=eb668e50036e979fb0a74821df4eee0307b44e66
>> >
>> >
>> >>
>> >> [1] https://sourceware.org/pipermail/binutils/2022-April/120559.html
>> >>
>> >> gcc/ChangeLog:
>> >>
>> >>         * common/config/riscv/riscv-common.cc: Add zawrs extension.
>> >>         * config/riscv/riscv-opts.h (MASK_ZAWRS): New.
>> >>         (TARGET_ZAWRS): New.
>> >>         * config/riscv/riscv.opt: New.
>> >>
>> >> gcc/testsuite/ChangeLog:
>> >>
>> >>         * gcc.target/riscv/zawrs.c: New test.
>> >>
>> >> Signed-off-by: Christoph Muellner <cmuellner@gcc.gnu.org>
>> >> ---
>> >>  gcc/common/config/riscv/riscv-common.cc |  4 ++++
>> >>  gcc/config/riscv/riscv-opts.h           |  3 +++
>> >>  gcc/config/riscv/riscv.opt              |  3 +++
>> >>  gcc/testsuite/gcc.target/riscv/zawrs.c  | 13 +++++++++++++
>> >>  4 files changed, 23 insertions(+)
>> >>  create mode 100644 gcc/testsuite/gcc.target/riscv/zawrs.c
>> >>
>> >> diff --git a/gcc/common/config/riscv/riscv-common.cc
>> >> b/gcc/common/config/riscv/riscv-common.cc
>> >> index d6404a01205..4b7f777c103 100644
>> >> --- a/gcc/common/config/riscv/riscv-common.cc
>> >> +++ b/gcc/common/config/riscv/riscv-common.cc
>> >> @@ -163,6 +163,8 @@ static const struct riscv_ext_version
>> >> riscv_ext_version_table[] =
>> >>    {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
>> >>    {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
>> >>
>> >> +  {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
>> >> +
>> >>    {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
>> >>    {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
>> >>    {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
>> >> @@ -1180,6 +1182,8 @@ static const riscv_ext_flag_table_t
>> >> riscv_ext_flag_table[] =
>> >>    {"zicsr",    &gcc_options::x_riscv_zi_subext, MASK_ZICSR},
>> >>    {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
>> >>
>> >> +  {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS},
>> >> +
>> >>    {"zba",    &gcc_options::x_riscv_zb_subext, MASK_ZBA},
>> >>    {"zbb",    &gcc_options::x_riscv_zb_subext, MASK_ZBB},
>> >>    {"zbc",    &gcc_options::x_riscv_zb_subext, MASK_ZBC},
>> >> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
>> >> index 1dfe8c89209..25fd85b09b1 100644
>> >> --- a/gcc/config/riscv/riscv-opts.h
>> >> +++ b/gcc/config/riscv/riscv-opts.h
>> >> @@ -73,6 +73,9 @@ enum stack_protector_guard {
>> >>  #define TARGET_ZICSR    ((riscv_zi_subext & MASK_ZICSR) != 0)
>> >>  #define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
>> >>
>> >> +#define MASK_ZAWRS   (1 << 0)
>> >> +#define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0)
>> >> +
>> >>  #define MASK_ZBA      (1 << 0)
>> >>  #define MASK_ZBB      (1 << 1)
>> >>  #define MASK_ZBC      (1 << 2)
>> >> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
>> >> index 426ea95cd14..7c3ca48d1cc 100644
>> >> --- a/gcc/config/riscv/riscv.opt
>> >> +++ b/gcc/config/riscv/riscv.opt
>> >> @@ -203,6 +203,9 @@ long riscv_stack_protector_guard_offset = 0
>> >>  TargetVariable
>> >>  int riscv_zi_subext
>> >>
>> >> +TargetVariable
>> >> +int riscv_za_subext
>> >> +
>> >>  TargetVariable
>> >>  int riscv_zb_subext
>> >>
>> >> diff --git a/gcc/testsuite/gcc.target/riscv/zawrs.c
>> >> b/gcc/testsuite/gcc.target/riscv/zawrs.c
>> >> new file mode 100644
>> >> index 00000000000..0b7e2662343
>> >> --- /dev/null
>> >> +++ b/gcc/testsuite/gcc.target/riscv/zawrs.c
>> >> @@ -0,0 +1,13 @@
>> >> +/* { dg-do compile } */
>> >> +/* { dg-options "-march=rv64gc_zawrs" { target { rv64 } } } */
>> >> +/* { dg-options "-march=rv32gc_zawrs" { target { rv32 } } } */
>> >> +
>> >> +#ifndef __riscv_zawrs
>> >> +#error Feature macro not defined
>> >> +#endif
>> >> +
>> >> +int
>> >> +foo (int a)
>> >> +{
>> >> +  return a;
>> >> +}
>> >> --
>> >> 2.37.3
>> >>
>> >>