From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by sourceware.org (Postfix) with ESMTPS id BE1123858D20 for ; Fri, 14 Apr 2023 09:32:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BE1123858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ed1-x535.google.com with SMTP id 4fb4d7f45d1cf-504fce3d7fbso1896812a12.2 for ; Fri, 14 Apr 2023 02:32:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1681464725; x=1684056725; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=jcqDn237gPknOm1V2rFgnf8apUhSKdjYgTJUF1UIOPw=; b=enHjA8isG69KIvslUAcp4f0czAMAPNNjOB8Ur6XAo3kiIPze3+veWv1bIDBlpJQ0mf MMKqzzO6wuSW+7QoixYoXUasZ1EwF49tUAosrcU6btXfqria+VZoNAEEmuuVWgs6nP82 0wBejDLPtL5HksbFM2BuDD3w4kUlLXAtHk/bqqj/Fm2+sxBRJ/MZpoPYxEGgJwiI8s8D 6/mE2GuZOCrRFljdICYBo5qU+62JU1COtpcHB2rIyvyuAqXR1ghdJRvQpBSuibx0O/HW mzT+xopS3uGikY6FjgmJlc9bDg/hXlYFDP3op3d4m79T99WjKSuCuikPRdKWfuzNCPdR Z8lA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681464725; x=1684056725; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=jcqDn237gPknOm1V2rFgnf8apUhSKdjYgTJUF1UIOPw=; b=KscZMJR0wgXMvOvECD1wh4DP6i5ItCOvFTEt6x/ADaOlm0Y8Lg0LUiIiHMKhkT9Oiy xFaaS7Jn5nAQq+JphUCSxs2iRI6XJosROwQBqT/TNPwvzubNoOCharxcb4Hmt7AKGKWm 35Vt/Mhtuu+R735Pm+F4wBfxhnzQ1do6Xm2sLgowTc9sqDA0oKlegpkEaBghbc7c0YCG 4VHCJQMlzIMwqek15aRZ0QqHsx0IqG/cu9cTXVexcpeyoWsOf6t1pcajhLsP98t5oQIC 0/XKCYYFKzNnYY+TO0YOu/iNoeNXOAedcb6Fk3FIbZJtxgrkPCaI7bS8lLZxX/HS/Xrn APOA== X-Gm-Message-State: AAQBX9fBzTCa5S4VS8lywbILWzJfBv8R4iD74VFrE6bWSxKNYb/bQpxb aVJRRpTFQYNcU/tlzLm7inStlPGA7ZJqxX+kZ4i9WQ== X-Google-Smtp-Source: AKy350YwP4evmNgPqzFbVGmV9Q+AsLiotpCymEQUPGgPqhGKyEmqAo/gyBinAA04sb9C3KsX1CPHkFlu8dXiUVYcQTM= X-Received: by 2002:aa7:c148:0:b0:501:d43e:d1e3 with SMTP id r8-20020aa7c148000000b00501d43ed1e3mr6354105edp.8.1681464725293; Fri, 14 Apr 2023 02:32:05 -0700 (PDT) MIME-Version: 1.0 References: <20230413232157.1487389-1-philipp.tomsich@vrull.eu> In-Reply-To: From: Philipp Tomsich Date: Fri, 14 Apr 2023 11:31:54 +0200 Message-ID: Subject: Re: [PATCH] aarch64: disable LDP via tuning structure for -mcpu=ampere1 To: Kyrylo Tkachov Cc: "gcc-patches@gcc.gnu.org" , Di Zhao Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_NUMSUBJECT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Kyrylo, On Fri, 14 Apr 2023 at 11:21, Kyrylo Tkachov wrote: > > Hi Philipp, > > > -----Original Message----- > > From: Philipp Tomsich > > Sent: Friday, April 14, 2023 12:22 AM > > To: gcc-patches@gcc.gnu.org > > Cc: Kyrylo Tkachov ; Philipp Tomsich > > ; Di Zhao > > Subject: [PATCH] aarch64: disable LDP via tuning structure for - > > mcpu=ampere1 > > > > AmpereOne (-mcpu=ampere1) breaks LDP instructions into two uops. > > Given the chance that this causes instructions to slip into the next > > decoding cycle and the additional overheads when handling > > cacheline-crossing LDP instructions, we disable the generation of LDP > > isntructions through the tuning structure from instruction combining > > (such as in peephole2). > > > > Given the code-density benefits in builtins and prologue/epilogue > > expansion, we allow LDPs there. > > LDPs are indeed quite an important part of the ISA for code density and there are, in principle, second-order benefits from using them, like keeping the instruction cache footprint low (which can be important for large workloads). > Did you gather some benchmarks showing a benefit of disabling them in this manner? This has been benchmark-driven, but I need to follow up separately (as I the final numbers are with the folks that have access to the benchmark machines).. > > > This commit: > > * adds a new tuning option AARCH64_EXTRA_TUNE_NO_LDP_COMBINE > > * allows -moverride=tune=... to override this > > > > Signed-off-by: Philipp Tomsich > > Co-Authored-By: Di Zhao > > > > gcc/ChangeLog: > > > > * config/aarch64/aarch64-tuning-flags.def > > (AARCH64_EXTRA_TUNING_OPTION): > > Add AARCH64_EXTRA_TUNE_NO_LDP_COMBINE. > > * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp): > > Check for the above tuning option when processing loads. > > > > --- > > > > gcc/config/aarch64/aarch64-tuning-flags.def | 3 +++ > > gcc/config/aarch64/aarch64.cc | 8 +++++++- > > 2 files changed, 10 insertions(+), 1 deletion(-) > > > > diff --git a/gcc/config/aarch64/aarch64-tuning-flags.def > > b/gcc/config/aarch64/aarch64-tuning-flags.def > > index 712895a5263..52112ba7c48 100644 > > --- a/gcc/config/aarch64/aarch64-tuning-flags.def > > +++ b/gcc/config/aarch64/aarch64-tuning-flags.def > > @@ -44,6 +44,9 @@ AARCH64_EXTRA_TUNING_OPTION > > ("cheap_shift_extend", CHEAP_SHIFT_EXTEND) > > /* Disallow load/store pair instructions on Q-registers. */ > > AARCH64_EXTRA_TUNING_OPTION ("no_ldp_stp_qregs", > > NO_LDP_STP_QREGS) > > > > +/* Disallow load-pair instructions to be formed in combine/peephole. */ > > +AARCH64_EXTRA_TUNING_OPTION ("no_ldp_combine", > > NO_LDP_COMBINE) > > + > > AARCH64_EXTRA_TUNING_OPTION ("rename_load_regs", > > RENAME_LOAD_REGS) > > > > AARCH64_EXTRA_TUNING_OPTION ("cse_sve_vl_constants", > > CSE_SVE_VL_CONSTANTS) > > diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc > > index f4ef22ce02f..8dc1a9ceb17 100644 > > --- a/gcc/config/aarch64/aarch64.cc > > +++ b/gcc/config/aarch64/aarch64.cc > > @@ -1971,7 +1971,7 @@ static const struct tune_params ampere1a_tunings > > = > > 2, /* min_div_recip_mul_df. */ > > 0, /* max_case_values. */ > > tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ > > - (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ > > + (AARCH64_EXTRA_TUNE_NO_LDP_COMBINE), /* tune_flags. */ > > &ere1_prefetch_tune > > }; > > > > @@ -26053,6 +26053,12 @@ aarch64_operands_ok_for_ldpstp (rtx > > *operands, bool load, > > enum reg_class rclass_1, rclass_2; > > rtx mem_1, mem_2, reg_1, reg_2; > > > > + /* Allow the tuning structure to disable LDP instruction formation > > + from combining instructions (e.g., in peephole2). */ > > + if (load && (aarch64_tune_params.extra_tuning_flags > > + & AARCH64_EXTRA_TUNE_NO_LDP_COMBINE)) > > + return false; > > If we do decide to do this, I think this is not a complete approach. See the similar tuning flag AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS. > There's various other places in the backend that would need to be adjusted to avoid bringing loads together for the peephole2s to merge (the sched_fusion stuff). > Plus there's the cpymem expansions that would generate load pairs too... I have add-on patches for these, but given that I don't have direct access to the benchmarking machine and the benchmarks have been run with this functionality only, I didn't submit them for the time being. Do you see a path to get this in during the current cycle and defer the add-on patches (happy to resubmit as a series) only? > We'd want some testcases added to check that LDPs are blocked too... > > Thanks, > Kyrill > > > + > > if (load) > > { > > mem_1 = operands[1]; > > -- > > 2.34.1 >