From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by sourceware.org (Postfix) with ESMTPS id 1418E385840F for ; Sat, 12 Nov 2022 22:02:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 1418E385840F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lf1-x12a.google.com with SMTP id bp15so13401760lfb.13 for ; Sat, 12 Nov 2022 14:02:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=gDDvSw5RJl0rYA2WxRwoPBhwwA1BiPl+z2GHhTdp7TM=; b=Y2eFzNc62jByxnGBvhfxTghjpCzyHfUx+fwwyanHiW6UhqlCXe3OJ36WL6Bkfv2Ngq rp32DNuHidWXC9kRihugwbOk4ALlKyWYLvy4Npk0efTGD9rJ29q4Omn8S53AACFmaDYX hGcIkgOnkJ03c+if87aRUWZJNNCtdG8pWA/Z+34HU8E35ZW+s0wwhJSSIsj43t4dQWeN lsqyO5Tb+ZWYDlBCshaNmfMemJfk+LSKBZaagR195QFJDXOFaTPrzOEImeKkWKswAwR8 WzaLhg9iAOnIOrlJCgXCJf2V3I0aZ18nlWOqkOfY6q329pmf8bZVwf/bSlld6eJ+bqdJ hM+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gDDvSw5RJl0rYA2WxRwoPBhwwA1BiPl+z2GHhTdp7TM=; b=PB9L+gm9IeG9trFU25kssqManZjxKZRPemkhyPyqTDxwPSCTD0nU2quFyvBFKwKakp OoHHn0+2alTA+KuefDrsPLumSK6YiZttEnEElQFn3QvpjwcCNstQGpbRS+nhgmCo950k LLzkRY8gD+n9Me4FiN1kSYdCNmEHXzcMi30TQSu5T43mrrY5hVnX1A3fhedOKXItztvs XjpQ+AiEVtD0Vqb/7sUbk6d3mlagu/RfTvbQOOUpRXPMW8GFZTu7FsuqK6BYM6qCczBu NBE6sB1vB1A+X2wdFcVMHjM1LZAbmh8JlODtfuizDCaiQUa9jItAvcHFVttcRjM405um Inpw== X-Gm-Message-State: ANoB5pmE2Zxp6l3cZG5inODSvbQwgXe8jEHsA2Tb84XZlGztveWdibVv A/Bu/DCJYgrnWV4yxT/tDEJ6iNwnaCB/Ymqw8PTIwg== X-Google-Smtp-Source: AA0mqf4Dlp25NtfAqLifuuKUM2pIrmQbphBz8aeiUTt6WTTGfvj/mNU7GD9XcYqDWe/BueJEoQnbQP4v4FPXT1Ssay8= X-Received: by 2002:a05:6512:3497:b0:4b1:753b:e671 with SMTP id v23-20020a056512349700b004b1753be671mr2311072lfr.441.1668290529335; Sat, 12 Nov 2022 14:02:09 -0800 (PST) MIME-Version: 1.0 References: <20221112212943.3068249-1-philipp.tomsich@vrull.eu> <20221112212943.3068249-8-philipp.tomsich@vrull.eu> In-Reply-To: From: Philipp Tomsich Date: Sat, 12 Nov 2022 23:01:58 +0100 Message-ID: Subject: Re: [PATCH 7/7] ifcvt: add if-conversion to conditional-zero instructions To: Andrew Pinski Cc: gcc-patches@gcc.gnu.org, Vineet Gupta , Palmer Dabbelt , Christoph Muellner , Kito Cheng , Jeff Law Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-7.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_SHORT,LIKELY_SPAM_BODY,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Sat, 12 Nov 2022 at 22:47, Andrew Pinski wrote: > > On Sat, Nov 12, 2022 at 1:34 PM Philipp Tomsich > wrote: > > > > Some architectures, as it the case on RISC-V with the proposed > > ZiCondOps and the vendor-defined XVentanaCondOps, define a > > conditional-zero instruction that is equivalent to: > > - the positive form: rd =3D (rc !=3D 0) ? rs : 0 > > - the negated form: rd =3D (rc =3D=3D 0) ? rs : 0 > > > > While noce_try_store_flag_mask will somewhat work for this case, it > > will generate a number of atomic RTX that will misdirect the cost > > calculation and may be too long (i.e., 4 RTX and more) to successfully > > merge at combine-time. > > > > Instead, we add two new transforms that attempt to build up what we > > define as the canonical form of a conditional-zero expression: > > > > (set (match_operand 0 "register_operand" "=3Dr") > > (and (neg (eq_or_ne (match_operand 1 "register_operand" "r") > > (const_int 0))) > > (match_operand 2 "register_operand" "r"))) > > > Why is it not: > (set x (if_then_else (eq_or_ne y (0)) z (0)) > (set x (if_then_else (ne y (0)) (0) z) > > That seems simpler to expression and is the normal a=3D=3D0?0:z expressio= n. Having an if_then_else come out of if-conversion would be a bit unusual, as transformation to branchless is the intent of the entire exercise. Existing if-conversion via noce_try_store_flag_mask and noce_try_store_flag already catch these sequences=E2=80=94if that happens, the above representa= tion will be present during combine: i.e., we need to implement this match anywa= y (and it also matches the typical idiom, if a programmer tries to express th= e idiom in a branchless way). Consequently, we decided to use the same pattern as the canonical representation in case that if-conversion had occurred prior. > Also all canonical forms of RTL should be documented too. > They are documented here: > https://gcc.gnu.org/onlinedocs/gcc-12.2.0/gccint/Insn-Canonicalizations.h= tml > https://gcc.gnu.org/onlinedocs/gccint/machine-descriptions/canonicalizati= on-of-instructions.html > gcc/doc/gccint/machine-descriptions/canonicalization-of-instructions.rst > > > Thanks, > Andrew Pinski > > > > > Architectures that provide a conditional-zero are thus expected to > > define an instruction matching this pattern in their backend. > > > > Based on this, we support the following cases: > > - noce_try_condzero: > > a ? a : b > > a ? b : 0 (and then/else swapped) > > !a ? b : 0 (and then/else swapped) > > - noce_try_condzero_arith: > > conditional-plus, conditional-minus, conditional-and, > > conditional-or, conditional-xor, conditional-shift, > > conditional-and > > > > Given that this is hooked into the CE passes, it is less powerful than > > a tree-pass (e.g., it can not transform cases where an extension, such > > as for uint16_t operations is in either the then or else-branch > > together with the arithmetic) but already covers a good array of cases > > and triggers across SPEC CPU 2017. > > Adding transofmrations in a tree pass will be considered as a future > > improvement. > > > > gcc/ChangeLog: > > > > * ifcvt.cc (noce_emit_insn): Add prototype. > > (noce_emit_condzero): Helper for noce_try_condzero and > > noce_try_condzero_arith transforms. > > (noce_try_condzero): New transform. > > (noce_try_condzero_arith): New transform for conditional > > arithmetic that can be built up by exploiting that the > > conditional-zero instruction will inject 0, which acts > > as the neutral element for operations. > > (noce_process_if_block): Call noce_try_condzero and > > noce_try_condzero_arith. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/riscv/xventanacondops-and-01.c: New test. > > * gcc.target/riscv/xventanacondops-and-02.c: New test. > > * gcc.target/riscv/xventanacondops-eq-01.c: New test. > > * gcc.target/riscv/xventanacondops-eq-02.c: New test. > > * gcc.target/riscv/xventanacondops-lt-01.c: New test. > > * gcc.target/riscv/xventanacondops-ne-01.c: New test. > > * gcc.target/riscv/xventanacondops-xor-01.c: New test. > > > > Signed-off-by: Philipp Tomsich > > --- > > > > gcc/ifcvt.cc | 214 ++++++++++++++++++ > > .../gcc.target/riscv/xventanacondops-and-01.c | 16 ++ > > .../gcc.target/riscv/xventanacondops-and-02.c | 15 ++ > > .../gcc.target/riscv/xventanacondops-eq-01.c | 11 + > > .../gcc.target/riscv/xventanacondops-eq-02.c | 14 ++ > > .../gcc.target/riscv/xventanacondops-lt-01.c | 16 ++ > > .../gcc.target/riscv/xventanacondops-ne-01.c | 11 + > > .../gcc.target/riscv/xventanacondops-xor-01.c | 14 ++ > > 8 files changed, 311 insertions(+) > > create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-and-= 01.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-and-= 02.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-eq-0= 1.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-eq-0= 2.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-lt-0= 1.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-0= 1.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-= 01.c > > > > diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc > > index eb8efb89a89..41c58876d05 100644 > > --- a/gcc/ifcvt.cc > > +++ b/gcc/ifcvt.cc > > @@ -97,6 +97,7 @@ static int find_if_case_2 (basic_block, edge, edge); > > static int dead_or_predicable (basic_block, basic_block, basic_block, > > edge, int); > > static void noce_emit_move_insn (rtx, rtx); > > +static rtx_insn *noce_emit_insn (rtx); > > static rtx_insn *block_has_only_trap (basic_block); > > static void need_cmov_or_rewire (basic_block, hash_set *, > > hash_map *); > > @@ -787,6 +788,9 @@ static rtx noce_get_alt_condition (struct noce_if_i= nfo *, rtx, rtx_insn **); > > static int noce_try_minmax (struct noce_if_info *); > > static int noce_try_abs (struct noce_if_info *); > > static int noce_try_sign_mask (struct noce_if_info *); > > +static rtx noce_emit_condzero (struct noce_if_info *, rtx, bool =3D fa= lse); > > +static int noce_try_condzero (struct noce_if_info *); > > +static int noce_try_condzero_arith (struct noce_if_info *); > > > > /* Return the comparison code for reversed condition for IF_INFO, > > or UNKNOWN if reversing the condition is not possible. */ > > @@ -1664,6 +1668,212 @@ noce_try_addcc (struct noce_if_info *if_info) > > return FALSE; > > } > > > > +/* Helper to noce_try_condzero: cond ? a : 0. */ > > +static rtx > > +noce_emit_condzero (struct noce_if_info *if_info, rtx a, bool reverse) > > +{ > > + /* The canonical form for a conditional-zero-or-value is: > > + (set (match_operand 0 "register_operand" "=3Dr") > > + (and (neg (eq_or_ne (match_operand 1 "register_operand" "r"= ) > > + (const_int 0))) > > + (match_operand 2 "register_operand" "r"))) > > + */ > > + > > + machine_mode opmode =3D GET_MODE (if_info->x); > > + enum rtx_code code =3D GET_CODE (if_info->cond); > > + rtx cond; > > + rtx op_a =3D XEXP (if_info->cond, 0); > > + rtx op_b =3D XEXP (if_info->cond, 1); > > + > > + /* If it is not a EQ/NE comparison against const0_rtx, canonicalize > > + by first synthesizing a truth-value and then building a NE > > + condition around it. */ > > + if ((code !=3D EQ && code !=3D NE) || XEXP (if_info->cond, 1) !=3D c= onst0_rtx) > > + { > > + rtx tmp =3D gen_reg_rtx (opmode); > > + > > + start_sequence (); > > + cond =3D gen_rtx_fmt_ee (code, opmode, op_a, op_b); > > + if (!noce_emit_insn (gen_rtx_SET (tmp, cond))) > > + { > > + end_sequence (); > > + > > + /* If we can't emit this pattern, try to reverse it and > > + invert the polarity of the second test. */ > > + start_sequence (); > > + cond =3D gen_rtx_fmt_ee (reverse_condition (code), opmode, op= _a, op_b); > > + if (!noce_emit_insn (gen_rtx_SET (tmp, cond))) { > > + end_sequence (); > > + return NULL_RTX; > > + } > > + > > + /* We have recovered by reversing the first comparison, > > + so we need change the second one around as well... */ > > + reverse =3D !reverse; > > + } > > + rtx_insn *seq =3D get_insns (); > > + end_sequence (); > > + emit_insn (seq); > > + > > + /* Set up the second comparison that will be embedded in the > > + canonical conditional-zero-or-value RTX. */ > > + code =3D NE; > > + op_a =3D tmp; > > + op_b =3D const0_rtx; > > + } > > + > > + cond =3D gen_rtx_fmt_ee (reverse ? reverse_condition (code) : code, > > + opmode, op_a, op_b); > > + > > + /* Build (and (neg (eq_or_ne ... const0_rtx)) (reg )) */ > > + rtx target =3D gen_reg_rtx (opmode); > > + rtx czero =3D gen_rtx_AND (opmode, gen_rtx_NEG (opmode, cond), a); > > + noce_emit_move_insn (target, czero); > > + > > + return target; > > +} > > + > > +/* Use a conditional-zero instruction for "if (test) x =3D 0;", if ava= ilable. */ > > +static int > > +noce_try_condzero (struct noce_if_info *if_info) > > +{ > > + rtx target; > > + rtx_insn *seq; > > + int reversep =3D 0; > > + rtx orig_b =3D NULL_RTX; > > + rtx cond =3D if_info->cond; > > + enum rtx_code code =3D GET_CODE (cond); > > + rtx cond_arg0 =3D XEXP (cond, 0); > > + rtx cond_arg1 =3D XEXP (cond, 1); > > + > > + if (!noce_simple_bbs (if_info)) > > + return FALSE; > > + > > + /* We may encounter the form "(a !=3D 0) ? a : b", which can be > > + simplified to "a | ((a !=3D 0) ? 0 : b)". */ > > + if (code =3D=3D NE && cond_arg1 =3D=3D const0_rtx && > > + REG_P (if_info->b) && rtx_equal_p (if_info->b, cond_arg0)) > > + { > > + orig_b =3D if_info->b; > > + if_info->b =3D const0_rtx; > > + } > > + > > + /* We may encounter the form "(a !=3D 0) ? b : a", which can be > > + simplied to "(a !=3D 0) ? b : 0". */ > > + if (code =3D=3D EQ && cond_arg1 =3D=3D const0_rtx && > > + REG_P (if_info->b) && rtx_equal_p (if_info->b, cond_arg0)) > > + { > > + /* We know that cond_arg0 is const_0, if the THEN branch is > > + taken... so if it is the same as if_info->b (yes, things are > > + backwards!), we can rewrite it with that knowledge. */ > > + if_info->b =3D const0_rtx; > > + } > > + > > + start_sequence (); > > + > > + if ((if_info->a =3D=3D const0_rtx > > + && (REG_P (if_info->b) || rtx_equal_p (if_info->b, if_info->x))= ) > > + || ((reversep =3D (noce_reversed_cond_code (if_info) !=3D UNKNOW= N)) > > + && if_info->b =3D=3D const0_rtx > > + && (REG_P (if_info->a) || rtx_equal_p (if_info->a, if_info->x= )))) > > + { > > + target =3D noce_emit_condzero(if_info, > > + reversep ? if_info->a : if_info->b, > > + reversep); > > + > > + if (orig_b && target) > > + target =3D expand_simple_binop (GET_MODE (if_info->x), IOR, ori= g_b, > > + target, if_info->x, 0, OPTAB_WIDE= N); > > + > > + if (target) > > + { > > + if (target !=3D if_info->x) > > + noce_emit_move_insn (if_info->x, target); > > + > > + seq =3D end_ifcvt_sequence (if_info); > > + if (!seq || !targetm.noce_conversion_profitable_p (seq, if_in= fo)) > > + return FALSE; > > + > > + emit_insn_before_setloc (seq, if_info->jump, > > + INSN_LOCATION (if_info->insn_a)); > > + if_info->transform_name =3D "noce_try_condzero"; > > + > > + return TRUE; > > + } > > + } > > + > > + end_sequence (); > > + > > + return FALSE; > > +} > > + > > +/* Convert "if (test) x op=3D a;" to a branchless sequence using the > > + canonical form for a conditional-zero. */ > > +static int > > +noce_try_condzero_arith (struct noce_if_info *if_info) > > +{ > > + rtx target; > > + rtx_insn *seq; > > + rtx_code op =3D GET_CODE (if_info->a); > > + const rtx arg0 =3D XEXP (if_info->a, 0); > > + const rtx arg1 =3D XEXP (if_info->a, 1); > > + > > + if (!noce_simple_bbs (if_info)) > > + return FALSE; > > + > > + /* Check for no else condition. */ > > + if (!rtx_equal_p (if_info->x, if_info->b)) > > + return FALSE; > > + > > + if (op !=3D PLUS && op !=3D MINUS && op !=3D IOR && op !=3D XOR && > > + op !=3D ASHIFT && op !=3D ASHIFTRT && op !=3D LSHIFTRT && op != =3D AND) > > + return FALSE; > > + > > + if (!rtx_equal_p (if_info->x, arg0)) > > + return FALSE; > > + > > + start_sequence (); > > + > > + target =3D noce_emit_condzero(if_info, arg1, op !=3D AND ? true : fa= lse); > > + > > + if (target) > > + { > > + rtx op1 =3D if_info->x; > > + > > + if (op =3D=3D AND) > > + { > > + /* Emit "tmp =3D x & val;" followed by "tmp |=3D !cond ? x : = 0;" */ > > + op1 =3D expand_simple_binop (GET_MODE (if_info->x), AND, op1, > > + arg1, NULL_RTX, 0, OPTAB_WIDEN); > > + op =3D IOR; > > + } > > + > > + if (op1) > > + target =3D expand_simple_binop (GET_MODE (if_info->x), op, op1, > > + target, if_info->x, 0, OPTAB_WIDE= N); > > + } > > + > > + if (target) > > + { > > + if (target !=3D if_info->x) > > + noce_emit_move_insn (if_info->x, target); > > + > > + seq =3D end_ifcvt_sequence (if_info); > > + if (!seq || !targetm.noce_conversion_profitable_p (seq, if_info)= ) > > + return FALSE; > > + > > + emit_insn_before_setloc(seq, if_info->jump, > > + INSN_LOCATION(if_info->insn_a)); > > + if_info->transform_name =3D "noce_try_condzero_arith"; > > + > > + return TRUE; > > + } > > + > > + end_sequence (); > > + > > + return FALSE; > > +} > > + > > /* Convert "if (test) x =3D 0;" to "x &=3D -(test =3D=3D 0);" */ > > > > static int > > @@ -3967,8 +4177,12 @@ noce_process_if_block (struct noce_if_info *if_i= nfo) > > { > > if (noce_try_addcc (if_info)) > > goto success; > > + if (noce_try_condzero (if_info)) > > + goto success; > > if (noce_try_store_flag_mask (if_info)) > > goto success; > > + if (noce_try_condzero_arith (if_info)) > > + goto success; > > if (HAVE_conditional_move > > && noce_try_cmove_arith (if_info)) > > goto success; > > diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-and-01.c b/= gcc/testsuite/gcc.target/riscv/xventanacondops-and-01.c > > new file mode 100644 > > index 00000000000..9b26cdf0513 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-and-01.c > > @@ -0,0 +1,16 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=3Drv64gc_xventanacondops -mabi=3Dlp64" } */ > > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > > + > > +long and1(long a, long b, long c, long d) > > +{ > > + if (c < d) > > + a &=3D b; > > + > > + return a; > > +} > > + > > +/* { dg-final { scan-assembler-times "and\t" 1 } } */ > > +/* { dg-final { scan-assembler-times "slt" 1 } } */ > > +/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */ > > +/* { dg-final { scan-assembler-times "or\t" 1 } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-and-02.c b/= gcc/testsuite/gcc.target/riscv/xventanacondops-and-02.c > > new file mode 100644 > > index 00000000000..66d2ec10211 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-and-02.c > > @@ -0,0 +1,15 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=3Drv64gc_xventanacondops -mabi=3Dlp64" } */ > > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > > + > > +int and2(int a, int b, long c) > > +{ > > + if (c) > > + a &=3D b; > > + > > + return a; > > +} > > + > > +/* { dg-final { scan-assembler-times "and\t" 1 } } */ > > +/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */ > > +/* { dg-final { scan-assembler-times "or\t" 1 } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-01.c b/g= cc/testsuite/gcc.target/riscv/xventanacondops-eq-01.c > > new file mode 100644 > > index 00000000000..bc877d9e81b > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-01.c > > @@ -0,0 +1,11 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=3Drv64gc_xventanacondops -mabi=3Dlp64" } */ > > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ > > + > > +long > > +eq1 (long a, long b) > > +{ > > + return (a =3D=3D 0) ? b : 0; > > +} > > + > > +/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-02.c b/g= cc/testsuite/gcc.target/riscv/xventanacondops-eq-02.c > > new file mode 100644 > > index 00000000000..28317613ba8 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-02.c > > @@ -0,0 +1,14 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=3Drv64gc_xventanacondops -mabi=3Dlp64" } */ > > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ > > + > > +long > > +eq2 (long a, long b) > > +{ > > + if (a =3D=3D 0) > > + return b; > > + > > + return 0; > > +} > > + > > +/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-01.c b/g= cc/testsuite/gcc.target/riscv/xventanacondops-lt-01.c > > new file mode 100644 > > index 00000000000..db7498801f9 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-01.c > > @@ -0,0 +1,16 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=3Drv64gc_xventanacondops -mabi=3Dlp64" } */ > > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > > + > > +long long sink (long long); > > + > > +long long lt3 (long long a, long long b) > > +{ > > + if (a < b) > > + b =3D 0; > > + > > + return sink(b); > > +} > > + > > +/* { dg-final { scan-assembler-times "vt.maskcn\" 1 } } */ > > +/* { dg-final { scan-assembler-times "slt\t" 1 } } */ > > diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-01.c b/g= cc/testsuite/gcc.target/riscv/xventanacondops-ne-01.c > > new file mode 100644 > > index 00000000000..eff1486828c > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-01.c > > @@ -0,0 +1,11 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=3Drv64gc_xventanacondops -mabi=3Dlp64" } */ > > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ > > + > > +long long ne1(long long a, long long b) > > +{ > > + return (a !=3D 0) ? b : 0; > > +} > > + > > +/* { dg-final { scan-assembler-times "vt.maskc" 1 } } */ > > + > > diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c b/= gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c > > new file mode 100644 > > index 00000000000..43020790a22 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c > > @@ -0,0 +1,14 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-march=3Drv64gc_xventanacondops -mabi=3Dlp64" } */ > > +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ > > + > > +long xor1(long crc, long poly) > > +{ > > + if (crc & 1) > > + crc ^=3D poly; > > + > > + return crc; > > +} > > + > > +/* { dg-final { scan-assembler-times "vt.maskc" 1 } } */ > > +/* { dg-final { scan-assembler-times "xor\t" 1 } } */ > > -- > > 2.34.1 > >