From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by sourceware.org (Postfix) with ESMTPS id 5C38B38493E5 for ; Mon, 21 Nov 2022 10:14:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5C38B38493E5 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lj1-x22e.google.com with SMTP id s24so13918265ljs.11 for ; Mon, 21 Nov 2022 02:14:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=36CWpeUOYrMaxAtkqR1FcIPBlu9L3UO7bXLn2H+niII=; b=W1AuK9XRA5oUVhXTJXR1KAP86SfWiYpkzq3An+StcqYsWpuQpmtcY+cXNATOndF3aJ dtZmGKze2w4pIIFo8wSr/9qe8ApaZQNrqG+Ti6gUduhR8p31eCB64VgOiL3KO4R9/L4e 5OqPfesRVAr3p6TqfXqzQhGzQmycZU801v/biuvrApYnAHBNxk5kAAjAha6a2OjuR8xH 1CJxqNLcJpJ+yXnPmleaIaIJ0J1Phfgepqj0P5owUh8kIvKxYpbDaVYvhkM9/tVsFg0L 2I7fifC7i4S+9tj9SPU/ADmSjuvbBic7/AaegTPgc1ax/uToo/kvMZV9Utqo5zrlKqji M/eQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=36CWpeUOYrMaxAtkqR1FcIPBlu9L3UO7bXLn2H+niII=; b=5vf3X5KSLrqmyXxI9RQHukYXijMT21yjQ4AUP7pV80ws8qTnG1HfOBZdJhaLmCNO9K 0Z6gKN7P79zNc1edyv2k5cYfErONiObYzr8SLWrU7xHZpz3qSIHtFmiRAnGps4hXG0u7 mbF4HCwxsnKs7EqBq6YzQQ5Y1Irq1NyFbWicfzeTxU1eRYlCBR2hm0KxvERhIw/bH03s 7EoVaOZ2RMQ0yafDlsXKRV8Qol8SyhbUmEiVIUI6WGitO1O2NikC9sWsWdxMtjFogJZG 7uqL41R99L+h66bKC13cJoBiAXfy7oCSN44y4HmybX8q530N5eFtZKGS+bwmguzee1sa h90w== X-Gm-Message-State: ANoB5pnNH0HTBN3qtxXhabbFWTmECQ56exI8MTAH1vZiZ4O1T8UQYct1 DrJqp7NDHg3OmhBcL8Mt3xF5ZPZUPim0WdP25sdA8A== X-Google-Smtp-Source: AA0mqf6ZwxcJxGgzLDBBJzIZP9GfxypdLqfgO9sXz2OZcfnhs1ZySjIuT8neIVnb+VWigrgsOUSGwNTkpwpeDrKJmz8= X-Received: by 2002:a2e:a544:0:b0:278:f5b8:82c8 with SMTP id e4-20020a2ea544000000b00278f5b882c8mr2032686ljn.228.1669025644760; Mon, 21 Nov 2022 02:14:04 -0800 (PST) MIME-Version: 1.0 References: <20221109230718.3240479-1-philipp.tomsich@vrull.eu> <84ccfc10-df8c-5c77-913e-2819c7a14ee4@gmail.com> <966b3a77-5cda-c4d0-be4e-2083c502ba05@ventanamicro.com> In-Reply-To: From: Philipp Tomsich Date: Mon, 21 Nov 2022 11:13:53 +0100 Message-ID: Subject: Re: [PATCH] RISC-V: Optimise adding a (larger than simm12) constant To: Kito Cheng Cc: Jeff Law , Jeff Law , gcc-patches@gcc.gnu.org, Christoph Muellner , Palmer Dabbelt , Vineet Gupta Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,JMQ_SPF_NEUTRAL,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, 21 Nov 2022 at 04:11, Kito Cheng wrote: > > > @@ -464,6 +464,60 @@ > > [(set_attr "type" "arith") > > (set_attr "mode" "DI")]) > > > > +(define_expand "add3" > > + [(set (match_operand:GPR 0 "register_operand" "=r,r") > > + (plus:GPR (match_operand:GPR 1 "register_operand" " r,r") > > + (match_operand:GPR 2 "addi_operand" " r,I")))] > > Is it possible to just define a predicate that accepts > register_operand and CONST_INT_P, > and then handle all cases in add3 pattern? Great suggestion. > > My point is put all check in one place: > > e.g. > check TARGET_ZBA && const_arith_shifted123_operand (operands[2], > mode) in add3 > rather than check TARGET_ZBA in addi_operand and use sh[123]add in > add3 without check. > > and that also means we need to sync addi_opearnad and add3 > once we have extension XX could improve addi codegen. > > > > + "" > > +{ > > + if (arith_operand (operands[2], mode)) > > + emit_insn (gen_riscv_add3 (operands[0], operands[1], operands[2])); > > + else if (const_arith_2simm12_operand (operands[2], mode)) > > const_arith_2simm12_operand only used once, could you inline the condition here? If we handle all cases in a single pattern, we'll punt this to riscv.cc anyway. So let's see how the code looks once we have a single predicate and do the inlining there... > > > + { > > + /* Split into two immediates that add up to the desired value: > > + * e.g., break up "a + 2445" into: > > + * addi a0,a0,2047 > > + * addi a0,a0,398 > > + */ > > + > > + HOST_WIDE_INT val = INTVAL (operands[2]); > > + HOST_WIDE_INT saturated = HOST_WIDE_INT_M1U << (IMM_BITS - 1); > > + > > + if (val >= 0) > > + saturated = ~saturated; > > + > > + val -= saturated; > > + > > + rtx tmp = gen_reg_rtx (mode); > > + emit_insn (gen_riscv_add3 (tmp, operands[1], GEN_INT (saturated))); > > + emit_insn (gen_riscv_add3 (operands[0], tmp, GEN_INT (val))); > > + } > > + else if (mode == word_mode > > + && const_arith_shifted123_operand (operands[2], mode)) > > Same for const_arith_shifted123_operand. > > > + { > > + /* Use a sh[123]add and an immediate shifted down by 1, 2, or 3. */ > > + > > + HOST_WIDE_INT val = INTVAL (operands[2]); > > + int shamt = ctz_hwi (val); > > + > > + if (shamt > 3) > > + shamt = 3; > > + > > + rtx tmp = gen_reg_rtx (mode); > > + emit_insn (gen_rtx_SET (tmp, GEN_INT (val >> shamt))); > > + > > + /* We don't use gen_riscv_shNadd here, as it will only exist for > > + . Instead we build up its canonical form directly. */ > > + rtx shifted_imm = gen_rtx_ASHIFT (mode, tmp, GEN_INT (shamt)); > > + rtx shNadd = gen_rtx_PLUS (mode, shifted_imm, operands[1]); > > + emit_insn (gen_rtx_SET (operands[0], shNadd)); > > + } > > + else > > + FAIL; > > Seems add3 FAIL will cause problems, we need either add something like: > > operands[2] = force_reg (mode, operands[2]); > emit_insn (gen_rtx_SET (operands[0], > gen_rtx_PLUS (mode, > operands[1], operands[2]))); > > Or just gcc_unreachable () if we keep using addi_operand to guard this pattern. This is a case for "gcc_unreachable ();". The change will be in v2. Thanks, Philipp.