From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by sourceware.org (Postfix) with ESMTPS id 924BF3858D39 for ; Wed, 15 Mar 2023 09:02:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 924BF3858D39 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ed1-x52f.google.com with SMTP id r11so20931475edd.5 for ; Wed, 15 Mar 2023 02:02:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1678870937; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=X6bSPJmH06yNwRh2Cu/6iRZ22eId7U6ziUdrqfpUZHw=; b=N7JxHXA+iYsn051PcrRk8iT/0hIvrDu/cXcbGWJg0h4gBNtKoErZNZ/ovK7NfxF6X2 P+mk/Y4jHQpk5OuG7Do1Xk126P10vDIFw5i/DSdTvIxqKSWCSN5B6C/wyo2r56SK+v1i 6SzgPhDe/C5XVXQDitmHhvlIUnzyqg9ndyFd/MdVchs0M83TdJkB/ZQpZeKDPylmWiMc IchZLSHjjG87ZbAgH3md8SC9ccJXxG6oCP93HcK5WXY/djB3tqsnlDNNBNtSsObEAK/8 dwmFmexCtRsos5sx/Mb2e8CaSCUV9sOMBQ0RCoUB299pT2dRFd/aPg3/vcCyQeX8H0HS YNbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678870937; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=X6bSPJmH06yNwRh2Cu/6iRZ22eId7U6ziUdrqfpUZHw=; b=FguvCzcP2Fl0JlzInfWLHQOd5ArjqwJEQXYtu57r81RQXyVCS6I8O4YFXD5suBF3Cl OfYs5Bw4gUAsvZ0VcQRUlk5CkV9BJ1XAumqoGj3K8FMvMVBz7NpXq20OJeWqTZ6zw0Bg LiKHNO5Cfrs9tsoltKAtB5YlVyxZLfXEnSnXuAxOckqU9PXONRb6Xt9tRtaSlBC2tHkA vomDud3ElV/lcm8/O8iga6jTddZH7MTOU3sX4iB9Oe/mqzfQBCYnsXOaHfnZ4YY5m2cl 6nCQ/j/5HDGYCI3cNwF7lJQ4l4XquG4yyqjDoKe6CqJ/8AFnrD8f4dzi4/OPMGp2cR2V 3sBQ== X-Gm-Message-State: AO0yUKVIcFumnaCBmG0oNUbialwcDhgBVeeshLGJWzV1d0UCgRXP0dDd pik5hRIBFNGBSqykcFdXSshmduXay4SHTXHgpPe/Hg== X-Google-Smtp-Source: AK7set9wb6TzVaR4F56ALuKlYcGddm+PYMHgtAzn7NqxDqlgXRUZ0LRdefVO7HARXiIYVt24T89dXusyhY807rn9xiI= X-Received: by 2002:a17:907:d86:b0:8b2:d30:e728 with SMTP id go6-20020a1709070d8600b008b20d30e728mr2964366ejc.1.1678870937237; Wed, 15 Mar 2023 02:02:17 -0700 (PDT) MIME-Version: 1.0 References: <20230302083534.4076244-1-christoph.muellner@vrull.eu> In-Reply-To: From: Philipp Tomsich Date: Wed, 15 Mar 2023 10:02:06 +0100 Message-ID: Subject: Re: [PATCH v4 0/9] RISC-V: Add XThead* extension support To: Kito Cheng Cc: Christoph Muellner , gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu , Andrew Pinski , Hans-Peter Nilsson Content-Type: multipart/alternative; boundary="000000000000d68def05f6ec9953" X-Spam-Status: No, score=-3.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,HTML_MESSAGE,JMQ_SPF_NEUTRAL,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000d68def05f6ec9953 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Sun, 5 Mar 2023 at 11:19, Kito Cheng wrote: > LGTM :) > Applied to master, thanks! --Philipp. On Thu, Mar 2, 2023 at 4:36=E2=80=AFPM Christoph Muellner > wrote: > > > > From: Christoph M=C3=BCllner > > > > This series introduces support for the T-Head specific RISC-V ISA > extensions > > which are available e.g. on the T-Head XuanTie C906. > > > > The ISA spec can be found here: > > https://github.com/T-head-Semi/thead-extension-spec > > > > This series adds support for the following XThead* extensions: > > * XTheadBa > > * XTheadBb > > * XTheadBs > > * XTheadCmo > > * XTheadCondMov > > * XTheadFmv > > * XTheadInt > > * XTheadMac > > * XTheadMemPair > > * XTheadSync > > > > All extensions are properly integrated and the included tests > > demonstrate the improvements of the generated code. > > > > The series also introduces support for "-mcpu=3Dthead-c906", which also > > enables all available XThead* ISA extensions of the T-Head C906. > > > > All patches have been tested and don't introduce regressions for RV32 or > RV64. > > The patches have also been tested with SPEC CPU2017 on QEMU and real HW > > (D1 board). > > > > Support patches for these extensions for Binutils, QEMU, and LLVM have > > already been merged in the corresponding upstream projects. > > > > Patches 1-8 from this series (everything except the last one) got an ACK > > by Kito. However, since there were a few comments after the ACK, I > > decided to send out a v4, so that reviewers can verify that their > > comments have been addressed properly. > > > > Note, that there was a concern raised by Andrew Pinski (on CC), which > > might not be resolved with this series (I could not reproduce the issue, > > but I might have misunderstood something). > > > > Changes in v4: > > - Drop XTheadMemIdx and XTheadFMemIdx (will be a follow-up series) > > - Replace 'immediate_operand' by 'const_int_operand' in many patterns > > - Small cleanups in XTheadBb > > - Factor out C code into thead.cc (XTheadMemPair) to minimize changes in > > riscv.cc > > > > Changes in v3: > > - Bugfix in XTheadBa > > - Rewrite of XTheadMemPair > > - Inclusion of XTheadMemIdx and XTheadFMemIdx > > > > Christoph M=C3=BCllner (9): > > riscv: Add basic XThead* vendor extension support > > riscv: riscv-cores.def: Add T-Head XuanTie C906 > > riscv: thead: Add support for the XTheadBa ISA extension > > riscv: thead: Add support for the XTheadBs ISA extension > > riscv: thead: Add support for the XTheadBb ISA extension > > riscv: thead: Add support for the XTheadCondMov ISA extensions > > riscv: thead: Add support for the XTheadMac ISA extension > > riscv: thead: Add support for the XTheadFmv ISA extension > > riscv: thead: Add support for the XTheadMemPair ISA extension > > > > gcc/common/config/riscv/riscv-common.cc | 26 ++ > > gcc/config.gcc | 1 + > > gcc/config/riscv/bitmanip.md | 52 ++- > > gcc/config/riscv/constraints.md | 8 + > > gcc/config/riscv/iterators.md | 4 + > > gcc/config/riscv/peephole.md | 56 +++ > > gcc/config/riscv/riscv-cores.def | 4 + > > gcc/config/riscv/riscv-opts.h | 26 ++ > > gcc/config/riscv/riscv-protos.h | 16 +- > > gcc/config/riscv/riscv.cc | 226 +++++++-- > > gcc/config/riscv/riscv.md | 67 ++- > > gcc/config/riscv/riscv.opt | 3 + > > gcc/config/riscv/t-riscv | 4 + > > gcc/config/riscv/thead.cc | 427 ++++++++++++++++++ > > gcc/config/riscv/thead.md | 346 ++++++++++++++ > > .../gcc.target/riscv/mcpu-thead-c906.c | 28 ++ > > .../gcc.target/riscv/xtheadba-addsl.c | 55 +++ > > gcc/testsuite/gcc.target/riscv/xtheadba.c | 14 + > > gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c | 20 + > > .../gcc.target/riscv/xtheadbb-extu-2.c | 22 + > > .../gcc.target/riscv/xtheadbb-extu.c | 22 + > > gcc/testsuite/gcc.target/riscv/xtheadbb-ff1.c | 18 + > > gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c | 45 ++ > > .../gcc.target/riscv/xtheadbb-srri.c | 25 + > > gcc/testsuite/gcc.target/riscv/xtheadbb.c | 14 + > > gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c | 13 + > > gcc/testsuite/gcc.target/riscv/xtheadbs.c | 14 + > > gcc/testsuite/gcc.target/riscv/xtheadcmo.c | 14 + > > .../riscv/xtheadcondmov-mveqz-imm-eqz.c | 38 ++ > > .../riscv/xtheadcondmov-mveqz-imm-not.c | 38 ++ > > .../riscv/xtheadcondmov-mveqz-reg-eqz.c | 38 ++ > > .../riscv/xtheadcondmov-mveqz-reg-not.c | 38 ++ > > .../riscv/xtheadcondmov-mvnez-imm-cond.c | 38 ++ > > .../riscv/xtheadcondmov-mvnez-imm-nez.c | 38 ++ > > .../riscv/xtheadcondmov-mvnez-reg-cond.c | 38 ++ > > .../riscv/xtheadcondmov-mvnez-reg-nez.c | 38 ++ > > .../gcc.target/riscv/xtheadcondmov.c | 14 + > > .../gcc.target/riscv/xtheadfmemidx.c | 14 + > > .../gcc.target/riscv/xtheadfmv-fmv.c | 24 + > > gcc/testsuite/gcc.target/riscv/xtheadfmv.c | 14 + > > gcc/testsuite/gcc.target/riscv/xtheadint.c | 14 + > > .../gcc.target/riscv/xtheadmac-mula-muls.c | 43 ++ > > gcc/testsuite/gcc.target/riscv/xtheadmac.c | 14 + > > gcc/testsuite/gcc.target/riscv/xtheadmemidx.c | 14 + > > .../gcc.target/riscv/xtheadmempair-1.c | 98 ++++ > > .../gcc.target/riscv/xtheadmempair-2.c | 84 ++++ > > .../gcc.target/riscv/xtheadmempair-3.c | 29 ++ > > .../gcc.target/riscv/xtheadmempair.c | 13 + > > gcc/testsuite/gcc.target/riscv/xtheadsync.c | 14 + > > 49 files changed, 2196 insertions(+), 67 deletions(-) > > create mode 100644 gcc/config/riscv/thead.cc > > create mode 100644 gcc/config/riscv/thead.md > > create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu-2.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ff1.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-srri.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcmo.c > > create mode 100644 > gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c > > create mode 100644 > gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c > > create mode 100644 > gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c > > create mode 100644 > gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c > > create mode 100644 > gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c > > create mode 100644 > gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c > > create mode 100644 > gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c > > create mode 100644 > gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmv.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadint.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmac-mula-muls.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmac.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-1.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-2.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-3.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadsync.c > > > > -- > > 2.39.2 > > > --000000000000d68def05f6ec9953--