[ARM] PR97906 - Missed lowering abs(a) >= abs(b) to vacge

[ARM] PR97906 - Missed lowering abs(a) >= abs(b) to vacge

[Prathamesh Kulkarni]

[-- Attachment #1: Type: text/plain, Size: 1311 bytes --]

Hi,
As mentioned in PR, for following test-case:

#include <arm_neon.h>

uint32x2_t f1(float32x2_t a, float32x2_t b)
{
  return vabs_f32 (a) >= vabs_f32 (b);
}

uint32x2_t f2(float32x2_t a, float32x2_t b)
{
  return (uint32x2_t) __builtin_neon_vcagev2sf (a, b);
}

We generate vacge for f2, but with -ffast-math, we generate following for f1:
f1:
        vabs.f32        d1, d1
        vabs.f32        d0, d0
        vcge.f32        d0, d0, d1
        bx      lr

This happens because, the middle-end inverts the comparison to b <= a,
.optimized dump:
 _8 = __builtin_neon_vabsv2sf (a_4(D));
  _7 = __builtin_neon_vabsv2sf (b_5(D));
  _1 = _7 <= _8;
  _2 = VIEW_CONVERT_EXPR<vector(2) int>(_1);
  _6 = VIEW_CONVERT_EXPR<uint32x2_t>(_2);
  return _6;

and combine fails to match the following pattern:
(set (reg:V2SI 121)
    (neg:V2SI (le:V2SI (abs:V2SF (reg:V2SF 123))
            (abs:V2SF (reg:V2SF 122)))))

because neon_vca<cmp_op><mode> pattern has GTGE code iterator.
The attached patch adjusts the neon_vca patterns to use GLTE instead
similar to neon_vca<cmp_op><mode>_fp16insn, and removes NEON_VACMP iterator.
Code-gen with patch:
f1:
        vacle.f32       d0, d1, d0
        bx      lr

Bootstrapped + tested on arm-linux-gnueabihf and cross-tested on arm*-*-*.
OK to commit ?

Thanks,
Prathamesh

[-- Attachment #2: pr97906-2.txt --]
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2021-06-01  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>

        PR target/97906
        * config/arm/iterators.md (NEON_VACMP): Remove.
        * config/arm/neon.md (neon_vca<cmp_op><mode>): Use GLTE instead of GTGE iterator.
        (neon_vca<cmp_op><mode>_insn): Likewise.
        (neon_vca<cmp_op_unsp><mode>_insn_unspec): Use NEON_VAGLTE instead of NEON_VACMP.

testsuite/
	* gcc.target/arm/simd/pr97906.c: New test.

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 3042bafc6c6..0e0e825225a 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -364,8 +364,6 @@
 (define_int_iterator NEON_VCMP [UNSPEC_VCEQ UNSPEC_VCGT UNSPEC_VCGE
 				UNSPEC_VCLT UNSPEC_VCLE])
 
-(define_int_iterator NEON_VACMP [UNSPEC_VCAGE UNSPEC_VCAGT])
-
 (define_int_iterator NEON_VAGLTE [UNSPEC_VCAGE UNSPEC_VCAGT
 				  UNSPEC_VCALE UNSPEC_VCALT])
 
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index cc82d068a1c..ccc99603531 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -2400,7 +2400,7 @@
 (define_expand "neon_vca<cmp_op><mode>"
   [(set (match_operand:<V_cmp_result> 0 "s_register_operand")
         (neg:<V_cmp_result>
-          (GTGE:<V_cmp_result>
+          (GLTE:<V_cmp_result>
             (abs:VCVTF (match_operand:VCVTF 1 "s_register_operand"))
             (abs:VCVTF (match_operand:VCVTF 2 "s_register_operand")))))]
   "TARGET_NEON"
@@ -2419,7 +2419,7 @@
 (define_insn "neon_vca<cmp_op><mode>_insn"
   [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
         (neg:<V_cmp_result>
-          (GTGE:<V_cmp_result>
+          (GLTE:<V_cmp_result>
             (abs:VCVTF (match_operand:VCVTF 1 "s_register_operand" "w"))
             (abs:VCVTF (match_operand:VCVTF 2 "s_register_operand" "w")))))]
   "TARGET_NEON && flag_unsafe_math_optimizations"
@@ -2431,7 +2431,7 @@
   [(set (match_operand:<V_cmp_result> 0 "s_register_operand" "=w")
         (unspec:<V_cmp_result> [(match_operand:VCVTF 1 "s_register_operand" "w")
 		                (match_operand:VCVTF 2 "s_register_operand" "w")]
-                               NEON_VACMP))]
+                               NEON_VAGLTE))]
   "TARGET_NEON"
   "vac<cmp_op_unsp>.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
   [(set_attr "type" "neon_fp_compare_s<q>")]
diff --git a/gcc/testsuite/gcc.target/arm/simd/pr97906.c b/gcc/testsuite/gcc.target/arm/simd/pr97906.c
new file mode 100644
index 00000000000..7c972e311ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/pr97906.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint32x2_t f1(float32x2_t a, float32x2_t b)
+{
+  return vabs_f32 (a) >= vabs_f32 (b);
+}
+
+/* { dg-final { scan-assembler-times {\tvacle.f32\td[0-9]+, d[0-9]+, d[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-not "vabs" } } */

Re: [ARM] PR97906 - Missed lowering abs(a) >= abs(b) to vacge

[Prathamesh Kulkarni]

On Tue, 1 Jun 2021 at 16:03, Prathamesh Kulkarni
<prathamesh.kulkarni@linaro.org> wrote:
>
> Hi,
> As mentioned in PR, for following test-case:
>
> #include <arm_neon.h>
>
> uint32x2_t f1(float32x2_t a, float32x2_t b)
> {
>   return vabs_f32 (a) >= vabs_f32 (b);
> }
>
> uint32x2_t f2(float32x2_t a, float32x2_t b)
> {
>   return (uint32x2_t) __builtin_neon_vcagev2sf (a, b);
> }
>
> We generate vacge for f2, but with -ffast-math, we generate following for f1:
> f1:
>         vabs.f32        d1, d1
>         vabs.f32        d0, d0
>         vcge.f32        d0, d0, d1
>         bx      lr
>
> This happens because, the middle-end inverts the comparison to b <= a,
> .optimized dump:
>  _8 = __builtin_neon_vabsv2sf (a_4(D));
>   _7 = __builtin_neon_vabsv2sf (b_5(D));
>   _1 = _7 <= _8;
>   _2 = VIEW_CONVERT_EXPR<vector(2) int>(_1);
>   _6 = VIEW_CONVERT_EXPR<uint32x2_t>(_2);
>   return _6;
>
> and combine fails to match the following pattern:
> (set (reg:V2SI 121)
>     (neg:V2SI (le:V2SI (abs:V2SF (reg:V2SF 123))
>             (abs:V2SF (reg:V2SF 122)))))
>
> because neon_vca<cmp_op><mode> pattern has GTGE code iterator.
> The attached patch adjusts the neon_vca patterns to use GLTE instead
> similar to neon_vca<cmp_op><mode>_fp16insn, and removes NEON_VACMP iterator.
> Code-gen with patch:
> f1:
>         vacle.f32       d0, d1, d0
>         bx      lr
>
> Bootstrapped + tested on arm-linux-gnueabihf and cross-tested on arm*-*-*.
> OK to commit ?
ping https://gcc.gnu.org/pipermail/gcc-patches/2021-June/571568.html

Thanks,
Prathamesh
>
> Thanks,
> Prathamesh

Re: [ARM] PR97906 - Missed lowering abs(a) >= abs(b) to vacge

[Prathamesh Kulkarni]

On Mon, 7 Jun 2021 at 12:46, Prathamesh Kulkarni
<prathamesh.kulkarni@linaro.org> wrote:
>
> On Tue, 1 Jun 2021 at 16:03, Prathamesh Kulkarni
> <prathamesh.kulkarni@linaro.org> wrote:
> >
> > Hi,
> > As mentioned in PR, for following test-case:
> >
> > #include <arm_neon.h>
> >
> > uint32x2_t f1(float32x2_t a, float32x2_t b)
> > {
> >   return vabs_f32 (a) >= vabs_f32 (b);
> > }
> >
> > uint32x2_t f2(float32x2_t a, float32x2_t b)
> > {
> >   return (uint32x2_t) __builtin_neon_vcagev2sf (a, b);
> > }
> >
> > We generate vacge for f2, but with -ffast-math, we generate following for f1:
> > f1:
> >         vabs.f32        d1, d1
> >         vabs.f32        d0, d0
> >         vcge.f32        d0, d0, d1
> >         bx      lr
> >
> > This happens because, the middle-end inverts the comparison to b <= a,
> > .optimized dump:
> >  _8 = __builtin_neon_vabsv2sf (a_4(D));
> >   _7 = __builtin_neon_vabsv2sf (b_5(D));
> >   _1 = _7 <= _8;
> >   _2 = VIEW_CONVERT_EXPR<vector(2) int>(_1);
> >   _6 = VIEW_CONVERT_EXPR<uint32x2_t>(_2);
> >   return _6;
> >
> > and combine fails to match the following pattern:
> > (set (reg:V2SI 121)
> >     (neg:V2SI (le:V2SI (abs:V2SF (reg:V2SF 123))
> >             (abs:V2SF (reg:V2SF 122)))))
> >
> > because neon_vca<cmp_op><mode> pattern has GTGE code iterator.
> > The attached patch adjusts the neon_vca patterns to use GLTE instead
> > similar to neon_vca<cmp_op><mode>_fp16insn, and removes NEON_VACMP iterator.
> > Code-gen with patch:
> > f1:
> >         vacle.f32       d0, d1, d0
> >         bx      lr
> >
> > Bootstrapped + tested on arm-linux-gnueabihf and cross-tested on arm*-*-*.
> > OK to commit ?
> ping https://gcc.gnu.org/pipermail/gcc-patches/2021-June/571568.html
ping * 2 https://gcc.gnu.org/pipermail/gcc-patches/2021-June/571568.html

Thanks,
Prathamesh
>
> Thanks,
> Prathamesh
> >
> > Thanks,
> > Prathamesh

RE: [ARM] PR97906 - Missed lowering abs(a) >= abs(b) to vacge

[Kyrylo Tkachov]

> -----Original Message-----
> From: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
> Sent: 14 June 2021 08:58
> To: gcc Patches <gcc-patches@gcc.gnu.org>; Kyrylo Tkachov
> <Kyrylo.Tkachov@arm.com>
> Subject: Re: [ARM] PR97906 - Missed lowering abs(a) >= abs(b) to vacge
> 
> On Mon, 7 Jun 2021 at 12:46, Prathamesh Kulkarni
> <prathamesh.kulkarni@linaro.org> wrote:
> >
> > On Tue, 1 Jun 2021 at 16:03, Prathamesh Kulkarni
> > <prathamesh.kulkarni@linaro.org> wrote:
> > >
> > > Hi,
> > > As mentioned in PR, for following test-case:
> > >
> > > #include <arm_neon.h>
> > >
> > > uint32x2_t f1(float32x2_t a, float32x2_t b)
> > > {
> > >   return vabs_f32 (a) >= vabs_f32 (b);
> > > }
> > >
> > > uint32x2_t f2(float32x2_t a, float32x2_t b)
> > > {
> > >   return (uint32x2_t) __builtin_neon_vcagev2sf (a, b);
> > > }
> > >
> > > We generate vacge for f2, but with -ffast-math, we generate following
> for f1:
> > > f1:
> > >         vabs.f32        d1, d1
> > >         vabs.f32        d0, d0
> > >         vcge.f32        d0, d0, d1
> > >         bx      lr
> > >
> > > This happens because, the middle-end inverts the comparison to b <= a,
> > > .optimized dump:
> > >  _8 = __builtin_neon_vabsv2sf (a_4(D));
> > >   _7 = __builtin_neon_vabsv2sf (b_5(D));
> > >   _1 = _7 <= _8;
> > >   _2 = VIEW_CONVERT_EXPR<vector(2) int>(_1);
> > >   _6 = VIEW_CONVERT_EXPR<uint32x2_t>(_2);
> > >   return _6;
> > >
> > > and combine fails to match the following pattern:
> > > (set (reg:V2SI 121)
> > >     (neg:V2SI (le:V2SI (abs:V2SF (reg:V2SF 123))
> > >             (abs:V2SF (reg:V2SF 122)))))
> > >
> > > because neon_vca<cmp_op><mode> pattern has GTGE code iterator.
> > > The attached patch adjusts the neon_vca patterns to use GLTE instead
> > > similar to neon_vca<cmp_op><mode>_fp16insn, and removes
> NEON_VACMP iterator.
> > > Code-gen with patch:
> > > f1:
> > >         vacle.f32       d0, d1, d0
> > >         bx      lr
> > >
> > > Bootstrapped + tested on arm-linux-gnueabihf and cross-tested on arm*-
> *-*.
> > > OK to commit ?

Is that inversion guaranteed to happen (is it a canonicalization rule)?
If so, ok.
Thanks,
Kyrill


> 
> Thanks,
> Prathamesh
> >
> > Thanks,
> > Prathamesh
> > >
> > > Thanks,
> > > Prathamesh

Re: [ARM] PR97906 - Missed lowering abs(a) >= abs(b) to vacge

[Prathamesh Kulkarni]

On Mon, 14 Jun 2021 at 16:15, Kyrylo Tkachov <Kyrylo.Tkachov@arm.com> wrote:
>
>
>
> > -----Original Message-----
> > From: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
> > Sent: 14 June 2021 08:58
> > To: gcc Patches <gcc-patches@gcc.gnu.org>; Kyrylo Tkachov
> > <Kyrylo.Tkachov@arm.com>
> > Subject: Re: [ARM] PR97906 - Missed lowering abs(a) >= abs(b) to vacge
> >
> > On Mon, 7 Jun 2021 at 12:46, Prathamesh Kulkarni
> > <prathamesh.kulkarni@linaro.org> wrote:
> > >
> > > On Tue, 1 Jun 2021 at 16:03, Prathamesh Kulkarni
> > > <prathamesh.kulkarni@linaro.org> wrote:
> > > >
> > > > Hi,
> > > > As mentioned in PR, for following test-case:
> > > >
> > > > #include <arm_neon.h>
> > > >
> > > > uint32x2_t f1(float32x2_t a, float32x2_t b)
> > > > {
> > > >   return vabs_f32 (a) >= vabs_f32 (b);
> > > > }
> > > >
> > > > uint32x2_t f2(float32x2_t a, float32x2_t b)
> > > > {
> > > >   return (uint32x2_t) __builtin_neon_vcagev2sf (a, b);
> > > > }
> > > >
> > > > We generate vacge for f2, but with -ffast-math, we generate following
> > for f1:
> > > > f1:
> > > >         vabs.f32        d1, d1
> > > >         vabs.f32        d0, d0
> > > >         vcge.f32        d0, d0, d1
> > > >         bx      lr
> > > >
> > > > This happens because, the middle-end inverts the comparison to b <= a,
> > > > .optimized dump:
> > > >  _8 = __builtin_neon_vabsv2sf (a_4(D));
> > > >   _7 = __builtin_neon_vabsv2sf (b_5(D));
> > > >   _1 = _7 <= _8;
> > > >   _2 = VIEW_CONVERT_EXPR<vector(2) int>(_1);
> > > >   _6 = VIEW_CONVERT_EXPR<uint32x2_t>(_2);
> > > >   return _6;
> > > >
> > > > and combine fails to match the following pattern:
> > > > (set (reg:V2SI 121)
> > > >     (neg:V2SI (le:V2SI (abs:V2SF (reg:V2SF 123))
> > > >             (abs:V2SF (reg:V2SF 122)))))
> > > >
> > > > because neon_vca<cmp_op><mode> pattern has GTGE code iterator.
> > > > The attached patch adjusts the neon_vca patterns to use GLTE instead
> > > > similar to neon_vca<cmp_op><mode>_fp16insn, and removes
> > NEON_VACMP iterator.
> > > > Code-gen with patch:
> > > > f1:
> > > >         vacle.f32       d0, d1, d0
> > > >         bx      lr
> > > >
> > > > Bootstrapped + tested on arm-linux-gnueabihf and cross-tested on arm*-
> > *-*.
> > > > OK to commit ?
>
> Is that inversion guaranteed to happen (is it a canonicalization rule)?
I think it follows the following rule for canonicalization from
tree_swap_operands_p:
  /* It is preferable to swap two SSA_NAME to ensure a canonical form
     for commutative and comparison operators.  Ensuring a canonical
     form allows the optimizers to find additional redundancies without
     having to explicitly check for both orderings.  */
  if (TREE_CODE (arg0) == SSA_NAME
      && TREE_CODE (arg1) == SSA_NAME
      && SSA_NAME_VERSION (arg0) > SSA_NAME_VERSION (arg1))
    return 1;

For the above test-case, it's ccp1 that inverts the comparison.
The input to ccp1 pass is:
  _12 = __builtin_neon_vabsv2sf (a_6(D));
  _14 = _12;
  _1 = _14;
  _11 = __builtin_neon_vabsv2sf (b_8(D));
  _16 = _11;
  _2 = _16;
  _3 = _1 >= _2;
  _4 = VEC_COND_EXPR <_3, { -1, -1 }, { 0, 0 }>;
  _10 = VIEW_CONVERT_EXPR<uint32x2_t>(_4);
  return _10;

_3 = _1 >= _2 is folded into:
_3 = _12 >= _11

Since _12 is higher ssa version than _11, it is canonicalized to:
_3 = _11 <= _12.

Thanks,
Prathamesh
> If so, ok.
> Thanks,
> Kyrill
>
>
> >
> > Thanks,
> > Prathamesh
> > >
> > > Thanks,
> > > Prathamesh
> > > >
> > > > Thanks,
> > > > Prathamesh

Re: [ARM] PR97906 - Missed lowering abs(a) >= abs(b) to vacge

[Prathamesh Kulkarni]

On Wed, 16 Jun 2021 at 15:49, Prathamesh Kulkarni
<prathamesh.kulkarni@linaro.org> wrote:
>
> On Mon, 14 Jun 2021 at 16:15, Kyrylo Tkachov <Kyrylo.Tkachov@arm.com> wrote:
> >
> >
> >
> > > -----Original Message-----
> > > From: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
> > > Sent: 14 June 2021 08:58
> > > To: gcc Patches <gcc-patches@gcc.gnu.org>; Kyrylo Tkachov
> > > <Kyrylo.Tkachov@arm.com>
> > > Subject: Re: [ARM] PR97906 - Missed lowering abs(a) >= abs(b) to vacge
> > >
> > > On Mon, 7 Jun 2021 at 12:46, Prathamesh Kulkarni
> > > <prathamesh.kulkarni@linaro.org> wrote:
> > > >
> > > > On Tue, 1 Jun 2021 at 16:03, Prathamesh Kulkarni
> > > > <prathamesh.kulkarni@linaro.org> wrote:
> > > > >
> > > > > Hi,
> > > > > As mentioned in PR, for following test-case:
> > > > >
> > > > > #include <arm_neon.h>
> > > > >
> > > > > uint32x2_t f1(float32x2_t a, float32x2_t b)
> > > > > {
> > > > >   return vabs_f32 (a) >= vabs_f32 (b);
> > > > > }
> > > > >
> > > > > uint32x2_t f2(float32x2_t a, float32x2_t b)
> > > > > {
> > > > >   return (uint32x2_t) __builtin_neon_vcagev2sf (a, b);
> > > > > }
> > > > >
> > > > > We generate vacge for f2, but with -ffast-math, we generate following
> > > for f1:
> > > > > f1:
> > > > >         vabs.f32        d1, d1
> > > > >         vabs.f32        d0, d0
> > > > >         vcge.f32        d0, d0, d1
> > > > >         bx      lr
> > > > >
> > > > > This happens because, the middle-end inverts the comparison to b <= a,
> > > > > .optimized dump:
> > > > >  _8 = __builtin_neon_vabsv2sf (a_4(D));
> > > > >   _7 = __builtin_neon_vabsv2sf (b_5(D));
> > > > >   _1 = _7 <= _8;
> > > > >   _2 = VIEW_CONVERT_EXPR<vector(2) int>(_1);
> > > > >   _6 = VIEW_CONVERT_EXPR<uint32x2_t>(_2);
> > > > >   return _6;
> > > > >
> > > > > and combine fails to match the following pattern:
> > > > > (set (reg:V2SI 121)
> > > > >     (neg:V2SI (le:V2SI (abs:V2SF (reg:V2SF 123))
> > > > >             (abs:V2SF (reg:V2SF 122)))))
> > > > >
> > > > > because neon_vca<cmp_op><mode> pattern has GTGE code iterator.
> > > > > The attached patch adjusts the neon_vca patterns to use GLTE instead
> > > > > similar to neon_vca<cmp_op><mode>_fp16insn, and removes
> > > NEON_VACMP iterator.
> > > > > Code-gen with patch:
> > > > > f1:
> > > > >         vacle.f32       d0, d1, d0
> > > > >         bx      lr
> > > > >
> > > > > Bootstrapped + tested on arm-linux-gnueabihf and cross-tested on arm*-
> > > *-*.
> > > > > OK to commit ?
> >
> > Is that inversion guaranteed to happen (is it a canonicalization rule)?
> I think it follows the following rule for canonicalization from
> tree_swap_operands_p:
>   /* It is preferable to swap two SSA_NAME to ensure a canonical form
>      for commutative and comparison operators.  Ensuring a canonical
>      form allows the optimizers to find additional redundancies without
>      having to explicitly check for both orderings.  */
>   if (TREE_CODE (arg0) == SSA_NAME
>       && TREE_CODE (arg1) == SSA_NAME
>       && SSA_NAME_VERSION (arg0) > SSA_NAME_VERSION (arg1))
>     return 1;
>
> For the above test-case, it's ccp1 that inverts the comparison.
> The input to ccp1 pass is:
>   _12 = __builtin_neon_vabsv2sf (a_6(D));
>   _14 = _12;
>   _1 = _14;
>   _11 = __builtin_neon_vabsv2sf (b_8(D));
>   _16 = _11;
>   _2 = _16;
>   _3 = _1 >= _2;
>   _4 = VEC_COND_EXPR <_3, { -1, -1 }, { 0, 0 }>;
>   _10 = VIEW_CONVERT_EXPR<uint32x2_t>(_4);
>   return _10;
>
> _3 = _1 >= _2 is folded into:
> _3 = _12 >= _11
>
> Since _12 is higher ssa version than _11, it is canonicalized to:
> _3 = _11 <= _12.
>
Hi Kyrill,
Is it OK to push given the above canonicalization ?

Thanks,
Prathamesh
> Thanks,
> Prathamesh
> > If so, ok.
> > Thanks,
> > Kyrill
> >
> >
> > >
> > > Thanks,
> > > Prathamesh
> > > >
> > > > Thanks,
> > > > Prathamesh
> > > > >
> > > > > Thanks,
> > > > > Prathamesh

RE: [ARM] PR97906 - Missed lowering abs(a) >= abs(b) to vacge

[Kyrylo Tkachov]

> -----Original Message-----
> From: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
> Sent: 21 June 2021 09:33
> To: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>
> Cc: gcc Patches <gcc-patches@gcc.gnu.org>
> Subject: Re: [ARM] PR97906 - Missed lowering abs(a) >= abs(b) to vacge
> 
> On Wed, 16 Jun 2021 at 15:49, Prathamesh Kulkarni
> <prathamesh.kulkarni@linaro.org> wrote:
> >
> > On Mon, 14 Jun 2021 at 16:15, Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>
> wrote:
> > >
> > >
> > >
> > > > -----Original Message-----
> > > > From: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
> > > > Sent: 14 June 2021 08:58
> > > > To: gcc Patches <gcc-patches@gcc.gnu.org>; Kyrylo Tkachov
> > > > <Kyrylo.Tkachov@arm.com>
> > > > Subject: Re: [ARM] PR97906 - Missed lowering abs(a) >= abs(b) to vacge
> > > >
> > > > On Mon, 7 Jun 2021 at 12:46, Prathamesh Kulkarni
> > > > <prathamesh.kulkarni@linaro.org> wrote:
> > > > >
> > > > > On Tue, 1 Jun 2021 at 16:03, Prathamesh Kulkarni
> > > > > <prathamesh.kulkarni@linaro.org> wrote:
> > > > > >
> > > > > > Hi,
> > > > > > As mentioned in PR, for following test-case:
> > > > > >
> > > > > > #include <arm_neon.h>
> > > > > >
> > > > > > uint32x2_t f1(float32x2_t a, float32x2_t b)
> > > > > > {
> > > > > >   return vabs_f32 (a) >= vabs_f32 (b);
> > > > > > }
> > > > > >
> > > > > > uint32x2_t f2(float32x2_t a, float32x2_t b)
> > > > > > {
> > > > > >   return (uint32x2_t) __builtin_neon_vcagev2sf (a, b);
> > > > > > }
> > > > > >
> > > > > > We generate vacge for f2, but with -ffast-math, we generate
> following
> > > > for f1:
> > > > > > f1:
> > > > > >         vabs.f32        d1, d1
> > > > > >         vabs.f32        d0, d0
> > > > > >         vcge.f32        d0, d0, d1
> > > > > >         bx      lr
> > > > > >
> > > > > > This happens because, the middle-end inverts the comparison to b
> <= a,
> > > > > > .optimized dump:
> > > > > >  _8 = __builtin_neon_vabsv2sf (a_4(D));
> > > > > >   _7 = __builtin_neon_vabsv2sf (b_5(D));
> > > > > >   _1 = _7 <= _8;
> > > > > >   _2 = VIEW_CONVERT_EXPR<vector(2) int>(_1);
> > > > > >   _6 = VIEW_CONVERT_EXPR<uint32x2_t>(_2);
> > > > > >   return _6;
> > > > > >
> > > > > > and combine fails to match the following pattern:
> > > > > > (set (reg:V2SI 121)
> > > > > >     (neg:V2SI (le:V2SI (abs:V2SF (reg:V2SF 123))
> > > > > >             (abs:V2SF (reg:V2SF 122)))))
> > > > > >
> > > > > > because neon_vca<cmp_op><mode> pattern has GTGE code
> iterator.
> > > > > > The attached patch adjusts the neon_vca patterns to use GLTE
> instead
> > > > > > similar to neon_vca<cmp_op><mode>_fp16insn, and removes
> > > > NEON_VACMP iterator.
> > > > > > Code-gen with patch:
> > > > > > f1:
> > > > > >         vacle.f32       d0, d1, d0
> > > > > >         bx      lr
> > > > > >
> > > > > > Bootstrapped + tested on arm-linux-gnueabihf and cross-tested on
> arm*-
> > > > *-*.
> > > > > > OK to commit ?
> > >
> > > Is that inversion guaranteed to happen (is it a canonicalization rule)?
> > I think it follows the following rule for canonicalization from
> > tree_swap_operands_p:
> >   /* It is preferable to swap two SSA_NAME to ensure a canonical form
> >      for commutative and comparison operators.  Ensuring a canonical
> >      form allows the optimizers to find additional redundancies without
> >      having to explicitly check for both orderings.  */
> >   if (TREE_CODE (arg0) == SSA_NAME
> >       && TREE_CODE (arg1) == SSA_NAME
> >       && SSA_NAME_VERSION (arg0) > SSA_NAME_VERSION (arg1))
> >     return 1;
> >
> > For the above test-case, it's ccp1 that inverts the comparison.
> > The input to ccp1 pass is:
> >   _12 = __builtin_neon_vabsv2sf (a_6(D));
> >   _14 = _12;
> >   _1 = _14;
> >   _11 = __builtin_neon_vabsv2sf (b_8(D));
> >   _16 = _11;
> >   _2 = _16;
> >   _3 = _1 >= _2;
> >   _4 = VEC_COND_EXPR <_3, { -1, -1 }, { 0, 0 }>;
> >   _10 = VIEW_CONVERT_EXPR<uint32x2_t>(_4);
> >   return _10;
> >
> > _3 = _1 >= _2 is folded into:
> > _3 = _12 >= _11
> >
> > Since _12 is higher ssa version than _11, it is canonicalized to:
> > _3 = _11 <= _12.
> >
> Hi Kyrill,
> Is it OK to push given the above canonicalization ?

Hi Prathamesh,

Yes, that's okay, thanks for checking.
Kyrill

> 
> Thanks,
> Prathamesh
> > Thanks,
> > Prathamesh
> > > If so, ok.
> > > Thanks,
> > > Kyrill
> > >
> > >
> > > >
> > > > Thanks,
> > > > Prathamesh
> > > > >
> > > > > Thanks,
> > > > > Prathamesh
> > > > > >
> > > > > > Thanks,
> > > > > > Prathamesh