From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x332.google.com (mail-wm1-x332.google.com [IPv6:2a00:1450:4864:20::332]) by sourceware.org (Postfix) with ESMTPS id B203A3858D33 for ; Wed, 25 Jan 2023 11:57:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B203A3858D33 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-wm1-x332.google.com with SMTP id bg13-20020a05600c3c8d00b003d9712b29d2so1051262wmb.2 for ; Wed, 25 Jan 2023 03:57:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=to:subject:message-id:date:from:in-reply-to:references:mime-version :from:to:cc:subject:date:message-id:reply-to; bh=WGJJTtQ6UitCilTwKzd500YU2OXkyw4ySa0nE8rj+Us=; b=uuVWf4NbDnqHmWa0+EiTwNy81Y/Dr4Pp3PuW/JAA6eEypMsGlNIbz3a7oh3o17d/Re 1cxSroOG9QGLC+fpn7D7uQr++aeVQ750e6iLZUJHAp5yW1jUGfwGKo3k38UDjrpqEiY6 uHndyX/zpHdGO1277AYvfZUNjFiMdKZxowD2LjUg+Hly9q+07jVBD5ABiVa8Mb2M2R5w Aj6yWO4WQ7h737L9CJAYJORODpqNiGQ3kxEHhkqFE0RH4HxFFWnKa6gnTyN8xFeZDQHF AHIeeJDwCJJBHuTdi7/7xMlsrkLZUGDsVsTGrZxXcu6vR7JPus6K+pPBLB0gft3JALQB cOhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=to:subject:message-id:date:from:in-reply-to:references:mime-version :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=WGJJTtQ6UitCilTwKzd500YU2OXkyw4ySa0nE8rj+Us=; b=uACnRhNpX1GKY9gVKCiXDFJIt87rkX03C/OQzGOP5swblbxJ8jetx+5hPhmQnvsJ3h tI8aPUKqSHiZIVRXP8kj5hP1yZEVz0svRhXfG1r4BvhhWPu7zDpgdpjnbQ+FfBga9dCm 2lxZN+0hl+O6UYBMKpav07o+JpiQOt0LQwPTzr7eDX9ODQ4T1VjjTYrVTr0tzwxW7vSI GpLRaC08D8f6O/+PoqqC5GujEIUP/DoZpTqSz/fvIqtGVBmmxRxLZWx20KhfgL08YtoI zEHFsWAuM3Y/MjWHePs/4q2c3XMGhEK9Xy071/W5L9WV2sKA66yFreSP/M/Os8dFsU4Y sk1g== X-Gm-Message-State: AFqh2krpCkgselJisbh7GJ6HV7Dv8ADBo/XgyszsUcIPLguB72EQ+YYw CtASp6LXNTHze5jMbrLA4VDPFWKLlNClPvfnwTf0iw== X-Google-Smtp-Source: AMrXdXvM5IEINQbarQ+rFvOnYBG30XtaVBACLVPMASqntqCVnMzIyw+TLhzngGB3vvd9YMQtYq394so9zSts15DrmVA= X-Received: by 2002:a05:600c:4215:b0:3b4:ff86:25af with SMTP id x21-20020a05600c421500b003b4ff8625afmr1288699wmh.68.1674647826387; Wed, 25 Jan 2023 03:57:06 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Prathamesh Kulkarni Date: Wed, 25 Jan 2023 17:26:33 +0530 Message-ID: Subject: Re: [aarch64] Use wzr/xzr for assigning vector element to 0 To: Prathamesh Kulkarni , gcc Patches , richard.sandiford@arm.com Content-Type: multipart/mixed; boundary="000000000000d14fdb05f3155494" X-Spam-Status: No, score=-9.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_NUMSUBJECT,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --000000000000d14fdb05f3155494 Content-Type: text/plain; charset="UTF-8" On Mon, 23 Jan 2023 at 22:26, Richard Sandiford wrote: > > Prathamesh Kulkarni writes: > > On Wed, 18 Jan 2023 at 19:59, Richard Sandiford > > wrote: > >> > >> Prathamesh Kulkarni writes: > >> > On Tue, 17 Jan 2023 at 18:29, Richard Sandiford > >> > wrote: > >> >> > >> >> Prathamesh Kulkarni writes: > >> >> > Hi Richard, > >> >> > For the following (contrived) test: > >> >> > > >> >> > void foo(int32x4_t v) > >> >> > { > >> >> > v[3] = 0; > >> >> > return v; > >> >> > } > >> >> > > >> >> > -O2 code-gen: > >> >> > foo: > >> >> > fmov s1, wzr > >> >> > ins v0.s[3], v1.s[0] > >> >> > ret > >> >> > > >> >> > I suppose we can instead emit the following code-gen ? > >> >> > foo: > >> >> > ins v0.s[3], wzr > >> >> > ret > >> >> > > >> >> > combine produces: > >> >> > Failed to match this instruction: > >> >> > (set (reg:V4SI 95 [ v ]) > >> >> > (vec_merge:V4SI (const_vector:V4SI [ > >> >> > (const_int 0 [0]) repeated x4 > >> >> > ]) > >> >> > (reg:V4SI 97) > >> >> > (const_int 8 [0x8]))) > >> >> > > >> >> > So, I wrote the following pattern to match the above insn: > >> >> > (define_insn "aarch64_simd_vec_set_zero" > >> >> > [(set (match_operand:VALL_F16 0 "register_operand" "=w") > >> >> > (vec_merge:VALL_F16 > >> >> > (match_operand:VALL_F16 1 "const_dup0_operand" "w") > >> >> > (match_operand:VALL_F16 3 "register_operand" "0") > >> >> > (match_operand:SI 2 "immediate_operand" "i")))] > >> >> > "TARGET_SIMD" > >> >> > { > >> >> > int elt = ENDIAN_LANE_N (, exact_log2 (INTVAL (operands[2]))); > >> >> > operands[2] = GEN_INT ((HOST_WIDE_INT) 1 << elt); > >> >> > return "ins\\t%0.[%p2], wzr"; > >> >> > } > >> >> > ) > >> >> > > >> >> > which now matches the above insn produced by combine. > >> >> > However, in reload dump, it creates a new insn for assigning > >> >> > register to (const_vector (const_int 0)), > >> >> > which results in: > >> >> > (insn 19 8 13 2 (set (reg:V4SI 33 v1 [99]) > >> >> > (const_vector:V4SI [ > >> >> > (const_int 0 [0]) repeated x4 > >> >> > ])) "wzr-test.c":8:1 1269 {*aarch64_simd_movv4si} > >> >> > (nil)) > >> >> > (insn 13 19 14 2 (set (reg/i:V4SI 32 v0) > >> >> > (vec_merge:V4SI (reg:V4SI 33 v1 [99]) > >> >> > (reg:V4SI 32 v0 [97]) > >> >> > (const_int 8 [0x8]))) "wzr-test.c":8:1 1808 > >> >> > {aarch64_simd_vec_set_zerov4si} > >> >> > (nil)) > >> >> > > >> >> > and eventually the code-gen: > >> >> > foo: > >> >> > movi v1.4s, 0 > >> >> > ins v0.s[3], wzr > >> >> > ret > >> >> > > >> >> > To get rid of redundant assignment of 0 to v1, I tried to split the > >> >> > above pattern > >> >> > as in the attached patch. This works to emit code-gen: > >> >> > foo: > >> >> > ins v0.s[3], wzr > >> >> > ret > >> >> > > >> >> > However, I am not sure if this is the right approach. Could you suggest, > >> >> > if it'd be possible to get rid of UNSPEC_SETZERO in the patch ? > >> >> > >> >> The problem is with the "w" constraint on operand 1, which tells LRA > >> >> to force the zero into an FPR. It should work if you remove the > >> >> constraint. > >> > Ah indeed, sorry about that, changing the constrained works. > >> > >> "i" isn't right though, because that's for scalar integers. > >> There's no need for any constraint here -- the predicate does > >> all of the work. > >> > >> > Does the attached patch look OK after bootstrap+test ? > >> > Since we're in stage-4, shall it be OK to commit now, or queue it for stage-1 ? > >> > >> It needs tests as well. :-) > >> > >> Also: > >> > >> > Thanks, > >> > Prathamesh > >> > > >> > > >> >> > >> >> Also, I think you'll need to use zr for the zero, so that > >> >> it uses xzr for 64-bit elements. > >> >> > >> >> I think this and the existing patterns ought to test > >> >> exact_log2 (INTVAL (operands[2])) >= 0 in the insn condition, > >> >> since there's no guarantee that RTL optimisations won't form > >> >> vec_merges that have other masks. > >> >> > >> >> Thanks, > >> >> Richard > >> > > >> > [aarch64] Use wzr/xzr for assigning 0 to vector element. > >> > > >> > gcc/ChangeLog: > >> > * config/aaarch64/aarch64-simd.md (aarch64_simd_vec_set_zero): > >> > New pattern. > >> > * config/aarch64/predicates.md (const_dup0_operand): New. > >> > > >> > diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md > >> > index 104088f67d2..8e54ee4e886 100644 > >> > --- a/gcc/config/aarch64/aarch64-simd.md > >> > +++ b/gcc/config/aarch64/aarch64-simd.md > >> > @@ -1083,6 +1083,20 @@ > >> > [(set_attr "type" "neon_ins, neon_from_gp, neon_load1_one_lane")] > >> > ) > >> > > >> > +(define_insn "aarch64_simd_vec_set_zero" > >> > + [(set (match_operand:VALL_F16 0 "register_operand" "=w") > >> > + (vec_merge:VALL_F16 > >> > + (match_operand:VALL_F16 1 "const_dup0_operand" "i") > >> > + (match_operand:VALL_F16 3 "register_operand" "0") > >> > + (match_operand:SI 2 "immediate_operand" "i")))] > >> > + "TARGET_SIMD && exact_log2 (INTVAL (operands[2])) >= 0" > >> > + { > >> > + int elt = ENDIAN_LANE_N (, exact_log2 (INTVAL (operands[2]))); > >> > + operands[2] = GEN_INT ((HOST_WIDE_INT) 1 << elt); > >> > + return "ins\\t%0.[%p2], zr"; > >> > + } > >> > +) > >> > + > >> > (define_insn "@aarch64_simd_vec_copy_lane" > >> > [(set (match_operand:VALL_F16 0 "register_operand" "=w") > >> > (vec_merge:VALL_F16 > >> > diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md > >> > index ff7f73d3f30..901fa1bd7f9 100644 > >> > --- a/gcc/config/aarch64/predicates.md > >> > +++ b/gcc/config/aarch64/predicates.md > >> > @@ -49,6 +49,13 @@ > >> > return CONST_INT_P (op) && IN_RANGE (INTVAL (op), 1, 3); > >> > }) > >> > > >> > +(define_predicate "const_dup0_operand" > >> > + (match_code "const_vector") > >> > +{ > >> > + op = unwrap_const_vec_duplicate (op); > >> > + return CONST_INT_P (op) && rtx_equal_p (op, const0_rtx); > >> > +}) > >> > + > >> > >> We already have aarch64_simd_imm_zero for this. aarch64_simd_imm_zero > >> is actually more general, because it works for floating-point modes too. > >> > >> I think the tests should cover all modes included in VALL_F16, since > >> that should have picked up this and the xzr thing. > > Hi Richard, > > Thanks for the suggestions. Does the attached patch look OK ? > > I am not sure how to test for v4bf and v8bf since it seems the compiler > > refuses conversions to/from bfloat16_t ? > > > > Thanks, > > Prathamesh > > > >> > >> Thanks, > >> Richard > >> > >> > (define_predicate "subreg_lowpart_operator" > >> > (ior (match_code "truncate") > >> > (and (match_code "subreg") > > > > [aarch64] Use wzr/xzr for assigning 0 to vector element. > > > > gcc/ChangeLog: > > * config/aaarch64/aarch64-simd.md (aarch64_simd_vec_set_zero): > > New pattern. > > > > gcc/testsuite/ChangeLog: > > * gcc.target/aarch64/vec-set-zero.c: New test. > > > > diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md > > index 7f212bf37cd..7428e74beaf 100644 > > --- a/gcc/config/aarch64/aarch64-simd.md > > +++ b/gcc/config/aarch64/aarch64-simd.md > > @@ -1083,6 +1083,20 @@ > > [(set_attr "type" "neon_ins, neon_from_gp, neon_load1_one_lane")] > > ) > > > > +(define_insn "aarch64_simd_vec_set_zero" > > + [(set (match_operand:VALL_F16 0 "register_operand" "=w") > > + (vec_merge:VALL_F16 > > + (match_operand:VALL_F16 1 "aarch64_simd_imm_zero" "") > > + (match_operand:VALL_F16 3 "register_operand" "0") > > + (match_operand:SI 2 "immediate_operand" "i")))] > > + "TARGET_SIMD && exact_log2 (INTVAL (operands[2])) >= 0" > > + { > > + int elt = ENDIAN_LANE_N (, exact_log2 (INTVAL (operands[2]))); > > + operands[2] = GEN_INT ((HOST_WIDE_INT) 1 << elt); > > + return "ins\\t%0.[%p2], zr"; > > + } > > +) > > + > > (define_insn "@aarch64_simd_vec_copy_lane" > > [(set (match_operand:VALL_F16 0 "register_operand" "=w") > > (vec_merge:VALL_F16 > > diff --git a/gcc/testsuite/gcc.target/aarch64/vec-set-zero.c b/gcc/testsuite/gcc.target/aarch64/vec-set-zero.c > > new file mode 100644 > > index 00000000000..c260cc9e445 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/aarch64/vec-set-zero.c > > @@ -0,0 +1,32 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-O2" } */ > > + > > +#include "arm_neon.h" > > + > > +#define FOO(type) \ > > +type f_##type(type v) \ > > +{ \ > > + v[1] = 0; \ > > + return v; \ > > +} > > + > > +FOO(int8x8_t) > > +FOO(int16x4_t) > > +FOO(int32x2_t) > > + > > +FOO(int8x16_t) > > +FOO(int16x8_t) > > +FOO(int32x4_t) > > +FOO(int64x2_t) > > + > > +FOO(float16x4_t) > > +FOO(float32x2_t) > > + > > +FOO(float16x8_t) > > +FOO(float32x4_t) > > +FOO(float64x2_t) > > + > > +/* { dg-final { scan-assembler-times "ins\\tv\[0-9\]+\.b\\\[\[1\]\\\], wzr" 2 } } */ > > +/* { dg-final { scan-assembler-times "ins\\tv\[0-9\]+\.h\\\[\[1\]\\\], wzr" 4 } } */ > > +/* { dg-final { scan-assembler-times "ins\\tv\[0-9\]+\.s\\\[\[1\]\\\], wzr" 4 } } */ > > +/* { dg-final { scan-assembler-times "ins\\tv\[0-9\]+\.d\\\[\[1\]\\\], xzr" 2 } } */ > > Can you test big-endian too? I'd expect it to use different INS indices. Ah indeed, thanks for pointing out. > > It might be worth quoting the regexps with {...} rather than "...", > to reduce the number of backslashes needed. Does the attached patch look OK ? Thanks, Prathamesh > > Thanks, > Richard --000000000000d14fdb05f3155494 Content-Type: text/plain; charset="US-ASCII"; name="gnu-811-7.txt" Content-Disposition: attachment; filename="gnu-811-7.txt" Content-Transfer-Encoding: base64 Content-ID: X-Attachment-Id: f_ldblzg190 W2FhcmNoNjRdIFVzZSB3enIveHpyIGZvciBhc3NpZ25pbmcgMCB0byB2ZWN0b3IgZWxlbWVudC4K CmdjYy9DaGFuZ2VMb2c6CgkqIGNvbmZpZy9hYWFyY2g2NC9hYXJjaDY0LXNpbWQubWQgKGFhcmNo NjRfc2ltZF92ZWNfc2V0X3plcm88bW9kZT4pOgoJTmV3IHBhdHRlcm4uCgpnY2MvdGVzdHN1aXRl L0NoYW5nZUxvZzoKCSogZ2NjLnRhcmdldC9hYXJjaDY0L3ZlYy1zZXQtemVyby5jOiBOZXcgdGVz dC4KCmRpZmYgLS1naXQgYS9nY2MvY29uZmlnL2FhcmNoNjQvYWFyY2g2NC1zaW1kLm1kIGIvZ2Nj L2NvbmZpZy9hYXJjaDY0L2FhcmNoNjQtc2ltZC5tZAppbmRleCA3ZjIxMmJmMzdjZC4uNzQyOGU3 NGJlYWYgMTAwNjQ0Ci0tLSBhL2djYy9jb25maWcvYWFyY2g2NC9hYXJjaDY0LXNpbWQubWQKKysr IGIvZ2NjL2NvbmZpZy9hYXJjaDY0L2FhcmNoNjQtc2ltZC5tZApAQCAtMTA4Myw2ICsxMDgzLDIw IEBACiAgIFsoc2V0X2F0dHIgInR5cGUiICJuZW9uX2luczxxPiwgbmVvbl9mcm9tX2dwPHE+LCBu ZW9uX2xvYWQxX29uZV9sYW5lPHE+IildCiApCiAKKyhkZWZpbmVfaW5zbiAiYWFyY2g2NF9zaW1k X3ZlY19zZXRfemVybzxtb2RlPiIKKyAgWyhzZXQgKG1hdGNoX29wZXJhbmQ6VkFMTF9GMTYgMCAi cmVnaXN0ZXJfb3BlcmFuZCIgIj13IikKKwkodmVjX21lcmdlOlZBTExfRjE2CisJICAgIChtYXRj aF9vcGVyYW5kOlZBTExfRjE2IDEgImFhcmNoNjRfc2ltZF9pbW1femVybyIgIiIpCisJICAgICht YXRjaF9vcGVyYW5kOlZBTExfRjE2IDMgInJlZ2lzdGVyX29wZXJhbmQiICIwIikKKwkgICAgKG1h dGNoX29wZXJhbmQ6U0kgMiAiaW1tZWRpYXRlX29wZXJhbmQiICJpIikpKV0KKyAgIlRBUkdFVF9T SU1EICYmIGV4YWN0X2xvZzIgKElOVFZBTCAob3BlcmFuZHNbMl0pKSA+PSAwIgorICB7CisgICAg aW50IGVsdCA9IEVORElBTl9MQU5FX04gKDxudW5pdHM+LCBleGFjdF9sb2cyIChJTlRWQUwgKG9w ZXJhbmRzWzJdKSkpOworICAgIG9wZXJhbmRzWzJdID0gR0VOX0lOVCAoKEhPU1RfV0lERV9JTlQp IDEgPDwgZWx0KTsKKyAgICByZXR1cm4gImluc1xcdCUwLjxWZXR5cGU+WyVwMl0sIDx2d2NvcmU+ enIiOworICB9CispCisKIChkZWZpbmVfaW5zbiAiQGFhcmNoNjRfc2ltZF92ZWNfY29weV9sYW5l PG1vZGU+IgogICBbKHNldCAobWF0Y2hfb3BlcmFuZDpWQUxMX0YxNiAwICJyZWdpc3Rlcl9vcGVy YW5kIiAiPXciKQogCSh2ZWNfbWVyZ2U6VkFMTF9GMTYKZGlmZiAtLWdpdCBhL2djYy90ZXN0c3Vp dGUvZ2NjLnRhcmdldC9hYXJjaDY0L3ZlYy1zZXQtemVyby5jIGIvZ2NjL3Rlc3RzdWl0ZS9nY2Mu dGFyZ2V0L2FhcmNoNjQvdmVjLXNldC16ZXJvLmMKbmV3IGZpbGUgbW9kZSAxMDA2NDQKaW5kZXgg MDAwMDAwMDAwMDAuLmIzNGI5MDJjZjI3Ci0tLSAvZGV2L251bGwKKysrIGIvZ2NjL3Rlc3RzdWl0 ZS9nY2MudGFyZ2V0L2FhcmNoNjQvdmVjLXNldC16ZXJvLmMKQEAgLTAsMCArMSw0MCBAQAorLyog eyBkZy1kbyBjb21waWxlIH0gKi8KKy8qIHsgZGctb3B0aW9ucyAiLU8yIiB9ICovCisKKyNpbmNs dWRlICJhcm1fbmVvbi5oIgorCisjZGVmaW5lIEZPTyh0eXBlKSBcCit0eXBlIGZfIyN0eXBlKHR5 cGUgdikgXAoreyBcCisgIHZbMV0gPSAwOyBcCisgIHJldHVybiB2OyBcCit9CisKK0ZPTyhpbnQ4 eDhfdCkKK0ZPTyhpbnQxNng0X3QpCitGT08oaW50MzJ4Ml90KQorCitGT08oaW50OHgxNl90KQor Rk9PKGludDE2eDhfdCkKK0ZPTyhpbnQzMng0X3QpCitGT08oaW50NjR4Ml90KQorCitGT08oZmxv YXQxNng0X3QpCitGT08oZmxvYXQzMngyX3QpCisKK0ZPTyhmbG9hdDE2eDhfdCkKK0ZPTyhmbG9h dDMyeDRfdCkKK0ZPTyhmbG9hdDY0eDJfdCkKKworLyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1i bGVyLXRpbWVzIHtpbnNcdHZbMC05XStcLmJcWzFcXSwgd3pyfSAyIHsgdGFyZ2V0IGFhcmNoNjRf bGl0dGxlX2VuZGlhbiB9IH0gfSAqLworLyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyLXRp bWVzIHtpbnNcdHZbMC05XStcLmhcWzFcXSwgd3pyfSA0IHsgdGFyZ2V0IGFhcmNoNjRfbGl0dGxl X2VuZGlhbiB9IH0gfSAqLworLyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyLXRpbWVzIHtp bnNcdHZbMC05XStcLnNcWzFcXSwgd3pyfSA0IHsgdGFyZ2V0IGFhcmNoNjRfbGl0dGxlX2VuZGlh biB9IH0gfSAqLworLyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyLXRpbWVzIHtpbnNcdHZb MC05XStcLmRcWzFcXSwgeHpyfSAyIHsgdGFyZ2V0IGFhcmNoNjRfbGl0dGxlX2VuZGlhbiB9IH0g fSAqLworCisvKiB7IGRnLWZpbmFsIHsgc2Nhbi1hc3NlbWJsZXItdGltZXMge2luc1x0dlswLTld K1wuYlxbNlxdLCB3enJ9IDEgeyB0YXJnZXQgYWFyY2g2NF9iaWdfZW5kaWFuIH0gfSB9ICovCisv KiB7IGRnLWZpbmFsIHsgc2Nhbi1hc3NlbWJsZXItdGltZXMge2luc1x0dlswLTldK1wuYlxbMTRc XSwgd3pyfSAxIHsgdGFyZ2V0IGFhcmNoNjRfYmlnX2VuZGlhbiB9IH0gfSAqLworLyogeyBkZy1m aW5hbCB7IHNjYW4tYXNzZW1ibGVyLXRpbWVzIHtpbnNcdHZbMC05XStcLmhcWzJcXSwgd3pyfSAy IHsgdGFyZ2V0IGFhcmNoNjRfYmlnX2VuZGlhbiB9IH0gfSAqLworLyogeyBkZy1maW5hbCB7IHNj YW4tYXNzZW1ibGVyLXRpbWVzIHtpbnNcdHZbMC05XStcLmhcWzZcXSwgd3pyfSAyIHsgdGFyZ2V0 IGFhcmNoNjRfYmlnX2VuZGlhbiB9IH0gfSAqLworLyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1i bGVyLXRpbWVzIHtpbnNcdHZbMC05XStcLnNcWzBcXSwgd3pyfSAyIHsgdGFyZ2V0IGFhcmNoNjRf YmlnX2VuZGlhbiB9IH0gfSAqLworLyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyLXRpbWVz IHtpbnNcdHZbMC05XStcLnNcWzJcXSwgd3pyfSAyIHsgdGFyZ2V0IGFhcmNoNjRfYmlnX2VuZGlh biB9IH0gfSAqLworLyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyLXRpbWVzIHtpbnNcdHZb MC05XStcLmRcWzBcXSwgeHpyfSAyIHsgdGFyZ2V0IGFhcmNoNjRfYmlnX2VuZGlhbiB9IH0gfSAq Lwo= --000000000000d14fdb05f3155494--