From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by sourceware.org (Postfix) with ESMTPS id 97CB03858D32 for ; Sat, 14 Jan 2023 17:59:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 97CB03858D32 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-wm1-x331.google.com with SMTP id bi26-20020a05600c3d9a00b003d3404a89faso2078556wmb.1 for ; Sat, 14 Jan 2023 09:59:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=to:subject:message-id:date:from:in-reply-to:references:mime-version :from:to:cc:subject:date:message-id:reply-to; bh=/KYAHHKf6KKilHggcOswEIVG3UkQWiWJOO/tyuc9r4I=; b=gMVUOmkZ6abAiH9X9fJlq3I6BnVYuU369OtHexqp/b+nqo2kh9KMoxd/aNq2FpgQuW 5m7Ee0tDK+OoTPvCbaEik4xGd4jh/0MN9yKIMSUHdqfqif+0Se19dlFcrYQyb9CEN82L ZUZCMjAWnyNTGlcylrhc8ST2Y5d6ItDYIZoavLc2Yne6rsFa7vM77sEzOfpgZVyNU5hW YtDHf/anmuYldwi/v1yJukeujSjyORSxE7OlIgIj+eRkWGG1Weo1Gfn8MriwosukQBNb Upq7fvxjCqGjpDT9m+3DtX354US6ivE+quETs7/XcHFYmRbJLbEKmBL0/wMqaSF3vBes /zjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=to:subject:message-id:date:from:in-reply-to:references:mime-version :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=/KYAHHKf6KKilHggcOswEIVG3UkQWiWJOO/tyuc9r4I=; b=pGNfuwHJnObdij7Ovqs7QWEWMPWDXaYSAlR3z0wOFPvU3HdfVitGqBeavDpi27GdUe sQC5fKJ+bcOJBDmNQgnwNNxiiJt3zIiioOIJcqybNFOCKSGW4YcgyLMkMCBGY16bL38I C5FCFunNCCbr9ZmoR5RO+VE3FO4SPSrC5+t2XGd64Da407QSAmMLj5aoDmmr6t4jUFu+ 043gNijEJ4R+PF/RRhgk469r9tQEbt9k5OTU3WCEsyvOzvAk2E67KYXFZhibQP2rMau6 2WvxNWq5jmZzp9E3wj+usHtcXX8J9Pda5cGXhrnlfiqPOYm6nCvJ488U6kG+QsZT1jJN +K7A== X-Gm-Message-State: AFqh2koR9D9vz4XdS5m23qZQrdGnqvPu5Ab9PddlnBc5fxaanRpmxzQD X73iRb1X/G/GslZ1zsJCILoSxHWVqad9CHNkLd0BVA== X-Google-Smtp-Source: AMrXdXv23Rt89LPoNJKetb9t9bvhWpeQtawegy72RwqGL49BoexvbWH0PTOoOAyAoBbwYP7NSeWp9nFBg+5FWoOvFz8= X-Received: by 2002:a05:600c:4194:b0:3d2:3cb4:946e with SMTP id p20-20020a05600c419400b003d23cb4946emr5010067wmh.36.1673719184334; Sat, 14 Jan 2023 09:59:44 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Prathamesh Kulkarni Date: Sat, 14 Jan 2023 23:29:07 +0530 Message-ID: Subject: Re: Missed lowering to ld1rq from svld1rq for memory operand To: Prathamesh Kulkarni , gcc Patches , richard.sandiford@arm.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, 12 Jan 2023 at 21:02, Richard Sandiford wrote: > > Prathamesh Kulkarni writes: > > On Fri, 5 Aug 2022 at 17:49, Richard Sandiford > > wrote: > >> > >> Prathamesh Kulkarni writes: > >> > Hi Richard, > >> > Following from off-list discussion, in the attached patch, I wrote pattern > >> > similar to vec_duplicate_reg, which seems to work for the svld1rq tests. > >> > Does it look OK ? > >> > > >> > Sorry, I didn't fully understand your suggestion on integrating with > >> > vec_duplicate_reg > >> > pattern. For vec_duplicate_reg, the operand to vec_duplicate expects > >> > mode to be , while the pattern in patch expects operand of > >> > vec_duplicate to have mode . > >> > How do we write a pattern so an operand can accept either of the 2 modes ? > >> > >> I quoted the wrong one, sorry, should have been > >> aarch64_vec_duplicate_vq_le. > >> > >> > Also it seems cannot be used with SVE_ALL ? > >> > >> Yeah, these would be SVE_FULL only. > > Hi Richard, > > Sorry for the very late reply. I have attached patch, to integrate > > with vec_duplicate_vq_le. > > Bootstrapped+tested on aarch64-linux-gnu. > > OK to commit ? > > > > Thanks, > > Prathamesh > >> > >> Richard > >> > > > > gcc/ > > * config/aarch64/aarch64-sve.md (aarch64_vec_duplicate_vq_le): > > Change to define_insn_and_split to fold ldr+dup to ld1rq. > > * config/aarch64/predicates.md (aarch64_sve_dup_ld1rq_operand): New. > > > > testsuite/ > > * gcc.target/aarch64/sve/acle/general/pr96463-2.c: Adjust. > > > > diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md > > index b8cc47ef5fc..4548375b8d6 100644 > > --- a/gcc/config/aarch64/aarch64-sve.md > > +++ b/gcc/config/aarch64/aarch64-sve.md > > @@ -2533,14 +2533,34 @@ > > ) > > > > ;; Duplicate an Advanced SIMD vector to fill an SVE vector (LE version). > > -(define_insn "@aarch64_vec_duplicate_vq_le" > > - [(set (match_operand:SVE_FULL 0 "register_operand" "=w") > > + > > +(define_insn_and_split "@aarch64_vec_duplicate_vq_le" > > + [(set (match_operand:SVE_FULL 0 "register_operand" "=w, w") > > (vec_duplicate:SVE_FULL > > - (match_operand: 1 "register_operand" "w")))] > > + (match_operand: 1 "aarch64_sve_dup_ld1rq_operand" "w, UtQ"))) > > + (clobber (match_scratch:VNx16BI 2 "=X, Upl"))] > > "TARGET_SVE && !BYTES_BIG_ENDIAN" > > { > > - operands[1] = gen_rtx_REG (mode, REGNO (operands[1])); > > - return "dup\t%0.q, %1.q[0]"; > > + switch (which_alternative) > > + { > > + case 0: > > + operands[1] = gen_rtx_REG (mode, REGNO (operands[1])); > > + return "dup\t%0.q, %1.q[0]"; > > + case 1: > > + return "#"; > > + default: > > + gcc_unreachable (); > > + } > > + } > > + "&& MEM_P (operands[1])" > > + [(const_int 0)] > > + { > > + if (GET_CODE (operands[2]) == SCRATCH) > > + operands[2] = gen_reg_rtx (VNx16BImode); > > + emit_move_insn (operands[2], CONSTM1_RTX (VNx16BImode)); > > + rtx gp = gen_lowpart (mode, operands[2]); > > + emit_insn (gen_aarch64_sve_ld1rq (operands[0], operands[1], gp)); > > + DONE; > > } > > ) > > > > diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md > > index ff7f73d3f30..6062f37025e 100644 > > --- a/gcc/config/aarch64/predicates.md > > +++ b/gcc/config/aarch64/predicates.md > > @@ -676,6 +676,10 @@ > > (ior (match_operand 0 "register_operand") > > (match_operand 0 "aarch64_sve_ld1r_operand"))) > > > > +(define_predicate "aarch64_sve_dup_ld1rq_operand" > > + (ior (match_operand 0 "register_operand") > > + (match_operand 0 "aarch64_sve_ld1rq_operand"))) > > + > > (define_predicate "aarch64_sve_ptrue_svpattern_immediate" > > (and (match_code "const") > > (match_test "aarch64_sve_ptrue_svpattern_p (op, NULL)"))) > > diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr96463-2.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr96463-2.c > > index 196de3f5e0a..c38204e6874 100644 > > --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr96463-2.c > > +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr96463-2.c > > @@ -26,4 +26,4 @@ TEST(svfloat64_t, float64_t, f64) > > > > TEST(svbfloat16_t, bfloat16_t, bf16) > > > > -/* { dg-final { scan-assembler-times {\tdup\tz[0-9]+\.q, z[0-9]+\.q\[0\]} 12 { target aarch64_little_endian } } } */ > > +/* { dg-final { scan-assembler-not {\tdup\t} } } */ > > It would be good to add something like: > > /* { dg-final { scan-assembler-times {\tld1rq\t} 12 } } */ > > (I assume it'll pass for both endiannesses, but please check!), > in addition to the scan-assembler-not. > > OK with that change, thanks. Thanks, committed the patch in a3b99b84609af310c72b4d6221621f5b63a3c169 after adjusting the test-case, and verifying that we generate ld1rq for big endian targets, and bootstrap+test on aarch64-linux-gnu. Thanks, Prathamesh > > Richard