From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by sourceware.org (Postfix) with ESMTPS id CDC7D385558F for ; Mon, 21 Aug 2023 19:56:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CDC7D385558F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-31c479ede21so1296943f8f.2 for ; Mon, 21 Aug 2023 12:56:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1692647788; x=1693252588; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=5AsEuVC9hJ7oN/MkrDrAjNYEPxXBVdkPe3t5TW77+pY=; b=YnEZNgvkrYmYlUGUIDUqAG4eU+BXoWHB1SwfRxT/WiRCEdTbxMMMmABgF43xHLg/gY RAUt+kz2tEC/2e1hqt7B0s6o/4EEn42kcAZ0sZGHUaPV3hZgQpSbI8y7c1PetD99/Dxw EOwnzoeqpjx1dcVLVHgM/nRhHiZbg9e0GcUTtuMrmtCClcJejj1CrFRIsCPw82X4tkL1 C117i1ecWfz7SeqXvpykNYkF92GZwdneZK/M7vpJpA6qktDjF3RQn0LfqyMxSj7e2hkQ NgzDKRUtm35wAOxoDbVppS/8qcp161Syjl54z+VhxyoxS2GBTcyVdfO8QBxO6FWvvCgS 8ILg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692647788; x=1693252588; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=5AsEuVC9hJ7oN/MkrDrAjNYEPxXBVdkPe3t5TW77+pY=; b=g7Vn8wlRnbLLCJQleKRWcGWheZ1NZqDRd8K1zbvOdZvyPm4FWifAjK3IpmovCmmlI/ ODikQg+A0l8JLGdTZarzjaknQUjJIXLELFcKMtkws3c9j730PtlMf0NEO8uJ/YPM3/S9 gcy4Z7pKqDCNRC9FEJwdFC0cQHn8MCWdW+bffXkhETJxlw4QVp5OXUUEk+GDWw6kv4EB NmhAjqwcpZKlZBEgH0yOey9CIylYgg4xSwQE5tTo7UEPW9V6vDbKh88ZWIwT0rZnVr5X 5LHGqZnMqJo4Bd385c9614NIHjD8wapEqbDSNkO9nIG2NltbBKKlEf8vBeORSulMFzyO gvpg== X-Gm-Message-State: AOJu0YzgaVmkEzWitrVtEIKXs/CDy8h+D60p66zYkJPgDQY82nT7fq26 FYjmtZP8dM8ZKoWWCPmCx9zGI0WkZAun5Q7j1gDBpA== X-Google-Smtp-Source: AGHT+IHYqK+qgS4ZvhsRbVCAKKzcpeuL3EU7cu4HiyBlUWtF65TY8z0VCUb3hAZ0bKuiS598tQLkbxDuF6t7ftHtixk= X-Received: by 2002:a5d:684b:0:b0:317:6310:a616 with SMTP id o11-20020a5d684b000000b003176310a616mr5264790wrw.36.1692647788486; Mon, 21 Aug 2023 12:56:28 -0700 (PDT) MIME-Version: 1.0 References: <20230816084038.2725233-1-yanzhang.wang@intel.com> In-Reply-To: <20230816084038.2725233-1-yanzhang.wang@intel.com> From: Prathamesh Kulkarni Date: Tue, 22 Aug 2023 01:25:51 +0530 Message-ID: Subject: Re: [PATCH] RISC-V: Support simplify (-1-x) for vector. To: yanzhang.wang@intel.com Cc: gcc-patches@gcc.gnu.org, Richard Sandiford Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, 16 Aug 2023 at 14:12, yanzhang.wang--- via Gcc-patches wrote: > > From: Yanzhang Wang > > The pattern is enabled for scalar but not for vector. The patch try to > make it consistent and will convert below code, (CCing Richard S.) Hi, Sorry if this comment is not relevant to the patch but I was wondering if it should also fold -1 - x --> ~x for the following test or is the test written incorrectly ? svint32_t f(svint32_t x) { return svsub_s32_x (svptrue_b8 (), svdup_s32 (-1), x); } expand dump shows: (insn 2 4 3 2 (set (reg/v:VNx4SI 93 [ x ]) (reg:VNx4SI 32 v0 [ x ])) "foo.c":9:1 -1 (nil)) (note 3 2 6 2 NOTE_INSN_FUNCTION_BEG) (insn 6 3 7 2 (set (reg:VNx4SI 94) (const_vector:VNx4SI repeat [ (const_int -1 [0xffffffffffffffff]) ])) "foo.c":10:10 -1 (nil)) (insn 7 6 11 2 (set (reg:VNx4SI 92 [ ]) (minus:VNx4SI (reg:VNx4SI 94) (reg/v:VNx4SI 93 [ x ]))) "foo.c":10:10 -1 (nil)) (insn 11 7 12 2 (set (reg/i:VNx4SI 32 v0) (reg:VNx4SI 92 [ ])) "foo.c":11:1 -1 (nil)) (insn 12 11 0 2 (use (reg/i:VNx4SI 32 v0)) "foo.c":11:1 -1 (nil)) and results in following code-gen: f: mov z31.b, #-1 sub z0.s, z31.s, z0.s ret Altho I suppose at TREE level the above call to svsub_s32_x could be folded by implementing the same transform (-1 - x -> ~x) in svsub_impl::fold ? Thanks, Prathamesh > > shortcut_for_riscv_vrsub_case_1_32: > vl1re32.v v1,0(a1) > vsetvli zero,a2,e32,m1,ta,ma > vrsub.vi v1,v1,-1 > vs1r.v v1,0(a0) > ret > > to, > > shortcut_for_riscv_vrsub_case_1_32: > vl1re32.v v1,0(a1) > vsetvli zero,a2,e32,m1,ta,ma > vnot.v v1,v1 > vs1r.v v1,0(a0) > ret > > gcc/ChangeLog: > > * simplify-rtx.cc (simplify_context::simplify_binary_operation_1): > Get -1 with mode. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/base/simplify-vrsub.c: New test. > > Signed-off-by: Yanzhang Wang > --- > gcc/simplify-rtx.cc | 2 +- > .../gcc.target/riscv/rvv/base/simplify-vrsub.c | 18 ++++++++++++++++++ > 2 files changed, 19 insertions(+), 1 deletion(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vrsub.c > > diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc > index d7315d82aa3..eb1ac120832 100644 > --- a/gcc/simplify-rtx.cc > +++ b/gcc/simplify-rtx.cc > @@ -3071,7 +3071,7 @@ simplify_context::simplify_binary_operation_1 (rtx_code code, > /* (-1 - a) is ~a, unless the expression contains symbolic > constants, in which case not retaining additions and > subtractions could cause invalid assembly to be produced. */ > - if (trueop0 == constm1_rtx > + if (trueop0 == CONSTM1_RTX (mode) > && !contains_symbolic_reference_p (op1)) > return simplify_gen_unary (NOT, mode, op1, mode); > > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vrsub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vrsub.c > new file mode 100644 > index 00000000000..df87ed94ea4 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vrsub.c > @@ -0,0 +1,18 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ > + > +#include "riscv_vector.h" > + > +#define VRSUB_WITH_LMUL(LMUL, DTYPE) \ > + vint##DTYPE##m##LMUL##_t \ > + shortcut_for_riscv_vrsub_case_##LMUL##_##DTYPE \ > + (vint##DTYPE##m##LMUL##_t v1, \ > + size_t vl) \ > + { \ > + return __riscv_vrsub_vx_i##DTYPE##m##LMUL (v1, -1, vl); \ > + } > + > +VRSUB_WITH_LMUL (1, 16) > +VRSUB_WITH_LMUL (1, 32) > + > +/* { dg-final { scan-assembler-times {vnot\.v} 2 } } */ > -- > 2.41.0 >