From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by sourceware.org (Postfix) with ESMTPS id 181AB3858D33 for ; Thu, 4 May 2023 11:48:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 181AB3858D33 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-3062678861fso242410f8f.0 for ; Thu, 04 May 2023 04:48:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683200889; x=1685792889; h=to:subject:message-id:date:from:in-reply-to:references:mime-version :from:to:cc:subject:date:message-id:reply-to; bh=HUG2q406aSiyCDU/Ebe+FgaQiMu1B/PSIivWYScNAwA=; b=Dz5CWzfarUsXqI8I7okWz70sipGZPqPKOwYs2vjOvc+rfKHCquvifN7JmhHzjyh6jy DyHE+Cz2j5/AeBZeD+8jIOQT4KzYYrPL3gxb0bqTB9lJMGjNcXChBk1MJqGs5KieoUbK E9Of0LDO0Zg+yTwvja1gYz8cVwCrJzcWDHIbarTTJ7zlLT2in5uNlQzwp7wGOX1a9QlB uJSPsJFmiI+mM93A+oal5t3uQbnvjN07HK12cwbM/Hm5bGDZZNvsvNDLVh5XlaPDLGOD a2ERNeOfYIaBQcwdVazEVkKQrkK7uF//6FQX/MJ5ulQyPkzlBdpVwbOVj9opeVyoX5wB vT8w== X-Google-DKIM-Signature: v=1; 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boundary="0000000000000cfb8a05fadcbf9e" X-Spam-Status: No, score=-9.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --0000000000000cfb8a05fadcbf9e Content-Type: text/plain; charset="UTF-8" On Mon, 24 Apr 2023 at 15:00, Richard Sandiford wrote: > > Prathamesh Kulkarni writes: > > [aarch64] Recursively intialize even and odd sub-parts and merge with zip1. > > > > gcc/ChangeLog: > > * config/aarch64/aarch64.cc (aarch64_expand_vector_init_fallback): Rename > > aarch64_expand_vector_init to this, and remove interleaving case. > > Recursively call aarch64_expand_vector_init_fallback, instead of > > aarch64_expand_vector_init. > > (aarch64_unzip_vector_init): New function. > > (aarch64_expand_vector_init): Likewise. > > > > gcc/testsuite/ChangeLog: > > * gcc.target/aarch64/ldp_stp_16.c (cons2_8_float): Adjust for new > > code-gen. > > * gcc.target/aarch64/sve/acle/general/dupq_5.c: Likewise. > > * gcc.target/aarch64/sve/acle/general/dupq_6.c: Likewise. > > * gcc.target/aarch64/vec-init-18.c: Rename interleave-init-1.c to > > this. > > * gcc.target/aarch64/vec-init-19.c: New test. > > * gcc.target/aarch64/vec-init-20.c: Likewise. > > * gcc.target/aarch64/vec-init-21.c: Likewise. > > * gcc.target/aarch64/vec-init-22-size.c: Likewise. > > * gcc.target/aarch64/vec-init-22-speed.c: Likewise. > > * gcc.target/aarch64/vec-init-22.h: New header. > > > > diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc > > index d7e895f8d34..416e062829c 100644 > > --- a/gcc/config/aarch64/aarch64.cc > > +++ b/gcc/config/aarch64/aarch64.cc > > @@ -22026,11 +22026,12 @@ aarch64_simd_make_constant (rtx vals) > > return NULL_RTX; > > } > > > > -/* Expand a vector initialisation sequence, such that TARGET is > > - initialised to contain VALS. */ > > +/* A subroutine of aarch64_expand_vector_init, with the same interface. > > + The caller has already tried a divide-and-conquer approach, so do > > + not consider that case here. */ > > > > void > > -aarch64_expand_vector_init (rtx target, rtx vals) > > +aarch64_expand_vector_init_fallback (rtx target, rtx vals) > > { > > machine_mode mode = GET_MODE (target); > > scalar_mode inner_mode = GET_MODE_INNER (mode); > > @@ -22090,38 +22091,6 @@ aarch64_expand_vector_init (rtx target, rtx vals) > > return; > > } > > > > - /* Check for interleaving case. > > - For eg if initializer is (int16x8_t) {x, y, x, y, x, y, x, y}. > > - Generate following code: > > - dup v0.h, x > > - dup v1.h, y > > - zip1 v0.h, v0.h, v1.h > > - for "large enough" initializer. */ > > - > > - if (n_elts >= 8) > > - { > > - int i; > > - for (i = 2; i < n_elts; i++) > > - if (!rtx_equal_p (XVECEXP (vals, 0, i), XVECEXP (vals, 0, i % 2))) > > - break; > > - > > - if (i == n_elts) > > - { > > - machine_mode mode = GET_MODE (target); > > - rtx dest[2]; > > - > > - for (int i = 0; i < 2; i++) > > - { > > - rtx x = expand_vector_broadcast (mode, XVECEXP (vals, 0, i)); > > - dest[i] = force_reg (mode, x); > > - } > > - > > - rtvec v = gen_rtvec (2, dest[0], dest[1]); > > - emit_set_insn (target, gen_rtx_UNSPEC (mode, v, UNSPEC_ZIP1)); > > - return; > > - } > > - } > > - > > enum insn_code icode = optab_handler (vec_set_optab, mode); > > gcc_assert (icode != CODE_FOR_nothing); > > > > @@ -22243,7 +22212,7 @@ aarch64_expand_vector_init (rtx target, rtx vals) > > } > > XVECEXP (copy, 0, i) = subst; > > } > > - aarch64_expand_vector_init (target, copy); > > + aarch64_expand_vector_init_fallback (target, copy); > > } > > > > /* Insert the variable lanes directly. */ > > @@ -22257,6 +22226,81 @@ aarch64_expand_vector_init (rtx target, rtx vals) > > } > > } > > > > +/* Return even or odd half of VALS depending on EVEN_P. */ > > + > > +static rtx > > +aarch64_unzip_vector_init (machine_mode mode, rtx vals, bool even_p) > > +{ > > + int n = XVECLEN (vals, 0); > > + machine_mode new_mode > > + = aarch64_simd_container_mode (GET_MODE_INNER (mode), > > + GET_MODE_BITSIZE (mode).to_constant () / 2); > > + rtvec vec = rtvec_alloc (n / 2); > > + for (int i = 0; i < n/2; i++) > > Formatting nit: n / 2 > > > + RTVEC_ELT (vec, i) = (even_p) ? XVECEXP (vals, 0, 2 * i) > > + : XVECEXP (vals, 0, 2 * i + 1); > > + return gen_rtx_PARALLEL (new_mode, vec); > > +} > > + > > +/* Expand a vector initialisation sequence, such that TARGET is > > initialization > > > + initialized to contain VALS. */ > > + > > +void > > +aarch64_expand_vector_init (rtx target, rtx vals) > > +{ > > + /* Try decomposing the initializer into even and odd halves and > > + then ZIP them together. Use the resulting sequence if it is > > + strictly cheaper than loading VALS directly. > > + > > + Prefer the fallback sequence in the event of a tie, since it > > + will tend to use fewer registers. */ > > + > > + machine_mode mode = GET_MODE (target); > > + int n_elts = XVECLEN (vals, 0); > > + > > + if (n_elts < 4 > > + || maybe_ne (GET_MODE_BITSIZE (mode), 128)) > > + { > > + aarch64_expand_vector_init_fallback (target, vals); > > + return; > > + } > > + > > + start_sequence (); > > + rtx halves[2]; > > + unsigned costs[2]; > > + for (int i = 0; i < 2; i++) > > + { > > + start_sequence (); > > + rtx new_vals > > + = aarch64_unzip_vector_init (mode, vals, (i % 2) == 0); > > Just i == 0 wouold be enough. Also, this fits on one line. > > > + rtx tmp_reg = gen_reg_rtx (GET_MODE (new_vals)); > > + aarch64_expand_vector_init (tmp_reg, new_vals); > > + halves[i] = gen_rtx_SUBREG (mode, tmp_reg, 0); > > + rtx_insn *rec_seq = get_insns (); > > + end_sequence (); > > + costs[i] = seq_cost (rec_seq, !optimize_size); > > + emit_insn (rec_seq); > > + } > > + > > + rtvec v = gen_rtvec (2, halves[0], halves[1]); > > + rtx_insn *zip1_insn > > + = emit_set_insn (target, gen_rtx_UNSPEC (mode, v, UNSPEC_ZIP1)); > > + unsigned seq_total_cost > > + = (!optimize_size) ? std::max (costs[0], costs[1]) : costs[0] + costs[1]; > > + seq_total_cost += insn_cost (zip1_insn, !optimize_size); > > + > > + rtx_insn *seq = get_insns (); > > + end_sequence (); > > + > > + start_sequence (); > > + aarch64_expand_vector_init_fallback (target, vals); > > + rtx_insn *fallback_seq = get_insns (); > > + unsigned fallback_seq_cost = seq_cost (fallback_seq, !optimize_size); > > + end_sequence (); > > + > > + emit_insn (seq_total_cost < fallback_seq_cost ? seq : fallback_seq); > > +} > > + > > /* Emit RTL corresponding to: > > insr TARGET, ELEM. */ > > > > diff --git a/gcc/testsuite/gcc.target/aarch64/ldp_stp_16.c b/gcc/testsuite/gcc.target/aarch64/ldp_stp_16.c > > index 8ab117c4dcd..30c86018773 100644 > > --- a/gcc/testsuite/gcc.target/aarch64/ldp_stp_16.c > > +++ b/gcc/testsuite/gcc.target/aarch64/ldp_stp_16.c > > @@ -96,10 +96,10 @@ CONS2_FN (4, float); > > > > /* > > ** cons2_8_float: > > -** dup v([0-9]+)\.4s, .* > > +** dup v([0-9]+)\.2s, v1.s\[0\] > > ** ... > > -** stp q\1, q\1, \[x0\] > > -** stp q\1, q\1, \[x0, #?32\] > > +** stp q0, q0, \[x0\] > > +** stp q0, q0, \[x0, #?32\] > > Leaving the capture in the first line while hard-coding q0 at the end > doesn't look right. The original was written that way because nothing > guarantees a particular register allocation. > > I think this now needs to match more of the sequence. > > > diff --git a/gcc/testsuite/gcc.target/aarch64/interleave-init-1.c b/gcc/testsuite/gcc.target/aarch64/vec-init-18.c > > similarity index 82% > > rename from gcc/testsuite/gcc.target/aarch64/interleave-init-1.c > > rename to gcc/testsuite/gcc.target/aarch64/vec-init-18.c > > index ee775048589..e812d3946de 100644 > > --- a/gcc/testsuite/gcc.target/aarch64/interleave-init-1.c > > +++ b/gcc/testsuite/gcc.target/aarch64/vec-init-18.c > > @@ -7,8 +7,8 @@ > > /* > > ** foo: > > ** ... > > -** dup v[0-9]+\.8h, w[0-9]+ > > -** dup v[0-9]+\.8h, w[0-9]+ > > +** dup v[0-9]+\.4h, w[0-9]+ > > +** dup v[0-9]+\.4h, w[0-9]+ > > ** zip1 v[0-9]+\.8h, v[0-9]+\.8h, v[0-9]+\.8h > > ** ... > > ** ret > > @@ -23,8 +23,8 @@ int16x8_t foo(int16_t x, int y) > > /* > > ** foo2: > > ** ... > > -** dup v[0-9]+\.8h, w[0-9]+ > > -** movi v[0-9]+\.8h, 0x1 > > +** dup v[0-9]+\.4h, w[0-9]+ > > +** movi v[0-9]+\.4h, 0x1 > > ** zip1 v[0-9]+\.8h, v[0-9]+\.8h, v[0-9]+\.8h > > ** ... > > ** ret > > diff --git a/gcc/testsuite/gcc.target/aarch64/vec-init-19.c b/gcc/testsuite/gcc.target/aarch64/vec-init-19.c > > new file mode 100644 > > index 00000000000..e28fdcda29d > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/aarch64/vec-init-19.c > > @@ -0,0 +1,21 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-O3" } */ > > +/* { dg-final { check-function-bodies "**" "" "" } } */ > > + > > +#include > > + > > +/* > > +** f_s8: > > +** ... > > +** dup v[0-9]+\.8b, w[0-9]+ > > +** adrp x[0-9]+, \.LC[0-9]+ > > +** ldr d[0-9]+, \[x[0-9]+, #:lo12:.LC[0-9]+\] > > +** zip1 v[0-9]+\.16b, v[0-9]+\.16b, v[0-9]+\.16b > > This kind of match is dangerous for a test that enables scheduling, > since the zip sequences start with two independent sequences that > build 64-bit vectors. > > Since the lines of the match don't build on each other (e.g. they > don't use captures to ensure that the zip operands are in the right > order), I think it'd be better to use scan-assemblers instead. > > There's then no need to match the adrp. or the exact addressing > mode of the ldr. Just {ldr\td[0-9]+, } would be enough. > > Same comments for the other tests. > > Please also check that the new tests pass on big-endian targets. Hi Richard, Thanks for the suggestions, I have tried to address them in the attached patch. I verified the new tests pass on aarch64_be-linux-gnu, and patch is under bootstrap+progress on aarch64-linux-gnu. OK to commit if passes ? Thanks, Prathamesh > > Thanks, > Richard > > > +** ret > > +*/ > > + > > +int8x16_t f_s8(int8_t x) > > +{ > > + return (int8x16_t) { x, 1, x, 2, x, 3, x, 4, > > + x, 5, x, 6, x, 7, x, 8 }; > > +} > > diff --git a/gcc/testsuite/gcc.target/aarch64/vec-init-20.c b/gcc/testsuite/gcc.target/aarch64/vec-init-20.c > > new file mode 100644 > > index 00000000000..9366ca349b6 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/aarch64/vec-init-20.c > > @@ -0,0 +1,22 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-O3" } */ > > +/* { dg-final { check-function-bodies "**" "" "" } } */ > > + > > +#include > > + > > +/* > > +** f_s8: > > +** ... > > +** adrp x[0-9]+, \.LC[0-9]+ > > +** dup v[0-9]+\.8b, w[0-9]+ > > +** ldr d[0-9]+, \[x[0-9]+, #:lo12:\.LC[0-9]+\] > > +** ins v0\.b\[0\], w0 > > +** zip1 v[0-9]+\.16b, v[0-9]+\.16b, v[0-9]+\.16b > > +** ret > > +*/ > > + > > +int8x16_t f_s8(int8_t x, int8_t y) > > +{ > > + return (int8x16_t) { x, y, 1, y, 2, y, 3, y, > > + 4, y, 5, y, 6, y, 7, y }; > > +} > > diff --git a/gcc/testsuite/gcc.target/aarch64/vec-init-21.c b/gcc/testsuite/gcc.target/aarch64/vec-init-21.c > > new file mode 100644 > > index 00000000000..e16459486d7 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/aarch64/vec-init-21.c > > @@ -0,0 +1,22 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-O3" } */ > > +/* { dg-final { check-function-bodies "**" "" "" } } */ > > + > > +#include > > + > > +/* > > +** f_s8: > > +** ... > > +** adrp x[0-9]+, \.LC[0-9]+ > > +** ldr q[0-9]+, \[x[0-9]+, #:lo12:\.LC[0-9]+\] > > +** ins v0\.b\[0\], w0 > > +** ins v0\.b\[1\], w1 > > +** ... > > +** ret > > +*/ > > + > > +int8x16_t f_s8(int8_t x, int8_t y) > > +{ > > + return (int8x16_t) { x, y, 1, 2, 3, 4, 5, 6, > > + 7, 8, 9, 10, 11, 12, 13, 14 }; > > +} > > diff --git a/gcc/testsuite/gcc.target/aarch64/vec-init-22-size.c b/gcc/testsuite/gcc.target/aarch64/vec-init-22-size.c > > new file mode 100644 > > index 00000000000..8f35854c008 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/aarch64/vec-init-22-size.c > > @@ -0,0 +1,24 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-Os" } */ > > +/* { dg-final { check-function-bodies "**" "" "" } } */ > > + > > +/* Verify that fallback code-sequence is chosen over > > + recursively generated code-sequence merged with zip1. */ > > + > > +/* > > +** f_s16: > > +** ... > > +** sxth w0, w0 > > +** fmov s0, w0 > > +** ins v0\.h\[1\], w1 > > +** ins v0\.h\[2\], w2 > > +** ins v0\.h\[3\], w3 > > +** ins v0\.h\[4\], w4 > > +** ins v0\.h\[5\], w5 > > +** ins v0\.h\[6\], w6 > > +** ins v0\.h\[7\], w7 > > +** ... > > +** ret > > +*/ > > + > > +#include "vec-init-22.h" > > diff --git a/gcc/testsuite/gcc.target/aarch64/vec-init-22-speed.c b/gcc/testsuite/gcc.target/aarch64/vec-init-22-speed.c > > new file mode 100644 > > index 00000000000..172d56ffdf1 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/aarch64/vec-init-22-speed.c > > @@ -0,0 +1,27 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-O3" } */ > > +/* { dg-final { check-function-bodies "**" "" "" } } */ > > + > > +/* Verify that we recursively generate code for even and odd halves > > + instead of fallback code. This is so despite the longer code-gen > > + because it has fewer dependencies and thus has lesser cost. */ > > + > > +/* > > +** f_s16: > > +** ... > > +** sxth w0, w0 > > +** sxth w1, w1 > > +** fmov d0, x0 > > +** fmov d1, x1 > > +** ins v[0-9]+\.h\[1\], w2 > > +** ins v[0-9]+\.h\[1\], w3 > > +** ins v[0-9]+\.h\[2\], w4 > > +** ins v[0-9]+\.h\[2\], w5 > > +** ins v[0-9]+\.h\[3\], w6 > > +** ins v[0-9]+\.h\[3\], w7 > > +** zip1 v[0-9]+\.8h, v[0-9]+\.8h, v[0-9]+\.8h > > +** ... > > +** ret > > +*/ > > + > > +#include "vec-init-22.h" > > diff --git a/gcc/testsuite/gcc.target/aarch64/vec-init-22.h b/gcc/testsuite/gcc.target/aarch64/vec-init-22.h > > new file mode 100644 > > index 00000000000..15b889d4097 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/aarch64/vec-init-22.h > > @@ -0,0 +1,7 @@ > > +#include > > + > > +int16x8_t f_s16 (int16_t x0, int16_t x1, int16_t x2, int16_t x3, > > + int16_t x4, int16_t x5, int16_t x6, int16_t x7) > > +{ > > + return (int16x8_t) { x0, x1, x2, x3, x4, x5, x6, x7 }; > > +} --0000000000000cfb8a05fadcbf9e Content-Type: text/plain; charset="US-ASCII"; name="gnu-821-10.txt" Content-Disposition: attachment; filename="gnu-821-10.txt" Content-Transfer-Encoding: base64 Content-ID: X-Attachment-Id: f_lh929qpo0 W2FhcmNoNjRdIFJlY3Vyc2l2ZWx5IGludGlhbGl6ZSBldmVuIGFuZCBvZGQgc3ViLXBhcnRzIGFu ZCBtZXJnZSB3aXRoIHppcDEuCgpnY2MvQ2hhbmdlTG9nOgoJKiBjb25maWcvYWFyY2g2NC9hYXJj aDY0LmNjIChhYXJjaDY0X2V4cGFuZF92ZWN0b3JfaW5pdF9mYWxsYmFjayk6IFJlbmFtZQoJYWFy Y2g2NF9leHBhbmRfdmVjdG9yX2luaXQgdG8gdGhpcywgYW5kIHJlbW92ZSAJaW50ZXJsZWF2aW5n IGNhc2UuCglSZWN1cnNpdmVseSBjYWxsIGFhcmNoNjRfZXhwYW5kX3ZlY3Rvcl9pbml0X2ZhbGxi YWNrLCBpbnN0ZWFkIG9mCglhYXJjaDY0X2V4cGFuZF92ZWN0b3JfaW5pdC4KCShhYXJjaDY0X3Vu emlwX3ZlY3Rvcl9pbml0KTogTmV3IGZ1bmN0aW9uLgoJKGFhcmNoNjRfZXhwYW5kX3ZlY3Rvcl9p bml0KTogTGlrZXdpc2UuCgpnY2MvdGVzdHN1aXRlL0NoYW5nZUxvZzoKCSogZ2NjLnRhcmdldC9h YXJjaDY0L2xkcF9zdHBfMTYuYyAoY29uczJfOF9mbG9hdCk6IEFkanVzdCBmb3IgbmV3Cgljb2Rl LWdlbi4KCSogZ2NjLnRhcmdldC9hYXJjaDY0L3N2ZS9hY2xlL2dlbmVyYWwvZHVwcV81LmM6IExp a2V3aXNlLgoJKiBnY2MudGFyZ2V0L2FhcmNoNjQvc3ZlL2FjbGUvZ2VuZXJhbC9kdXBxXzYuYzog TGlrZXdpc2UuCgkqIGdjYy50YXJnZXQvYWFyY2g2NC92ZWMtaW5pdC0xOC5jOiBSZW5hbWUgaW50 ZXJsZWF2ZS1pbml0LTEuYyB0bwoJdGhpcy4KCSogZ2NjLnRhcmdldC9hYXJjaDY0L3ZlYy1pbml0 LTE5LmM6IE5ldyB0ZXN0LgoJKiBnY2MudGFyZ2V0L2FhcmNoNjQvdmVjLWluaXQtMjAuYzogTGlr ZXdpc2UuCgkqIGdjYy50YXJnZXQvYWFyY2g2NC92ZWMtaW5pdC0yMS5jOiBMaWtld2lzZS4KCSog Z2NjLnRhcmdldC9hYXJjaDY0L3ZlYy1pbml0LTIyLXNpemUuYzogTGlrZXdpc2UuCgkqIGdjYy50 YXJnZXQvYWFyY2g2NC92ZWMtaW5pdC0yMi1zcGVlZC5jOiBMaWtld2lzZS4KCSogZ2NjLnRhcmdl dC9hYXJjaDY0L3ZlYy1pbml0LTIyLmg6IE5ldyBoZWFkZXIuCgpkaWZmIC0tZ2l0IGEvZ2NjL2Nv bmZpZy9hYXJjaDY0L2FhcmNoNjQuY2MgYi9nY2MvY29uZmlnL2FhcmNoNjQvYWFyY2g2NC5jYwpp bmRleCAyYjBkZTdjYTAzOC4uNDhlY2UwYWQzMjggMTAwNjQ0Ci0tLSBhL2djYy9jb25maWcvYWFy Y2g2NC9hYXJjaDY0LmNjCisrKyBiL2djYy9jb25maWcvYWFyY2g2NC9hYXJjaDY0LmNjCkBAIC0y MjA2MCwxMSArMjIwNjAsMTIgQEAgYWFyY2g2NF9zaW1kX21ha2VfY29uc3RhbnQgKHJ0eCB2YWxz KQogICAgIHJldHVybiBOVUxMX1JUWDsKIH0KIAotLyogRXhwYW5kIGEgdmVjdG9yIGluaXRpYWxp c2F0aW9uIHNlcXVlbmNlLCBzdWNoIHRoYXQgVEFSR0VUIGlzCi0gICBpbml0aWFsaXNlZCB0byBj b250YWluIFZBTFMuICAqLworLyogQSBzdWJyb3V0aW5lIG9mIGFhcmNoNjRfZXhwYW5kX3ZlY3Rv cl9pbml0LCB3aXRoIHRoZSBzYW1lIGludGVyZmFjZS4KKyAgIFRoZSBjYWxsZXIgaGFzIGFscmVh ZHkgdHJpZWQgYSBkaXZpZGUtYW5kLWNvbnF1ZXIgYXBwcm9hY2gsIHNvIGRvCisgICBub3QgY29u c2lkZXIgdGhhdCBjYXNlIGhlcmUuICAqLwogCiB2b2lkCi1hYXJjaDY0X2V4cGFuZF92ZWN0b3Jf aW5pdCAocnR4IHRhcmdldCwgcnR4IHZhbHMpCithYXJjaDY0X2V4cGFuZF92ZWN0b3JfaW5pdF9m YWxsYmFjayAocnR4IHRhcmdldCwgcnR4IHZhbHMpCiB7CiAgIG1hY2hpbmVfbW9kZSBtb2RlID0g R0VUX01PREUgKHRhcmdldCk7CiAgIHNjYWxhcl9tb2RlIGlubmVyX21vZGUgPSBHRVRfTU9ERV9J Tk5FUiAobW9kZSk7CkBAIC0yMjEyNCwzOCArMjIxMjUsNiBAQCBhYXJjaDY0X2V4cGFuZF92ZWN0 b3JfaW5pdCAocnR4IHRhcmdldCwgcnR4IHZhbHMpCiAgICAgICByZXR1cm47CiAgICAgfQogCi0g IC8qIENoZWNrIGZvciBpbnRlcmxlYXZpbmcgY2FzZS4KLSAgICAgRm9yIGVnIGlmIGluaXRpYWxp emVyIGlzIChpbnQxNng4X3QpIHt4LCB5LCB4LCB5LCB4LCB5LCB4LCB5fS4KLSAgICAgR2VuZXJh dGUgZm9sbG93aW5nIGNvZGU6Ci0gICAgIGR1cCB2MC5oLCB4Ci0gICAgIGR1cCB2MS5oLCB5Ci0g ICAgIHppcDEgdjAuaCwgdjAuaCwgdjEuaAotICAgICBmb3IgImxhcmdlIGVub3VnaCIgaW5pdGlh bGl6ZXIuICAqLwotCi0gIGlmIChuX2VsdHMgPj0gOCkKLSAgICB7Ci0gICAgICBpbnQgaTsKLSAg ICAgIGZvciAoaSA9IDI7IGkgPCBuX2VsdHM7IGkrKykKLQlpZiAoIXJ0eF9lcXVhbF9wIChYVkVD RVhQICh2YWxzLCAwLCBpKSwgWFZFQ0VYUCAodmFscywgMCwgaSAlIDIpKSkKLQkgIGJyZWFrOwot Ci0gICAgICBpZiAoaSA9PSBuX2VsdHMpCi0JewotCSAgbWFjaGluZV9tb2RlIG1vZGUgPSBHRVRf TU9ERSAodGFyZ2V0KTsKLQkgIHJ0eCBkZXN0WzJdOwotCi0JICBmb3IgKGludCBpID0gMDsgaSA8 IDI7IGkrKykKLQkgICAgewotCSAgICAgIHJ0eCB4ID0gZXhwYW5kX3ZlY3Rvcl9icm9hZGNhc3Qg KG1vZGUsIFhWRUNFWFAgKHZhbHMsIDAsIGkpKTsKLQkgICAgICBkZXN0W2ldID0gZm9yY2VfcmVn IChtb2RlLCB4KTsKLQkgICAgfQotCi0JICBydHZlYyB2ID0gZ2VuX3J0dmVjICgyLCBkZXN0WzBd LCBkZXN0WzFdKTsKLQkgIGVtaXRfc2V0X2luc24gKHRhcmdldCwgZ2VuX3J0eF9VTlNQRUMgKG1v ZGUsIHYsIFVOU1BFQ19aSVAxKSk7Ci0JICByZXR1cm47Ci0JfQotICAgIH0KLQogICBlbnVtIGlu c25fY29kZSBpY29kZSA9IG9wdGFiX2hhbmRsZXIgKHZlY19zZXRfb3B0YWIsIG1vZGUpOwogICBn Y2NfYXNzZXJ0IChpY29kZSAhPSBDT0RFX0ZPUl9ub3RoaW5nKTsKIApAQCAtMjIyNzcsNyArMjIy NDYsNyBAQCBhYXJjaDY0X2V4cGFuZF92ZWN0b3JfaW5pdCAocnR4IHRhcmdldCwgcnR4IHZhbHMp CiAJICAgIH0KIAkgIFhWRUNFWFAgKGNvcHksIDAsIGkpID0gc3Vic3Q7CiAJfQotICAgICAgYWFy Y2g2NF9leHBhbmRfdmVjdG9yX2luaXQgKHRhcmdldCwgY29weSk7CisgICAgICBhYXJjaDY0X2V4 cGFuZF92ZWN0b3JfaW5pdF9mYWxsYmFjayAodGFyZ2V0LCBjb3B5KTsKICAgICB9CiAKICAgLyog SW5zZXJ0IHRoZSB2YXJpYWJsZSBsYW5lcyBkaXJlY3RseS4gICovCkBAIC0yMjI5MSw2ICsyMjI2 MCw4MCBAQCBhYXJjaDY0X2V4cGFuZF92ZWN0b3JfaW5pdCAocnR4IHRhcmdldCwgcnR4IHZhbHMp CiAgICAgfQogfQogCisvKiBSZXR1cm4gZXZlbiBvciBvZGQgaGFsZiBvZiBWQUxTIGRlcGVuZGlu ZyBvbiBFVkVOX1AuICAqLworCitzdGF0aWMgcnR4CithYXJjaDY0X3VuemlwX3ZlY3Rvcl9pbml0 IChtYWNoaW5lX21vZGUgbW9kZSwgcnR4IHZhbHMsIGJvb2wgZXZlbl9wKQoreworICBpbnQgbiA9 IFhWRUNMRU4gKHZhbHMsIDApOworICBtYWNoaW5lX21vZGUgbmV3X21vZGUKKyAgICA9IGFhcmNo NjRfc2ltZF9jb250YWluZXJfbW9kZSAoR0VUX01PREVfSU5ORVIgKG1vZGUpLAorCQkJCSAgIEdF VF9NT0RFX0JJVFNJWkUgKG1vZGUpLnRvX2NvbnN0YW50ICgpIC8gMik7CisgIHJ0dmVjIHZlYyA9 IHJ0dmVjX2FsbG9jIChuIC8gMik7CisgIGZvciAoaW50IGkgPSAwOyBpIDwgbiAvIDI7IGkrKykK KyAgICBSVFZFQ19FTFQgKHZlYywgaSkgPSAoZXZlbl9wKSA/IFhWRUNFWFAgKHZhbHMsIDAsIDIg KiBpKQorCQkJCSAgOiBYVkVDRVhQICh2YWxzLCAwLCAyICogaSArIDEpOworICByZXR1cm4gZ2Vu X3J0eF9QQVJBTExFTCAobmV3X21vZGUsIHZlYyk7Cit9CisKKy8qIEV4cGFuZCBhIHZlY3RvciBp bml0aWFsaXphdGlvbiBzZXF1ZW5jZSwgc3VjaCB0aGF0IFRBUkdFVCBpcworICAgaW5pdGlhbGl6 ZWQgdG8gY29udGFpbiBWQUxTLiAgKi8KKwordm9pZAorYWFyY2g2NF9leHBhbmRfdmVjdG9yX2lu aXQgKHJ0eCB0YXJnZXQsIHJ0eCB2YWxzKQoreworICAvKiBUcnkgZGVjb21wb3NpbmcgdGhlIGlu aXRpYWxpemVyIGludG8gZXZlbiBhbmQgb2RkIGhhbHZlcyBhbmQKKyAgICAgdGhlbiBaSVAgdGhl bSB0b2dldGhlci4gIFVzZSB0aGUgcmVzdWx0aW5nIHNlcXVlbmNlIGlmIGl0IGlzCisgICAgIHN0 cmljdGx5IGNoZWFwZXIgdGhhbiBsb2FkaW5nIFZBTFMgZGlyZWN0bHkuCisKKyAgICAgUHJlZmVy IHRoZSBmYWxsYmFjayBzZXF1ZW5jZSBpbiB0aGUgZXZlbnQgb2YgYSB0aWUsIHNpbmNlIGl0Cisg ICAgIHdpbGwgdGVuZCB0byB1c2UgZmV3ZXIgcmVnaXN0ZXJzLiAgKi8KKworICBtYWNoaW5lX21v ZGUgbW9kZSA9IEdFVF9NT0RFICh0YXJnZXQpOworICBpbnQgbl9lbHRzID0gWFZFQ0xFTiAodmFs cywgMCk7CisKKyAgaWYgKG5fZWx0cyA8IDQKKyAgICAgIHx8IG1heWJlX25lIChHRVRfTU9ERV9C SVRTSVpFIChtb2RlKSwgMTI4KSkKKyAgICB7CisgICAgICBhYXJjaDY0X2V4cGFuZF92ZWN0b3Jf aW5pdF9mYWxsYmFjayAodGFyZ2V0LCB2YWxzKTsKKyAgICAgIHJldHVybjsKKyAgICB9CisKKyAg c3RhcnRfc2VxdWVuY2UgKCk7CisgIHJ0eCBoYWx2ZXNbMl07CisgIHVuc2lnbmVkIGNvc3RzWzJd OworICBmb3IgKGludCBpID0gMDsgaSA8IDI7IGkrKykKKyAgICB7CisgICAgICBzdGFydF9zZXF1 ZW5jZSAoKTsKKyAgICAgIHJ0eCBuZXdfdmFscyA9IGFhcmNoNjRfdW56aXBfdmVjdG9yX2luaXQg KG1vZGUsIHZhbHMsIGkgPT0gMCk7CisgICAgICBydHggdG1wX3JlZyA9IGdlbl9yZWdfcnR4IChH RVRfTU9ERSAobmV3X3ZhbHMpKTsKKyAgICAgIGFhcmNoNjRfZXhwYW5kX3ZlY3Rvcl9pbml0ICh0 bXBfcmVnLCBuZXdfdmFscyk7CisgICAgICBoYWx2ZXNbaV0gPSBnZW5fcnR4X1NVQlJFRyAobW9k ZSwgdG1wX3JlZywgMCk7CisgICAgICBydHhfaW5zbiAqcmVjX3NlcSA9IGdldF9pbnNucyAoKTsK KyAgICAgIGVuZF9zZXF1ZW5jZSAoKTsKKyAgICAgIGNvc3RzW2ldID0gc2VxX2Nvc3QgKHJlY19z ZXEsICFvcHRpbWl6ZV9zaXplKTsKKyAgICAgIGVtaXRfaW5zbiAocmVjX3NlcSk7CisgICAgfQor CisgIHJ0dmVjIHYgPSBnZW5fcnR2ZWMgKDIsIGhhbHZlc1swXSwgaGFsdmVzWzFdKTsKKyAgcnR4 X2luc24gKnppcDFfaW5zbgorICAgID0gZW1pdF9zZXRfaW5zbiAodGFyZ2V0LCBnZW5fcnR4X1VO U1BFQyAobW9kZSwgdiwgVU5TUEVDX1pJUDEpKTsKKyAgdW5zaWduZWQgc2VxX3RvdGFsX2Nvc3QK KyAgICA9ICghb3B0aW1pemVfc2l6ZSkgPyBzdGQ6Om1heCAoY29zdHNbMF0sIGNvc3RzWzFdKSA6 IGNvc3RzWzBdICsgY29zdHNbMV07CisgIHNlcV90b3RhbF9jb3N0ICs9IGluc25fY29zdCAoemlw MV9pbnNuLCAhb3B0aW1pemVfc2l6ZSk7CisKKyAgcnR4X2luc24gKnNlcSA9IGdldF9pbnNucyAo KTsKKyAgZW5kX3NlcXVlbmNlICgpOworCisgIHN0YXJ0X3NlcXVlbmNlICgpOworICBhYXJjaDY0 X2V4cGFuZF92ZWN0b3JfaW5pdF9mYWxsYmFjayAodGFyZ2V0LCB2YWxzKTsKKyAgcnR4X2luc24g KmZhbGxiYWNrX3NlcSA9IGdldF9pbnNucyAoKTsKKyAgdW5zaWduZWQgZmFsbGJhY2tfc2VxX2Nv c3QgPSBzZXFfY29zdCAoZmFsbGJhY2tfc2VxLCAhb3B0aW1pemVfc2l6ZSk7CisgIGVuZF9zZXF1 ZW5jZSAoKTsKKworICBlbWl0X2luc24gKHNlcV90b3RhbF9jb3N0IDwgZmFsbGJhY2tfc2VxX2Nv c3QgPyBzZXEgOiBmYWxsYmFja19zZXEpOworfQorCiAvKiBFbWl0IFJUTCBjb3JyZXNwb25kaW5n IHRvOgogICAgaW5zciBUQVJHRVQsIEVMRU0uICAqLwogCmRpZmYgLS1naXQgYS9nY2MvdGVzdHN1 aXRlL2djYy50YXJnZXQvYWFyY2g2NC9pbnRlcmxlYXZlLWluaXQtMS5jIGIvZ2NjL3Rlc3RzdWl0 ZS9nY2MudGFyZ2V0L2FhcmNoNjQvaW50ZXJsZWF2ZS1pbml0LTEuYwpkZWxldGVkIGZpbGUgbW9k ZSAxMDA2NDQKaW5kZXggZWU3NzUwNDg1ODkuLjAwMDAwMDAwMDAwCi0tLSBhL2djYy90ZXN0c3Vp dGUvZ2NjLnRhcmdldC9hYXJjaDY0L2ludGVybGVhdmUtaW5pdC0xLmMKKysrIC9kZXYvbnVsbApA QCAtMSwzNyArMCwwIEBACi0vKiB7IGRnLWRvIGNvbXBpbGUgfSAqLwotLyogeyBkZy1vcHRpb25z ICItTzMiIH0gKi8KLS8qIHsgZGctZmluYWwgeyBjaGVjay1mdW5jdGlvbi1ib2RpZXMgIioqIiAi IiAiIiB9IH0gKi8KLQotI2luY2x1ZGUgPGFybV9uZW9uLmg+Ci0KLS8qCi0qKiBmb286Ci0qKgku Li4KLSoqCWR1cAl2WzAtOV0rXC44aCwgd1swLTldKwotKioJZHVwCXZbMC05XStcLjhoLCB3WzAt OV0rCi0qKgl6aXAxCXZbMC05XStcLjhoLCB2WzAtOV0rXC44aCwgdlswLTldK1wuOGgKLSoqCS4u LgotKioJcmV0Ci0qLwotCi1pbnQxNng4X3QgZm9vKGludDE2X3QgeCwgaW50IHkpCi17Ci0gIGlu dDE2eDhfdCB2ID0gKGludDE2eDhfdCkge3gsIHksIHgsIHksIHgsIHksIHgsIHl9OyAKLSAgcmV0 dXJuIHY7Ci19Ci0KLS8qCi0qKiBmb28yOgotKioJLi4uCi0qKglkdXAJdlswLTldK1wuOGgsIHdb MC05XSsKLSoqCW1vdmkJdlswLTldK1wuOGgsIDB4MQotKioJemlwMQl2WzAtOV0rXC44aCwgdlsw LTldK1wuOGgsIHZbMC05XStcLjhoCi0qKgkuLi4KLSoqCXJldAotKi8KLQotaW50MTZ4OF90IGZv bzIoaW50MTZfdCB4KSAKLXsKLSAgaW50MTZ4OF90IHYgPSAoaW50MTZ4OF90KSB7eCwgMSwgeCwg MSwgeCwgMSwgeCwgMX07IAotICByZXR1cm4gdjsKLX0KZGlmZiAtLWdpdCBhL2djYy90ZXN0c3Vp dGUvZ2NjLnRhcmdldC9hYXJjaDY0L2xkcF9zdHBfMTYuYyBiL2djYy90ZXN0c3VpdGUvZ2NjLnRh cmdldC9hYXJjaDY0L2xkcF9zdHBfMTYuYwppbmRleCA4YWIxMTdjNGRjZC4uYmExNDE5NGQwYTQg MTAwNjQ0Ci0tLSBhL2djYy90ZXN0c3VpdGUvZ2NjLnRhcmdldC9hYXJjaDY0L2xkcF9zdHBfMTYu YworKysgYi9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYWFyY2g2NC9sZHBfc3RwXzE2LmMKQEAg LTk2LDggKzk2LDkgQEAgQ09OUzJfRk4gKDQsIGZsb2F0KTsKIAogLyoKICoqIGNvbnMyXzhfZmxv YXQ6Ci0qKglkdXAJdihbMC05XSspXC40cywgLioKLSoqCS4uLgorKioJZHVwCXZbMC05XStcLjJz LCB2WzAtOV0rXC5zXFswXF0KKyoqCWR1cAl2WzAtOV0rXC4ycywgdlswLTldK1wuc1xbMFxdCisq Kgl6aXAxCXYoWzAtOV0rKVwuNHMsIHZbMC05XStcLjRzLCB2WzAtOV0rXC40cwogKioJc3RwCXFc MSwgcVwxLCBcW3gwXF0KICoqCXN0cAlxXDEsIHFcMSwgXFt4MCwgIz8zMlxdCiAqKglyZXQKZGlm ZiAtLWdpdCBhL2djYy90ZXN0c3VpdGUvZ2NjLnRhcmdldC9hYXJjaDY0L3N2ZS9hY2xlL2dlbmVy YWwvZHVwcV81LmMgYi9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYWFyY2g2NC9zdmUvYWNsZS9n ZW5lcmFsL2R1cHFfNS5jCmluZGV4IDUzNDI2YzlhZjVhLi5jN2Q2ZjNmZjM5MCAxMDA2NDQKLS0t IGEvZ2NjL3Rlc3RzdWl0ZS9nY2MudGFyZ2V0L2FhcmNoNjQvc3ZlL2FjbGUvZ2VuZXJhbC9kdXBx XzUuYworKysgYi9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYWFyY2g2NC9zdmUvYWNsZS9nZW5l cmFsL2R1cHFfNS5jCkBAIC0xMSw3ICsxMSw3IEBAIGR1cHEgKGludCB4MSwgaW50IHgyLCBpbnQg eDMsIGludCB4NCkKIAogLyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyLW5vdCB7XHRsZHJc dH0gfSB9ICovCiAvKiB7IGRnLWZpbmFsIHsgc2Nhbi1hc3NlbWJsZXIgeywgW3d4XTBcbn0gfSB9 ICovCi0vKiB7IGRnLWZpbmFsIHsgc2Nhbi1hc3NlbWJsZXIge1x0aW5zXHR2WzAtOV0rXC5zXFsx XF0sIHcxXG59IH0gfSAqLwotLyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyIHtcdGluc1x0 dlswLTldK1wuc1xbMlxdLCB3MlxufSB9IH0gKi8KLS8qIHsgZGctZmluYWwgeyBzY2FuLWFzc2Vt YmxlciB7XHRpbnNcdHZbMC05XStcLnNcWzNcXSwgdzNcbn0gfSB9ICovCisvKiB7IGRnLWZpbmFs IHsgc2Nhbi1hc3NlbWJsZXIge1x0aW5zXHR2WzAtOV0rXC5zXFsxXF0sIHcyXG59IH0gfSAqLwor LyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyIHtcdGluc1x0dlswLTldK1wuc1xbMVxdLCB3 M1xufSB9IH0gKi8KKy8qIHsgZGctZmluYWwgeyBzY2FuLWFzc2VtYmxlciB7XHR6aXAxXHR2WzAt OV0rXC40cywgdlswLTldK1wuNHMsIHZbMC05XVwuNHNcbn0gfSB9ICovCiAvKiB7IGRnLWZpbmFs IHsgc2Nhbi1hc3NlbWJsZXIge1x0ZHVwXHR6WzAtOV0rXC5xLCB6WzAtOV0rXC5xXFswXF1cbn0g fSB9ICovCmRpZmYgLS1naXQgYS9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYWFyY2g2NC9zdmUv YWNsZS9nZW5lcmFsL2R1cHFfNi5jIGIvZ2NjL3Rlc3RzdWl0ZS9nY2MudGFyZ2V0L2FhcmNoNjQv c3ZlL2FjbGUvZ2VuZXJhbC9kdXBxXzYuYwppbmRleCBkZmNlNWU3YTEyYS4uNDc0NWEzODE1YjAg MTAwNjQ0Ci0tLSBhL2djYy90ZXN0c3VpdGUvZ2NjLnRhcmdldC9hYXJjaDY0L3N2ZS9hY2xlL2dl bmVyYWwvZHVwcV82LmMKKysrIGIvZ2NjL3Rlc3RzdWl0ZS9nY2MudGFyZ2V0L2FhcmNoNjQvc3Zl L2FjbGUvZ2VuZXJhbC9kdXBxXzYuYwpAQCAtMTIsNyArMTIsNyBAQCBkdXBxIChpbnQgeDEsIGlu dCB4MiwgaW50IHgzLCBpbnQgeDQpCiAKIC8qIHsgZGctZmluYWwgeyBzY2FuLWFzc2VtYmxlci1u b3Qge1x0bGRyXHR9IH0gfSAqLwogLyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyIHssIFt3 eF0wXG59IH0gfSAqLwotLyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyIHtcdGluc1x0dlsw LTldK1wuc1xbMVxdLCB3MVxufSB9IH0gKi8KLS8qIHsgZGctZmluYWwgeyBzY2FuLWFzc2VtYmxl ciB7XHRpbnNcdHZbMC05XStcLnNcWzJcXSwgdzJcbn0gfSB9ICovCi0vKiB7IGRnLWZpbmFsIHsg c2Nhbi1hc3NlbWJsZXIge1x0aW5zXHR2WzAtOV0rXC5zXFszXF0sIHczXG59IH0gfSAqLworLyog eyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyIHtcdGluc1x0dlswLTldK1wuc1xbMVxdLCB3Mlxu fSB9IH0gKi8KKy8qIHsgZGctZmluYWwgeyBzY2FuLWFzc2VtYmxlciB7XHRpbnNcdHZbMC05XStc LnNcWzFcXSwgdzNcbn0gfSB9ICovCisvKiB7IGRnLWZpbmFsIHsgc2Nhbi1hc3NlbWJsZXIge1x0 emlwMVx0dlswLTldK1wuNHMsIHZbMC05XStcLjRzLCB2WzAtOV1cLjRzXG59IH0gfSAqLwogLyog eyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyIHtcdGR1cFx0elswLTldK1wucSwgelswLTldK1wu cVxbMFxdXG59IH0gfSAqLwpkaWZmIC0tZ2l0IGEvZ2NjL3Rlc3RzdWl0ZS9nY2MudGFyZ2V0L2Fh cmNoNjQvdmVjLWluaXQtMTguYyBiL2djYy90ZXN0c3VpdGUvZ2NjLnRhcmdldC9hYXJjaDY0L3Zl Yy1pbml0LTE4LmMKbmV3IGZpbGUgbW9kZSAxMDA2NDQKaW5kZXggMDAwMDAwMDAwMDAuLjU5OGE1 MWYxN2M2Ci0tLSAvZGV2L251bGwKKysrIGIvZ2NjL3Rlc3RzdWl0ZS9nY2MudGFyZ2V0L2FhcmNo NjQvdmVjLWluaXQtMTguYwpAQCAtMCwwICsxLDIwIEBACisvKiB7IGRnLWRvIGNvbXBpbGUgfSAq LworLyogeyBkZy1vcHRpb25zICItTzMiIH0gKi8KKworI2luY2x1ZGUgPGFybV9uZW9uLmg+CisK K2ludDE2eDhfdCBmb28oaW50MTZfdCB4LCBpbnQgeSkKK3sKKyAgaW50MTZ4OF90IHYgPSAoaW50 MTZ4OF90KSB7eCwgeSwgeCwgeSwgeCwgeSwgeCwgeX07IAorICByZXR1cm4gdjsKK30KKworaW50 MTZ4OF90IGZvbzIoaW50MTZfdCB4KSAKK3sKKyAgaW50MTZ4OF90IHYgPSAoaW50MTZ4OF90KSB7 eCwgMSwgeCwgMSwgeCwgMSwgeCwgMX07IAorICByZXR1cm4gdjsKK30KKworLyogeyBkZy1maW5h bCB7IHNjYW4tYXNzZW1ibGVyLXRpbWVzIHtcdGR1cFx0dlswLTldK1wuNGgsIHdbMC05XSt9IDMg fSB9ICovCisvKiB7IGRnLWZpbmFsIHsgc2Nhbi1hc3NlbWJsZXIge1x0bW92aVx0dlswLTldK1wu NGgsIDB4MX0gfSB9ICovCisvKiB7IGRnLWZpbmFsIHsgc2Nhbi1hc3NlbWJsZXIge1x0emlwMVx0 dlswLTldK1wuOGgsIHZbMC05XStcLjhoLCB2WzAtOV0rXC44aH0gfSB9ICovCmRpZmYgLS1naXQg YS9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYWFyY2g2NC92ZWMtaW5pdC0xOS5jIGIvZ2NjL3Rl c3RzdWl0ZS9nY2MudGFyZ2V0L2FhcmNoNjQvdmVjLWluaXQtMTkuYwpuZXcgZmlsZSBtb2RlIDEw MDY0NAppbmRleCAwMDAwMDAwMDAwMC4uNDZlOWRiZjUxYTMKLS0tIC9kZXYvbnVsbAorKysgYi9n Y2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYWFyY2g2NC92ZWMtaW5pdC0xOS5jCkBAIC0wLDAgKzEs MTQgQEAKKy8qIHsgZGctZG8gY29tcGlsZSB9ICovCisvKiB7IGRnLW9wdGlvbnMgIi1PMyIgfSAq LworCisjaW5jbHVkZSA8YXJtX25lb24uaD4KKworaW50OHgxNl90IGZfczgoaW50OF90IHgpCit7 CisgIHJldHVybiAoaW50OHgxNl90KSB7IHgsIDEsIHgsIDIsIHgsIDMsIHgsIDQsCisgICAgICAg ICAgICAgICAgICAgICAgIHgsIDUsIHgsIDYsIHgsIDcsIHgsIDggfTsKK30KKworLyogeyBkZy1m aW5hbCB7IHNjYW4tYXNzZW1ibGVyIHtcdGR1cFx0dlswLTldK1wuOGIsIHdbMC05XSt9IH0gfSAq LworLyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyIHtcdGxkclx0ZFswLTldKyx9IH0gfSAq LworLyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyIHtcdHppcDFcdHZbMC05XStcLjE2Yiwg dlswLTldK1wuMTZiLCB2WzAtOV0rXC4xNmJ9IH0gfSAqLwpkaWZmIC0tZ2l0IGEvZ2NjL3Rlc3Rz dWl0ZS9nY2MudGFyZ2V0L2FhcmNoNjQvdmVjLWluaXQtMjAuYyBiL2djYy90ZXN0c3VpdGUvZ2Nj LnRhcmdldC9hYXJjaDY0L3ZlYy1pbml0LTIwLmMKbmV3IGZpbGUgbW9kZSAxMDA2NDQKaW5kZXgg MDAwMDAwMDAwMDAuLjQ0OTQxMjFjYjJkCi0tLSAvZGV2L251bGwKKysrIGIvZ2NjL3Rlc3RzdWl0 ZS9nY2MudGFyZ2V0L2FhcmNoNjQvdmVjLWluaXQtMjAuYwpAQCAtMCwwICsxLDE1IEBACisvKiB7 IGRnLWRvIGNvbXBpbGUgfSAqLworLyogeyBkZy1vcHRpb25zICItTzMiIH0gKi8KKworI2luY2x1 ZGUgPGFybV9uZW9uLmg+CisKK2ludDh4MTZfdCBmX3M4KGludDhfdCB4LCBpbnQ4X3QgeSkKK3sK KyAgcmV0dXJuIChpbnQ4eDE2X3QpIHsgeCwgeSwgMSwgeSwgMiwgeSwgMywgeSwKKyAgICAgICAg ICAgICAgICAgICAgICAgNCwgeSwgNSwgeSwgNiwgeSwgNywgeSB9OworfQorCisvKiB7IGRnLWZp bmFsIHsgc2Nhbi1hc3NlbWJsZXIge1x0ZHVwXHR2WzAtOV0rXC44Yiwgd1swLTldK30gfSB9ICov CisvKiB7IGRnLWZpbmFsIHsgc2Nhbi1hc3NlbWJsZXIge1x0bGRyXHRkWzAtOV0rLH0gfSB9ICov CisvKiB7IGRnLWZpbmFsIHsgc2Nhbi1hc3NlbWJsZXIge1x0aW5zXHR2WzAtOV0rXC5iXFswfDdc XSwgd1swLTldK30gfSB9ICovCisvKiB7IGRnLWZpbmFsIHsgc2Nhbi1hc3NlbWJsZXIge1x0emlw MVx0dlswLTldK1wuMTZiLCB2WzAtOV0rXC4xNmIsIHZbMC05XStcLjE2Yn0gfSB9ICovCmRpZmYg LS1naXQgYS9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYWFyY2g2NC92ZWMtaW5pdC0yMS5jIGIv Z2NjL3Rlc3RzdWl0ZS9nY2MudGFyZ2V0L2FhcmNoNjQvdmVjLWluaXQtMjEuYwpuZXcgZmlsZSBt b2RlIDEwMDY0NAppbmRleCAwMDAwMDAwMDAwMC4uZjUzZTBlZDA4ZDUKLS0tIC9kZXYvbnVsbAor KysgYi9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYWFyY2g2NC92ZWMtaW5pdC0yMS5jCkBAIC0w LDAgKzEsMTQgQEAKKy8qIHsgZGctZG8gY29tcGlsZSB9ICovCisvKiB7IGRnLW9wdGlvbnMgIi1P MyIgfSAqLworCisjaW5jbHVkZSA8YXJtX25lb24uaD4KKworaW50OHgxNl90IGZfczgoaW50OF90 IHgsIGludDhfdCB5KQoreworICByZXR1cm4gKGludDh4MTZfdCkgeyB4LCB5LCAxLCAyLCAzLCA0 LCA1LCA2LAorICAgICAgICAgICAgICAgICAgICAgICA3LCA4LCA5LCAxMCwgMTEsIDEyLCAxMywg MTQgfTsKK30KKworLyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyIHtcdGxkclx0cVswLTld Kyx9IH0gfSAqLworLyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyIHtcdGluc1x0dlswLTld K1wuYlxbMHwxNVxdLCB3MH0gfSB9ICovCisvKiB7IGRnLWZpbmFsIHsgc2Nhbi1hc3NlbWJsZXIg e1x0aW5zXHR2WzAtOV0rXC5iXFsxfDE0XF0sIHcxfSB9IH0gKi8KZGlmZiAtLWdpdCBhL2djYy90 ZXN0c3VpdGUvZ2NjLnRhcmdldC9hYXJjaDY0L3ZlYy1pbml0LTIyLXNpemUuYyBiL2djYy90ZXN0 c3VpdGUvZ2NjLnRhcmdldC9hYXJjaDY0L3ZlYy1pbml0LTIyLXNpemUuYwpuZXcgZmlsZSBtb2Rl IDEwMDY0NAppbmRleCAwMDAwMDAwMDAwMC4uNDMzM2ZmNTAyMDUKLS0tIC9kZXYvbnVsbAorKysg Yi9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYWFyY2g2NC92ZWMtaW5pdC0yMi1zaXplLmMKQEAg LTAsMCArMSwxMCBAQAorLyogeyBkZy1kbyBjb21waWxlIH0gKi8KKy8qIHsgZGctb3B0aW9ucyAi LU9zIiB9ICovCisKKy8qIFZlcmlmeSB0aGF0IGZhbGxiYWNrIGNvZGUtc2VxdWVuY2UgaXMgY2hv c2VuIG92ZXIKKyAgIHJlY3Vyc2l2ZWx5IGdlbmVyYXRlZCBjb2RlLXNlcXVlbmNlIG1lcmdlZCB3 aXRoIHppcDEuICAqLworCisjaW5jbHVkZSAidmVjLWluaXQtMjIuaCIKKworLyogeyBkZy1maW5h bCB7IHNjYW4tYXNzZW1ibGVyIHtcdGZtb3ZcdHNbMC05XSssIHcwfHc3fSB9IH0gKi8KKy8qIHsg ZGctZmluYWwgeyBzY2FuLWFzc2VtYmxlci10aW1lcyB7XHRpbnNcdHZbMC05XStcLmhcW1sxLTdd XF0sIHdbMC05XSt9IDcgfSB9ICovCmRpZmYgLS1naXQgYS9nY2MvdGVzdHN1aXRlL2djYy50YXJn ZXQvYWFyY2g2NC92ZWMtaW5pdC0yMi1zcGVlZC5jIGIvZ2NjL3Rlc3RzdWl0ZS9nY2MudGFyZ2V0 L2FhcmNoNjQvdmVjLWluaXQtMjItc3BlZWQuYwpuZXcgZmlsZSBtb2RlIDEwMDY0NAppbmRleCAw MDAwMDAwMDAwMC4uOTkzZWY4YzQxNjEKLS0tIC9kZXYvbnVsbAorKysgYi9nY2MvdGVzdHN1aXRl L2djYy50YXJnZXQvYWFyY2g2NC92ZWMtaW5pdC0yMi1zcGVlZC5jCkBAIC0wLDAgKzEsMTIgQEAK Ky8qIHsgZGctZG8gY29tcGlsZSB9ICovCisvKiB7IGRnLW9wdGlvbnMgIi1PMyIgfSAqLworCisv KiBWZXJpZnkgdGhhdCB3ZSByZWN1cnNpdmVseSBnZW5lcmF0ZSBjb2RlIGZvciBldmVuIGFuZCBv ZGQgaGFsdmVzCisgICBpbnN0ZWFkIG9mIGZhbGxiYWNrIGNvZGUuIFRoaXMgaXMgc28gZGVzcGl0 ZSB0aGUgbG9uZ2VyIGNvZGUtZ2VuCisgICBiZWNhdXNlIGl0IGhhcyBmZXdlciBkZXBlbmRlbmNp ZXMgYW5kIHRodXMgaGFzIGxlc3NlciBjb3N0LiAgKi8KKworI2luY2x1ZGUgInZlYy1pbml0LTIy LmgiCisKKy8qIHsgZGctZmluYWwgeyBzY2FuLWFzc2VtYmxlci10aW1lcyB7XHRmbW92XHRkWzAt OV0rLCB4WzAtOV0rfSAyIH0gfSAqLworLyogeyBkZy1maW5hbCB7IHNjYW4tYXNzZW1ibGVyLXRp bWVzIHtcdGluc1x0dlswLTldK1wuaFxbWzEtM11cXSwgd1swLTldK30gNiB9IH0gKi8KKy8qIHsg ZGctZmluYWwgeyBzY2FuLWFzc2VtYmxlciB7XHR6aXAxXHR2WzAtOV0rXC44aCwgdlswLTldK1wu OGgsIHZbMC05XStcLjhofSB9IH0gKi8KZGlmZiAtLWdpdCBhL2djYy90ZXN0c3VpdGUvZ2NjLnRh cmdldC9hYXJjaDY0L3ZlYy1pbml0LTIyLmggYi9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYWFy Y2g2NC92ZWMtaW5pdC0yMi5oCm5ldyBmaWxlIG1vZGUgMTAwNjQ0CmluZGV4IDAwMDAwMDAwMDAw Li4xNWI4ODlkNDA5NwotLS0gL2Rldi9udWxsCisrKyBiL2djYy90ZXN0c3VpdGUvZ2NjLnRhcmdl dC9hYXJjaDY0L3ZlYy1pbml0LTIyLmgKQEAgLTAsMCArMSw3IEBACisjaW5jbHVkZSA8YXJtX25l b24uaD4KKworaW50MTZ4OF90IGZfczE2IChpbnQxNl90IHgwLCBpbnQxNl90IHgxLCBpbnQxNl90 IHgyLCBpbnQxNl90IHgzLAorICAgICAgICAgICAgICAgICBpbnQxNl90IHg0LCBpbnQxNl90IHg1 LCBpbnQxNl90IHg2LCBpbnQxNl90IHg3KQoreworICByZXR1cm4gKGludDE2eDhfdCkgeyB4MCwg eDEsIHgyLCB4MywgeDQsIHg1LCB4NiwgeDcgfTsKK30K --0000000000000cfb8a05fadcbf9e--