From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by sourceware.org (Postfix) with ESMTPS id 3FC843858C53 for ; Thu, 19 Jan 2023 07:19:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3FC843858C53 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-wm1-x330.google.com with SMTP id l41-20020a05600c1d2900b003daf986faaeso555348wms.3 for ; Wed, 18 Jan 2023 23:19:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=to:subject:message-id:date:from:in-reply-to:references:mime-version :from:to:cc:subject:date:message-id:reply-to; bh=oAz+2M+sqVNJqFWePJ3009co3MziacZHpsSZqGijtgg=; b=tSEcm4WsKMMYDWic1KOYGluj382ovWhSy6j53JoDm9ikbQZUW/KuSbzCLEEcO/kVbV fcZewciT9Z/pVYP3x1MBWeRDy2Dud7y9K7I9G9IEFLJWV3KfniP7Ja13Bykk9qHAZvKX bJfUVYJy6jbz3uoIYNCs3y52nTfIhsBP0DM2suOZmgScyCrV44dgDr96JBuSlZAYuQvB +uD/0mTCtlF1GAGgrwoSaykPs7vjt31GUJYVK72Y9vclW4AW8QqhMFt11Z/J/OPbIim+ 6Cd7nKf96K3dGLjlkuV9MwS3XFU8Cqzy45ENpTCn+jAP42v4Z2e4jysdod0jkX84oe6U lSyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=to:subject:message-id:date:from:in-reply-to:references:mime-version :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=oAz+2M+sqVNJqFWePJ3009co3MziacZHpsSZqGijtgg=; b=Gd0hDkD5iYBc15BTCDW8U8qk3jY93qlYWF0PeJvuQWSgontb8HvH6ao49gdtCh+efe MiL1+8l+zL8hIRTxHfltS5Q+qxbA/VsxKx8jo0zeLu6Etq6BEAAVcVAf+Av6CtIVbbnO cZvucO29tshT6WGHPf6cKDeUVk8INa4CtTg3aeeqODSWCdDrt/Ww7z/7YTXGwKEpcxQW x81dt71XW+Dgp60jgJ0wVlfBCx3LeIo0cy/vPBhtaEN+HbAf5AlG68WhY348QYNcbkf/ 77de8KeHwugpkPkcj/wYaMbCo9SbhYK7Ky3SpjOqYW6QEAvUHWyeNyO/OmBH3GD46sZr i3uQ== X-Gm-Message-State: AFqh2ko6zrj+ylrTvjIyLpI6kjoKihSX/Kg4ITX3F0JPTdA+6dnL5vGw /gDnF+KxUMBwUUxqgGSFkJkEpvVjpkj2oMzkqdba8Q== X-Google-Smtp-Source: AMrXdXsiLwexEXqcFBaDD4KoQS2RcEWZmoFJPXOoWI/pdxYB+VAilic96Vo35D4DIdbtoJJfr0mAWDAoxtR7ATPZRH0= X-Received: by 2002:a05:600c:3ac9:b0:3db:1ed:6388 with SMTP id d9-20020a05600c3ac900b003db01ed6388mr16844wms.36.1674112753044; Wed, 18 Jan 2023 23:19:13 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Prathamesh Kulkarni Date: Thu, 19 Jan 2023 12:48:36 +0530 Message-ID: Subject: Re: [aarch64] Use exact_log2 (INTVAL (operands[2])) >= 0 to gate for vec_merge patterns. To: Prathamesh Kulkarni , gcc Patches , richard.sandiford@arm.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, 18 Jan 2023 at 20:00, Richard Sandiford wrote: > > Prathamesh Kulkarni writes: > > Hi Richard, > > Based on your suggestion in the other thread, the patch uses > > exact_log2 (INTVAL (operands[2])) >= 0 to gate for vec_merge patterns. > > Bootstrap+test in progress on aarch64-linux-gnu. > > Does it look OK ? > > Yeah, this is OK, thanks. IMO it's a latent bug and suitable for stage 4. Thanks, pushed in 22c75b4ed94bd731cb6e37c507de1d91954a17cf. Thanks, Prathamesh > > Richard > > > > > Thanks, > > Prathamesh > > > > [aarch64] Use exact_log2 (INTVAL (operands[2])) >= 0 to gate for vec_merge patterns. > > > > gcc/ChangeLog: > > * gcc/config/aarch64-simd.md (aarch64_simd_vec_set): Use > > exact_log2 (INTVAL (operands[2])) >= 0 as condition for gating > > the pattern. > > (aarch64_simd_vec_copy_lane): Likewise. > > (aarch64_simd_vec_copy_lane_): Likewise. > > > > diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md > > index 104088f67d2..7cc8c00f0ec 100644 > > --- a/gcc/config/aarch64/aarch64-simd.md > > +++ b/gcc/config/aarch64/aarch64-simd.md > > @@ -1064,7 +1064,7 @@ > > (match_operand: 1 "aarch64_simd_nonimmediate_operand" "w,?r,Utv")) > > (match_operand:VALL_F16 3 "register_operand" "0,0,0") > > (match_operand:SI 2 "immediate_operand" "i,i,i")))] > > - "TARGET_SIMD" > > + "TARGET_SIMD && exact_log2 (INTVAL (operands[2])) >= 0" > > { > > int elt = ENDIAN_LANE_N (, exact_log2 (INTVAL (operands[2]))); > > operands[2] = GEN_INT ((HOST_WIDE_INT) 1 << elt); > > @@ -1093,7 +1093,7 @@ > > [(match_operand:SI 4 "immediate_operand" "i")]))) > > (match_operand:VALL_F16 1 "register_operand" "0") > > (match_operand:SI 2 "immediate_operand" "i")))] > > - "TARGET_SIMD" > > + "TARGET_SIMD && exact_log2 (INTVAL (operands[2])) >= 0" > > { > > int elt = ENDIAN_LANE_N (, exact_log2 (INTVAL (operands[2]))); > > operands[2] = GEN_INT (HOST_WIDE_INT_1 << elt); > > @@ -1114,7 +1114,7 @@ > > [(match_operand:SI 4 "immediate_operand" "i")]))) > > (match_operand:VALL_F16_NO_V2Q 1 "register_operand" "0") > > (match_operand:SI 2 "immediate_operand" "i")))] > > - "TARGET_SIMD" > > + "TARGET_SIMD && exact_log2 (INTVAL (operands[2])) >= 0" > > { > > int elt = ENDIAN_LANE_N (, exact_log2 (INTVAL (operands[2]))); > > operands[2] = GEN_INT (HOST_WIDE_INT_1 << elt);