From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by sourceware.org (Postfix) with ESMTPS id CACF63858012 for ; Tue, 9 Aug 2022 10:10:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CACF63858012 Received: by mail-ed1-x52e.google.com with SMTP id z22so14471443edd.6 for ; Tue, 09 Aug 2022 03:10:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=ZNKr+wb7QLjBHSPnl0atploorGxX9AVsdlHkrUUeF4g=; b=CUorM5pQEzIcezxDs1VeG+n0PI9q9rPkqGI9hEcesSXkJLRGAPsTZUBXWUkswbXXjX 2t+4RakZCYTUQkCE2Wmqx0NxOfDH8lU2OZFp6U4FIQaDn8g7qs5ezjIazswTVWKGgtG0 lJ4fxTL/NYwQsRVGO3gBFhrlngbcgtHxslXBuOVtRhDDSjA/NxR/hIMjN1v1tMG4equX gE2+1A/YUqV7YR9XUQvoqqAvLiqtiMRkGyRId1BEO8+l7NV49X8i5rTh/kQw5JG/76Qf cOdjzi2E9blP1wA+pKs6Q/mYBVven/cmf8qCFuIoFnQuw5Bz03NxlpOpZmy8Bi0SioDb +/yg== X-Gm-Message-State: ACgBeo2TUVCGLrhpiN5emHHr3DV9KY31BJjllQa7W1rxLrQk28aLN402 eXcpdXQKyES3s7PjzwviXMKsATcj8qCnCASAwDvMCg== X-Google-Smtp-Source: AA6agR79M/eiJ5EfWnK5yy0LUxE3nzxUTkmP4aCldCU5nBEQEj5dp+1yNb2OZO134QeaENhlnLuXGdvF3NpcHjyE3nM= X-Received: by 2002:aa7:db44:0:b0:43d:267c:edd9 with SMTP id n4-20020aa7db44000000b0043d267cedd9mr21449276edt.385.1660039805900; Tue, 09 Aug 2022 03:10:05 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Prathamesh Kulkarni Date: Tue, 9 Aug 2022 15:39:31 +0530 Message-ID: Subject: Re: ICE after folding svld1rq to vec_perm_expr duing forwprop To: Richard Biener Cc: gcc Patches , Richard Sandiford Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-3.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 09 Aug 2022 10:10:13 -0000 On Mon, 8 Aug 2022 at 14:27, Richard Biener wr= ote: > > On Mon, Aug 1, 2022 at 5:17 AM Prathamesh Kulkarni > wrote: > > > > On Thu, 21 Jul 2022 at 12:21, Richard Biener wrote: > > > > > > On Wed, Jul 20, 2022 at 5:36 PM Prathamesh Kulkarni > > > wrote: > > > > > > > > On Mon, 18 Jul 2022 at 11:57, Richard Biener wrote: > > > > > > > > > > On Fri, Jul 15, 2022 at 3:49 PM Prathamesh Kulkarni > > > > > wrote: > > > > > > > > > > > > On Thu, 14 Jul 2022 at 17:22, Richard Sandiford > > > > > > wrote: > > > > > > > > > > > > > > Richard Biener writes: > > > > > > > > On Thu, Jul 14, 2022 at 9:55 AM Prathamesh Kulkarni > > > > > > > > wrote: > > > > > > > >> > > > > > > > >> On Wed, 13 Jul 2022 at 12:22, Richard Biener wrote: > > > > > > > >> > > > > > > > > >> > On Tue, Jul 12, 2022 at 9:12 PM Prathamesh Kulkarni via = Gcc-patches > > > > > > > >> > wrote: > > > > > > > >> > > > > > > > > > >> > > Hi Richard, > > > > > > > >> > > For the following test: > > > > > > > >> > > > > > > > > > >> > > svint32_t f2(int a, int b, int c, int d) > > > > > > > >> > > { > > > > > > > >> > > int32x4_t v =3D (int32x4_t) {a, b, c, d}; > > > > > > > >> > > return svld1rq_s32 (svptrue_b8 (), &v[0]); > > > > > > > >> > > } > > > > > > > >> > > > > > > > > > >> > > The compiler emits following ICE with -O3 -mcpu=3Dgene= ric+sve: > > > > > > > >> > > foo.c: In function =E2=80=98f2=E2=80=99: > > > > > > > >> > > foo.c:4:11: error: non-trivial conversion in =E2=80=98= view_convert_expr=E2=80=99 > > > > > > > >> > > 4 | svint32_t f2(int a, int b, int c, int d) > > > > > > > >> > > | ^~ > > > > > > > >> > > svint32_t > > > > > > > >> > > __Int32x4_t > > > > > > > >> > > _7 =3D VIEW_CONVERT_EXPR<__Int32x4_t>(_8); > > > > > > > >> > > during GIMPLE pass: forwprop > > > > > > > >> > > dump file: foo.c.109t.forwprop2 > > > > > > > >> > > foo.c:4:11: internal compiler error: verify_gimple fai= led > > > > > > > >> > > 0xfda04a verify_gimple_in_cfg(function*, bool) > > > > > > > >> > > ../../gcc/gcc/tree-cfg.cc:5568 > > > > > > > >> > > 0xe9371f execute_function_todo > > > > > > > >> > > ../../gcc/gcc/passes.cc:2091 > > > > > > > >> > > 0xe93ccb execute_todo > > > > > > > >> > > ../../gcc/gcc/passes.cc:2145 > > > > > > > >> > > > > > > > > > >> > > This happens because, after folding svld1rq_s32 to vec= _perm_expr, we have: > > > > > > > >> > > int32x4_t v; > > > > > > > >> > > __Int32x4_t _1; > > > > > > > >> > > svint32_t _9; > > > > > > > >> > > vector(4) int _11; > > > > > > > >> > > > > > > > > > >> > > : > > > > > > > >> > > _1 =3D {a_3(D), b_4(D), c_5(D), d_6(D)}; > > > > > > > >> > > v_12 =3D _1; > > > > > > > >> > > _11 =3D v_12; > > > > > > > >> > > _9 =3D VEC_PERM_EXPR <_11, _11, { 0, 1, 2, 3, ... }>= ; > > > > > > > >> > > return _9; > > > > > > > >> > > > > > > > > > >> > > During forwprop, simplify_permutation simplifies vec_p= erm_expr to > > > > > > > >> > > view_convert_expr, > > > > > > > >> > > and the end result becomes: > > > > > > > >> > > svint32_t _7; > > > > > > > >> > > __Int32x4_t _8; > > > > > > > >> > > > > > > > > > >> > > ;; basic block 2, loop depth 0 > > > > > > > >> > > ;; pred: ENTRY > > > > > > > >> > > _8 =3D {a_2(D), b_3(D), c_4(D), d_5(D)}; > > > > > > > >> > > _7 =3D VIEW_CONVERT_EXPR<__Int32x4_t>(_8); > > > > > > > >> > > return _7; > > > > > > > >> > > ;; succ: EXIT > > > > > > > >> > > > > > > > > > >> > > which causes the error duing verify_gimple since VIEW_= CONVERT_EXPR > > > > > > > >> > > has incompatible types (svint32_t, int32x4_t). > > > > > > > >> > > > > > > > > > >> > > The attached patch disables simplification of VEC_PERM= _EXPR > > > > > > > >> > > in simplify_permutation, if lhs and rhs have non compa= tible types, > > > > > > > >> > > which resolves ICE, but am not sure if it's the correc= t approach ? > > > > > > > >> > > > > > > > > >> > It for sure papers over the issue. I think the error ha= ppens earlier, > > > > > > > >> > the V_C_E should have been built with the type of the VE= C_PERM_EXPR > > > > > > > >> > which is the type of the LHS. But then you probably run= into the > > > > > > > >> > different sizes ICE (VLA vs constant size). I think for= this case you > > > > > > > >> > want a BIT_FIELD_REF instead of a VIEW_CONVERT_EXPR, > > > > > > > >> > selecting the "low" part of the VLA vector. > > > > > > > >> Hi Richard, > > > > > > > >> Sorry I don't quite follow. In this case, we use VEC_PERM_= EXPR to > > > > > > > >> represent dup operation > > > > > > > >> from fixed width to VLA vector. I am not sure how folding = it to > > > > > > > >> BIT_FIELD_REF will work. > > > > > > > >> Could you please elaborate ? > > > > > > > >> > > > > > > > >> Also, the issue doesn't seem restricted to this case. > > > > > > > >> The following test case also ICE's during forwprop: > > > > > > > >> svint32_t foo() > > > > > > > >> { > > > > > > > >> int32x4_t v =3D (int32x4_t) {1, 2, 3, 4}; > > > > > > > >> svint32_t v2 =3D svld1rq_s32 (svptrue_b8 (), &v[0]); > > > > > > > >> return v2; > > > > > > > >> } > > > > > > > >> > > > > > > > >> foo2.c: In function =E2=80=98foo=E2=80=99: > > > > > > > >> foo2.c:9:1: error: non-trivial conversion in =E2=80=98vect= or_cst=E2=80=99 > > > > > > > >> 9 | } > > > > > > > >> | ^ > > > > > > > >> svint32_t > > > > > > > >> int32x4_t > > > > > > > >> v2_4 =3D { 1, 2, 3, 4 }; > > > > > > > >> > > > > > > > >> because simplify_permutation folds > > > > > > > >> VEC_PERM_EXPR< {1, 2, 3, 4}, {1, 2, 3, 4}, {0, 1, 2, 3, ..= .} > > > > > > > > >> into: > > > > > > > >> vector_cst {1, 2, 3, 4} > > > > > > > >> > > > > > > > >> and it complains during verify_gimple_assign_single becaus= e we don't > > > > > > > >> support assignment of vector_cst to VLA vector. > > > > > > > >> > > > > > > > >> I guess the issue really is that currently, only VEC_PERM_= EXPR > > > > > > > >> supports lhs and rhs > > > > > > > >> to have vector types with differing lengths, and simplifyi= ng it to > > > > > > > >> other tree codes, like above, > > > > > > > >> will result in type errors ? > > > > > > > > > > > > > > > > That might be the case - Richard should know. > > > > > > > > > > > > > > I don't see anything particularly special about VEC_PERM_EXPR= here, > > > > > > > or about the VLA vs. VLS thing. We would have the same issue= trying > > > > > > > to build a 128-bit vector from 2 64-bit vectors. And there a= re other > > > > > > > tree codes whose input types are/can be different from their = output > > > > > > > types. > > > > > > > > > > > > > > So it just seems like a normal type correctness issue: a VEC_= PERM_EXPR > > > > > > > of type T needs to be replaced by something of type T. Wheth= er T has a > > > > > > > constant size or a variable size doesn't matter. > > > > > > > > > > > > > > > If so your type check > > > > > > > > is still too late, you should instead recognize that we are= permuting > > > > > > > > a VLA vector and then refuse to go any of the non-VEC_PERM = generating > > > > > > > > paths - that probably means just allowing the code =3D=3D V= EC_PERM_EXPR > > > > > > > > case and not any of the CTOR/CST/VIEW_CONVERT_EXPR cases? > > > > > > > > > > > > > > Yeah. If we're talking about the match.pd code, I think only= : > > > > > > > > > > > > > > (if (sel.series_p (0, 1, 0, 1)) > > > > > > > { op0; } > > > > > > > (if (sel.series_p (0, 1, nelts, 1)) > > > > > > > { op1; } > > > > > > > > > > > > > > need a type compatibility check. For fold_vec_perm I think > > > > > > > we should just rearrange: > > > > > > > > > > > > > > gcc_assert (known_eq (TYPE_VECTOR_SUBPARTS (type), nelts) > > > > > > > && known_eq (TYPE_VECTOR_SUBPARTS (TREE_TYPE (a= rg0)), nelts) > > > > > > > && known_eq (TYPE_VECTOR_SUBPARTS (TREE_TYPE (a= rg1)), nelts)); > > > > > > > if (TREE_TYPE (TREE_TYPE (arg0)) !=3D TREE_TYPE (type) > > > > > > > || TREE_TYPE (TREE_TYPE (arg1)) !=3D TREE_TYPE (type)) > > > > > > > return NULL_TREE; > > > > > > > > > > > > > > so that the assert comes after the early-out. > > > > > > > > > > > > > > It would be good at some point to relax fold_vec_perm to case= s where the > > > > > > > outputs are a different length from the inputs, since the all= -constant > > > > > > > VEC_PERM_EXPR above could be folded to a VECTOR_CST. > > > > > > Hi, > > > > > > For the above case, I think the issue is that simplify_permutat= ion > > > > > > uses TREE_TYPE (arg0) for res_type, > > > > > > while it should now use type for lhs. > > > > > > > > > > > > /* Shuffle of a constructor. */ > > > > > > bool ret =3D false; > > > > > > tree res_type =3D TREE_TYPE (arg0); > > > > > > tree opt =3D fold_ternary (VEC_PERM_EXPR, res_type, arg0,= arg1, op2); > > > > > > > > > > > > Using, res_type =3D TREE_TYPE (gimple_get_lhs (stmt)), > > > > > > resolves the ICE, and emits all constant VEC_PERM_EXPR: > > > > > > > > > > > > v2_4 =3D VEC_PERM_EXPR <{ 1, 2, 3, 4 }, { 1, 2, 3, 4 }, { 0, = 1, 2, 3, ... }>; > > > > > > return v2_4; > > > > > > > > > > > > Does the patch look OK to commit after bootstrap+test ? > > > > > > > > > > Ok with using gimple_assign_lhs (stmt) instead of gimple_get_lhs = (stmt). > > > > Hi, > > > > I committed the patch but unfortunately it caused PR106360. > > > > The issue is that for slp-reduc-sad-2.c on ppc64le, > > > > simplify_permutation sees the following during forwprop4: > > > > > > > > _78 =3D (void *) ivtmp.21_73; > > > > _92 =3D MEM [(uint8_t *)_78]; > > > > _91 =3D {_92, 0}; > > > > vect__1.6_90 =3D VIEW_CONVERT_EXPR(_91)= ; > > > > _88 =3D MEM [(uint8_t *)_78 + 16B]; > > > > _87 =3D {_88, 0}; > > > > vect__1.7_86 =3D VIEW_CONVERT_EXPR(_87)= ; > > > > vect__1.8_85 =3D VEC_PERM_EXPR > > > 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23 }>; > > > > > > > > So for, > > > > tree res_type =3D TREE_TYPE (gimple_assign_lhs (stmt)); > > > > tree opt =3D fold_ternary (VEC_PERM_EXPR, res_type, arg0, arg1, op2= ); > > > > > > > > we have: > > > > res_type =3D V16QI > > > > arg0 =3D {_92, 0} > > > > arg1 =3D {_88, 0} > > > > op2 =3D {0, 2} > > > > > > > > and thus we hit the following assert in fold_vec_perm: > > > > > > > > gcc_assert (known_eq (TYPE_VECTOR_SUBPARTS (type), nelts) > > > > && known_eq (TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg0)),= nelts) > > > > && known_eq (TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg1)),= nelts)); > > > > > > > > since nelts =3D=3D 2, and TYPE_VECTOR_SUBPARTS (type) =3D=3D 16. > > > > > > > > If we revert the committed patch so we pass res_type =3D TREE_TYPE = (arg0) instead, > > > > it simplifies the above VEC_PERM_EXPR to VIEW_CONVERT_EXPR: > > > > _92 =3D MEM [(uint8_t *)_78]; > > > > _88 =3D MEM [(uint8_t *)_78 + 16B]; > > > > _5 =3D {_92, _88}; > > > > vect__1.8_85 =3D VIEW_CONVERT_EXPR(_5); > > > > > > > > I suppose it's legal to cast vector of one type to another as long = as > > > > sizes match ? > > > > > > > > IIUC, the above VIEW_CONVERT_EXPR will result in: > > > > vect__1.8_85 =3D { (uint8_t) _92, 0, 0, 0, 0, 0, 0, 0, (uint8_t) _8= 8, 0, > > > > 0, 0, 0, 0, 0, 0 } ? > > > > > > > > In the attached patch, it restores res_type to TREE_TYPE (arg0), an= d checks > > > > if lhs_type and res_type differ but have same size, and in that cas= e emit: > > > > lhs =3D VIEW_CONVERT_EXPR (opt), > > > > instead of: > > > > lhs =3D VIEW_CONVERT_EXPR (opt) > > > > where opt is result of folding VEC_PERM_EXPR > > > > > > > > Does it look OK ? > > > > > > Definitely the original change was bogus. > > > > > > + if (!operand_equal_p (TYPE_SIZE (lhs_type), TYPE_SIZE (res_= type))) > > > + return 0; > > > > > > just repeats your very original change though ... I'll note that > > > fold_ternary will > > > ICE on now valid VEC_PERM_EXPRs so we should fix it, possibly by > > > returning NULL_TREE on cases it does not handle. > > > > > > I think what should be done is, in the > > > > > > /* If there are any VIEW_CONVERT_EXPRs found when finding permu= tation > > > operands source, check whether it's valid to transform and p= repare > > > the required new operands. */ > > > if (code =3D=3D VIEW_CONVERT_EXPR || code2 =3D=3D VIEW_CONVERT_= EXPR) > > > { > > > ... > > > > > > path also transform the expected result type. It should remain V_C_E= compatible > > > to TREE_TYPE (lhs) but get a new element type. > > > > > > But as said, > > > > > > tree > > > fold_vec_perm (tree type, tree arg0, tree arg1, const vec_perm_indice= s &sel) > > > { > > > unsigned int i; > > > unsigned HOST_WIDE_INT nelts; > > > bool need_ctor =3D false; > > > > > > if (!sel.length ().is_constant (&nelts)) > > > return NULL_TREE; > > > gcc_assert (known_eq (TYPE_VECTOR_SUBPARTS (type), nelts) > > > && known_eq (TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg0)), n= elts) > > > && known_eq (TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg1)), n= elts)); > > > > > > ^^^ this doesn't match what we allow for VEC_PERM_EXPRs now and fold_= ternary > > > doesn't guard according to those asserts (I think we should extend fo= ld_vec_perm > > > to support the new constraints). > > Hi Richard, > > Thanks for the suggestions and sorry for late reply. I reverted the cha= nge to > > simplify_permutaton which resolved the ppc64le case ICE. > > > > The attached patch extends fold_vec_perm to handle vectors with > > differing lengths. > > For, > > lhs =3D vec_perm_expr, > > the patch: > > (a) asserts lhs and mask have same vector length. > > (b) asserts arg0 and arg1 have same vector length. > > (c) returns NULL_TREE if element type differs for lhs, arg0 and arg1. > > (d) if len(lhs) > len(arg0), then the patch allows permuting arg0, arg1 > > if the mask has npatterns =3D=3D len(arg0) and nelts_per_pattern =3D=3D= 1. > > The intent is to permute arg0 and arg1, and then to dup elements in res= ult > > to target vector length. > > So for eg: > > vec_perm_expr< {1, 2, 3, 4}, {5, 6, 7, 8}, {0, 4, 1, 5, ...}> > > will result in vla vector {1, 5, 2, 6, ....} with {1, 5, 2, 6} > > replicated thru-out. > > Does it look OK ? > > > > With the patch, we don't ICE for either of the aarch64 tests above. > > For, > > svint32_t f1() > > { > > int32x4_t v =3D {1, 2, 3, 4}; > > return svld1rq_s32 (svptrue_b8 (), &v[0]); > > } > > > > optimized dump shows: > > svint32_t f1 () > > { > > int32x4_t v; > > > > : > > return { 1, 2, 3, 4, ... }; > > > > } > > > > code-gen: > > f1: > > .LFB3900: > > .cfi_startproc > > ptrue p0.b, all > > adrp x0, .LC0 > > add x0, x0, :lo12:.LC0 > > ld1rqw z0.s, p0/z, [x0] > > ret > > .LC0: > > .word 1 > > .word 2 > > .word 3 > > .word 4 > > > > I guess for this particular case, we could use index instead. > > > > For, > > svint32_t f2(int a, int b, int c, int d) > > { > > int32x4_t v =3D {a, b, c, d}; > > return svld1rq_s32 (svptrue_b8 (), &v[0]); > > } > > > > optimized dump shows: > > svint32_t f2 (int a, int b, int c, int d) > > { > > svint32_t _6; > > > > [local count: 1073741824]: > > _6 =3D {a_1(D), b_2(D), c_3(D), d_4(D), ... }; > > return _6; > > > > The code-gen seems pretty bad however: > > f2: > > .LFB3901: > > .cfi_startproc > > addvl sp, sp, #-4 > > .cfi_escape 0xf,0x9,0x8f,0,0x92,0x2e,0,0x8,0x20,0x1e,0x22 > > ptrue p0.b, all > > addvl x4, sp, #3 > > mov z0.b, #0 > > st1w z0.s, p0, [sp, #3, mul vl] > > str w0, [x4] > > addvl x0, sp, #2 > > ld1w z0.s, p0/z, [sp, #3, mul vl] > > st1w z0.s, p0, [sp, #2, mul vl] > > str w1, [x0, 4] > > addvl x0, sp, #1 > > ld1w z0.s, p0/z, [sp, #2, mul vl] > > st1w z0.s, p0, [sp, #1, mul vl] > > str w2, [x0, 8] > > ld1w z0.s, p0/z, [sp, #1, mul vl] > > st1w z0.s, p0, [sp] > > str w3, [sp, 12] > > ld1w z0.s, p0/z, [sp] > > addvl sp, sp, #4 > > .cfi_def_cfa_offset 0 > > ret > > > > I will try to address code-gen issues in follow up patches. > > Bootstrapped+tested on x64_64-linux-gnu and aarch64-linux-gnu. > > > /* If result vector has greater length than input vector, > + then allow permuting two vectors as long as: > + a) sel.nelts_per_pattern =3D=3D 1 > + b) sel.npatterns =3D=3D len of input vector. > + The intent is to permute input vectors, and > + dup the elements in resulting vector to target vector length. */ > + > + if (maybe_gt (TYPE_VECTOR_SUBPARTS (type), > + TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg0)))) > + { > + nelts =3D sel.encoding ().npatterns (); > + if (sel.encoding ().nelts_per_pattern () !=3D 1 > + || (!known_eq (nelts, TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg0))))= ) > + return NULL_TREE; > + } > > so the only case you add is non-VLA to VLA and there > explicitely only the case of a period that's same as the > element count in the input vectors. > > > @@ -2602,6 +2602,9 @@ dump_generic_node (pretty_printer *pp, tree > node, int spc, dump_flags_t flags, > pp_space (pp); > } > } > + if (VECTOR_TYPE_P (TREE_TYPE (node)) > + && !TYPE_VECTOR_SUBPARTS (TREE_TYPE (node)).is_constant ()) > + pp_string (pp, ", ... "); > pp_right_brace (pp); > > btw, I do wonder if VLA CONSTRUCTORs are a "thing"? Are they? Well, it got created for the following case after folding: svint32_t f2(int a, int b, int c, int d) { int32x4_t v =3D {a, b, c, d}; return svld1rq_s32 (svptrue_b8 (), &v[0]); } The svld1rq_s32 call gets folded to: v =3D {a, b, c, d} lhs =3D VEC_PERM_EXPR fold_vec_perm then folds the above VEC_PERM_EXPR to VLA constructor, since elements in v (in_elts) are not constant, and need_ctor is thus true: lhs =3D {a, b, c, d, ...} I added "..." to make it more explicit that it's a VLA constructor. > > I had hoped that you would make > > tree *in_elts =3D XALLOCAVEC (tree, nelts * 2); > if (!vec_cst_ctor_to_array (arg0, nelts, in_elts) > || !vec_cst_ctor_to_array (arg1, nelts, in_elts + nelts)) > return NULL_TREE; > > VLA agnostic, thus support for example permuting > { 0, 2, 4, 8, ... }, { 1, 3, 5, 7 ... }, { 0, 4, 1, 5 ... } > as { 0, 1, 2, 3, ... }, etc. > > that should be entirely doable, to somebody familiar with VLA and the API= s > even more so. Thanks, I will work on adding this case. Thanks, Prathamesh > > Richard. > > > Thanks, > > Prathamesh > > > > > > > > Richard. > > > > > > > Thanks, > > > > Prathamesh > > > > > > > > > > > > > > > I will try to address the folding for above VEC_PERM_EXPR in fo= llow-up patch. > > > > > > > > > > > > Thanks, > > > > > > Prathamesh > > > > > > > > > > > > > > Thanks, > > > > > > > Richard