From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by sourceware.org (Postfix) with ESMTPS id 35C7238582A1 for ; Tue, 18 Jul 2023 10:54:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 35C7238582A1 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-3fbef8ad9bbso55281555e9.0 for ; Tue, 18 Jul 2023 03:54:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689677668; x=1692269668; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=ZCchHh15WXL/rYZ9tYu/eeOuUsum6V7RWfdjCCpByqY=; b=Q9NEkfiOCKmkJpvWN/3lEv/KkHVWrOynP7Q4+Byg6VQbWdSaBWyowm+OkFspvIoLXA buW1HtIUOaRzECdHUSjudNjTCkJBd21nm/s2So5Lm52Z6r8K6Bh9WANbpZ4LHwzSA5Ym b/dF5K+7r+czt94FmYY4UYy2iSlsfH3QiQhdHC67DPQAEYuSeOSrFBIP7aROPcTwSlZu csLPUQUCPzbRdlTFmYOEDcHoBb+3+qpmuhWVsz1PWlp8rewxgW1sDo8RPWsbJd873DK3 3z17tCL7OUMO/ZFDaq6hZpXLYtWxHfOpSrIqeDuB9LA41s9snVVTZZVqWn78Ms9H9VDZ PJeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689677668; x=1692269668; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=ZCchHh15WXL/rYZ9tYu/eeOuUsum6V7RWfdjCCpByqY=; b=i7dIdm1REOcUeZTuAd4KAVWlq8c5q19Y9gIchgUPUu/6ls3RGofJTzC36Q1o9SzvhR e41J8TzmJZwTpRdWcuhRcCdQBp7vs9Y7CTD9M1X4DmL/vsmcXP50USjSSiYmAWLkyzvq xE3uDcAcJgWCgqNel4+bJR3691gIfGDFberjFGlYwy5Z2Wq0ImOapEiG87+fvDuHe2jo fUlzPawZ2z2/ZkwIzE/opNjqZgjmZrIOorG6mO+JajLWt1xIbwWoYXlvbURzKoHP4DZV iHuGc3S375D/1B+qxmcsH5jrK5/JnBRRWYi2jjyDVOQJUrg3WBsJ0TZlXBaGwAKP8CEA y+tA== X-Gm-Message-State: ABy/qLYXgYlGCGThkMnC6jgDaelA9FaAdixM5jSEpVdQUyiiN8ReKysG a19T1hZ70mcP/vGf4gh4L9TQtM61X9hA0buWI5qhhA== X-Google-Smtp-Source: APBJJlGh2aiCdaQPTYRSHiNup2p5Tyl361tW41jhow8piEKF4ejoP9AhI6K7PkMQVqbUWasz9EFl4e5GWFcihs+GV04= X-Received: by 2002:a05:6000:12c7:b0:315:94ea:31ad with SMTP id l7-20020a05600012c700b0031594ea31admr12736380wrx.66.1689677668685; Tue, 18 Jul 2023 03:54:28 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Prathamesh Kulkarni Date: Tue, 18 Jul 2023 16:23:53 +0530 Message-ID: Subject: Re: [PATCH] aarch64: remove useless pairs of rev instructions To: Serval Martinot-Lagarde Cc: "gcc-patches@gcc.gnu.org" , Etienne Renault Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_ASCII_DIVIDERS,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, 18 Jul 2023 at 15:20, Serval Martinot-Lagarde via Gcc-patches wrote: > > SVE generates superflous rev instructions that can be replaced > by single mov instruction or a pair of (rev, mov) instructions Hi Serval, I had added a similar transform to remove pair of rev instructions in: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=f0eabc52c9a2d3da0bfc201da7a5c1658b76e9a4 which seems to be removing the superfluous VEC_PERM_EXPR for your test: For example, following pair of VEC_PERM_EXPR is input to forwprop4: vect__4.9_58 = VEC_PERM_EXPR ; vect__4.12_63 = VEC_PERM_EXPR ; and forwprop4 dump shows: Removing dead stmt vect__4.12_63 = vect__4.8_57; Which shows that forwprop replaced the VEC_PERM_EXPR pair with assignment vect__4.12_63 = vect__4.8_57 (which turned out to be eventually dead). Sorry if this sounds silly to ask but could you let me know how to reproduce this issue on trunk ? I tried using -O3 -mcpu=generic+sve for your test but grepping for rev didn't return any results in code-gen. Thanks, Prathamesh > > gcc/ > * config/aarch64/aarch64-sve.md: New peephole2. > * testsuite/gcc.target/aarch64/sve/revrev.c: New dg test. > > Signed-off-by: Serval Martinot-Lagarde > --- > gcc/config/aarch64/aarch64-sve.md | 21 +++++++++++++++++++ > gcc/testsuite/gcc.target/aarch64/sve/revrev.c | 13 ++++++++++++ > 2 files changed, 34 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/revrev.c > > diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md > index da5534c3e32..e5e0c7ddfc5 100644 > --- a/gcc/config/aarch64/aarch64-sve.md > +++ b/gcc/config/aarch64/aarch64-sve.md > @@ -8836,6 +8836,27 @@ > "TARGET_SVE" > "rev\t%0., %1.") > > +(define_peephole2 > + [(set (match_operand:SVE_ALL 0 "register_operand" "") > + (unspec:SVE_ALL > + [(match_operand:SVE_ALL 1 "register_operand" "")] UNSPEC_REV)) > + (set (match_operand:SVE_ALL 2 "register_operand" "") > + (unspec:SVE_ALL > + [(match_dup 0)] UNSPEC_REV))] > + "TARGET_SVE" > + [(const_int 0)] > + { > + if (REGNO (operands[2]) != REGNO (operands[0])) > + { > + emit_insn (gen_rtx_SET (operands[2], operands[1])); > + rtx rev = gen_rtx_UNSPEC (mode, gen_rtvec (1, operands[1]), UNSPEC_REV); > + emit_insn (gen_rtx_SET (operands[0], rev)); > + } > + else > + emit_insn (gen_rtx_SET (operands[0], operands[1])); > + DONE; > + }) > + > ;; ------------------------------------------------------------------------- > ;; ---- [INT,FP] Special-purpose binary permutes > ;; ------------------------------------------------------------------------- > diff --git a/gcc/testsuite/gcc.target/aarch64/sve/revrev.c b/gcc/testsuite/gcc.target/aarch64/sve/revrev.c > new file mode 100644 > index 00000000000..04af6eed291 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/sve/revrev.c > @@ -0,0 +1,13 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O3" } */ > + > +#include > + > +void > +test (uint8_t a[], uint8_t b[], uint64_t N) > +{ > + for (uint64_t i = N; i > 0; i--) > + a[i - 1] = b[i - 1]; > +} > + > +/* { dg-final { scan-assembler-not {\trev\t(z[0-9]+\.h), \1\n\trev\t\1, \1\n} } } */ > -- > 2.21.0