From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by sourceware.org (Postfix) with ESMTPS id 5F6843858D1E for ; Tue, 2 May 2023 12:39:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5F6843858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-2f6401ce8f8so2275129f8f.3 for ; Tue, 02 May 2023 05:39:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683031145; x=1685623145; h=to:subject:message-id:date:from:in-reply-to:references:mime-version :from:to:cc:subject:date:message-id:reply-to; bh=MrwpJnBUy58RZiEw8KnV/g3JpUqV0Lc9m6sHqzLkHdA=; b=a8UDtQDvFNUaeCiFGs2CLkgK5rQ5RMDIhMMQGmvUIiW3JXy3CKr5zzRgAn9uFirDrd kivbozKLux9cB1rgbSyXQ9h1rmdi4TJZFMpZjNlmiNllZuCT3jlznPrPqGHdUao7xAys lKg7oMG2UFd5mbS5q1w9+8MCEnpZBWhIUcKxV96cSxmyadYnmQ9zSTEqOCFSksHSFiH0 3EeyfEAFhuydi1PfrVYOY9O+Ftn36m43vublb8ZmCKgNUsB6i1Ktn5tKJ9j73vDH3p91 1OAruoums9tdmDgFteENFR93Rh6dvCn8j6OWG8NxioqXJ/AocoGRq5CcQEfB5j2tEWcS Zfgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683031145; x=1685623145; h=to:subject:message-id:date:from:in-reply-to:references:mime-version :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=MrwpJnBUy58RZiEw8KnV/g3JpUqV0Lc9m6sHqzLkHdA=; b=J95wU0lh6JMfxzatmeFd1CpMbIL8ehKzR42VIBwt2C2sofBfYmIssihDZBhN+IzsAV 04AjKfMGDPJfqWihLGKlXzJysWvqWFIWbcBfH0g5qySn1j7FvRv2LL7OIe4+5KfJLOYf SHturDafBX7FW+BYu2TeEGX6XbRuNq8EASFEQDUkZR9U6F8Z2NC/4m/6ObL/N5qsH4L4 MrGIbtpAoF/J5uW7VAZ+KqVUBXHD/LXJsvJ4gh8ygibdnvkOGWt8NPXJymNwOfDpGus4 GwhZNBIUyxb5IJlmX+aMxuuNsgOgCQupfZbHV58Zk1adGxaS0GxHXDL5GfGkt8SBlSmx ejqA== X-Gm-Message-State: AC+VfDylnJ1hAt7bZijZCFpkyh0Ci7jfXRF6GqKgcABSW/iKI/EMPd2X KOW7RU7zYKwL2rReGtKZLzewHpuTBfKSKG+03wPr4roAxUgzyCFQ X-Google-Smtp-Source: ACHHUZ7whRlyU3zsVZBrVGtuHrkp2+4+MYpmqx7lDxJuf228iSJxspLlHAazTxltPvquTpguRd/xSceAMNTyvj5HGIE= X-Received: by 2002:adf:e647:0:b0:306:3153:d2fe with SMTP id b7-20020adfe647000000b003063153d2femr3153690wrn.27.1683031144818; Tue, 02 May 2023 05:39:04 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Prathamesh Kulkarni Date: Tue, 2 May 2023 18:08:27 +0530 Message-ID: Subject: Re: [aarch64] Code-gen for vector initialization involving constants To: Prathamesh Kulkarni , gcc Patches , richard.sandiford@arm.com Content-Type: multipart/mixed; boundary="0000000000008894d605fab5395a" X-Spam-Status: No, score=-9.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --0000000000008894d605fab5395a Content-Type: text/plain; charset="UTF-8" On Tue, 2 May 2023 at 17:32, Richard Sandiford wrote: > > Prathamesh Kulkarni writes: > > On Tue, 2 May 2023 at 14:56, Richard Sandiford > > wrote: > >> > [aarch64] Improve code-gen for vector initialization with single constant element. > >> > > >> > gcc/ChangeLog: > >> > * config/aarch64/aarc64.cc (aarch64_expand_vector_init): Tweak condition > >> > if (n_var == n_elts && n_elts <= 16) to allow a single constant, > >> > and if maxv == 1, use constant element for duplicating into register. > >> > > >> > gcc/testsuite/ChangeLog: > >> > * gcc.target/aarch64/vec-init-single-const.c: New test. > >> > > >> > diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc > >> > index 2b0de7ca038..f46750133a6 100644 > >> > --- a/gcc/config/aarch64/aarch64.cc > >> > +++ b/gcc/config/aarch64/aarch64.cc > >> > @@ -22167,7 +22167,7 @@ aarch64_expand_vector_init (rtx target, rtx vals) > >> > and matches[X][1] with the count of duplicate elements (if X is the > >> > earliest element which has duplicates). */ > >> > > >> > - if (n_var == n_elts && n_elts <= 16) > >> > + if ((n_var >= n_elts - 1) && n_elts <= 16) > >> > { > >> > int matches[16][2] = {0}; > >> > for (int i = 0; i < n_elts; i++) > >> > @@ -22227,6 +22227,18 @@ aarch64_expand_vector_init (rtx target, rtx vals) > >> > vector register. For big-endian we want that position to hold > >> > the last element of VALS. */ > >> > maxelement = BYTES_BIG_ENDIAN ? n_elts - 1 : 0; > >> > + > >> > + /* If we have a single constant element, use that for duplicating > >> > + instead. */ > >> > + if (n_var == n_elts - 1) > >> > + for (int i = 0; i < n_elts; i++) > >> > + if (CONST_INT_P (XVECEXP (vals, 0, i)) > >> > + || CONST_DOUBLE_P (XVECEXP (vals, 0, i))) > >> > + { > >> > + maxelement = i; > >> > + break; > >> > + } > >> > + > >> > rtx x = force_reg (inner_mode, XVECEXP (vals, 0, maxelement)); > >> > aarch64_emit_move (target, lowpart_subreg (mode, x, inner_mode)); > >> > >> We don't want to force the constant into a register though. > > OK right, sorry. > > With the attached patch, for the following test-case: > > int64x2_t f_s64(int64_t x) > > { > > return (int64x2_t) { x, 1 }; > > } > > > > it loads constant from memory (same code-gen as without patch). > > f_s64: > > adrp x1, .LC0 > > ldr q0, [x1, #:lo12:.LC0] > > ins v0.d[0], x0 > > ret > > > > Does the patch look OK ? > > > > Thanks, > > Prathamesh > > [...] > > [aarch64] Improve code-gen for vector initialization with single constant element. > > > > gcc/ChangeLog: > > * config/aarch64/aarc64.cc (aarch64_expand_vector_init): Tweak condition > > if (n_var == n_elts && n_elts <= 16) to allow a single constant, > > and if maxv == 1, use constant element for duplicating into register. > > > > gcc/testsuite/ChangeLog: > > * gcc.target/aarch64/vec-init-single-const.c: New test. > > > > diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc > > index 2b0de7ca038..97309ddec4f 100644 > > --- a/gcc/config/aarch64/aarch64.cc > > +++ b/gcc/config/aarch64/aarch64.cc > > @@ -22167,7 +22167,7 @@ aarch64_expand_vector_init (rtx target, rtx vals) > > and matches[X][1] with the count of duplicate elements (if X is the > > earliest element which has duplicates). */ > > > > - if (n_var == n_elts && n_elts <= 16) > > + if ((n_var >= n_elts - 1) && n_elts <= 16) > > No need for the extra brackets. Adjusted, thanks. Sorry if this sounds like a silly question, but why do we need the n_elts <= 16 check ? Won't n_elts be always <= 16 since max number of elements in a vector would be 16 for V16QI ? > > > { > > int matches[16][2] = {0}; > > for (int i = 0; i < n_elts; i++) > > @@ -22227,8 +22227,26 @@ aarch64_expand_vector_init (rtx target, rtx vals) > > vector register. For big-endian we want that position to hold > > the last element of VALS. */ > > maxelement = BYTES_BIG_ENDIAN ? n_elts - 1 : 0; > > - rtx x = force_reg (inner_mode, XVECEXP (vals, 0, maxelement)); > > - aarch64_emit_move (target, lowpart_subreg (mode, x, inner_mode)); > > + > > + /* If we have a single constant element, use that for duplicating > > + instead. */ > > + if (n_var == n_elts - 1) > > + for (int i = 0; i < n_elts; i++) > > + if (CONST_INT_P (XVECEXP (vals, 0, i)) > > + || CONST_DOUBLE_P (XVECEXP (vals, 0, i))) > > + { > > + maxelement = i; > > + break; > > + } > > + > > + rtx maxval = XVECEXP (vals, 0, maxelement); > > + if (!(CONST_INT_P (maxval) || CONST_DOUBLE_P (maxval))) > > + { > > + rtx x = force_reg (inner_mode, XVECEXP (vals, 0, maxelement)); > > + aarch64_emit_move (target, lowpart_subreg (mode, x, inner_mode)); > > + } > > + else > > + aarch64_emit_move (target, gen_vec_duplicate (mode, maxval)); > > } > > else > > { > > This seems a bit convoluted. It might be easier to record whether > we see a CONST_INT_P or a CONST_DOUBLE_P during the previous loop, > and if so what the constant is. Then handle that case first, > as a separate arm of the "if". Adjusted in the attached patch. Does it look OK ? > > > diff --git a/gcc/testsuite/gcc.target/aarch64/vec-init-single-const.c b/gcc/testsuite/gcc.target/aarch64/vec-init-single-const.c > > new file mode 100644 > > index 00000000000..682fd43439a > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/aarch64/vec-init-single-const.c > > @@ -0,0 +1,66 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-O2" } */ > > +/* { dg-final { check-function-bodies "**" "" "" } } */ > > + > > +#include > > + > > +/* > > +** f_s8: > > +** ... > > +** dup v[0-9]+\.16b, w[0-9]+ > > +** movi v[0-9]+\.8b, 0x1 > > +** ins v[0-9]+\.b\[15\], v[0-9]+\.b\[0\] > > +** ... > > +** ret > > Like with the divide-and-conquer patch, there's nothing that requires > the first two instructions to be in that order. Hmm, will it be OK to disable scheduling by passing -fno-schedule-insns -fno-schedule-insns2 for the test ? > > What is the second ... hiding? What sequences do we actually generate? Sorry, added them by mistake. They were the exact sequences. Adjusted tests in the patch. > > BTW, remember to say how patches were tested :-) Right, sorry. The patch is under bootstrap+test on aarch64-linux-gnu. OK to commit if passes ? Thanks, Prathamesh > > Thanks, > Richard > > > +*/ > > + > > +int8x16_t f_s8(int8_t x) > > +{ > > + return (int8x16_t) { x, x, x, x, x, x, x, x, > > + x, x, x, x, x, x, x, 1 }; > > +} > > + > > +/* > > +** f_s16: > > +** ... > > +** dup v[0-9]+\.8h, w[0-9]+ > > +** movi v[0-9]+\.4h, 0x1 > > +** ins v[0-9]+\.h\[7\], v[0-9]+\.h\[0\] > > +** ... > > +** ret > > +*/ > > + > > +int16x8_t f_s16(int16_t x) > > +{ > > + return (int16x8_t) { x, x, x, x, x, x, x, 1 }; > > +} > > + > > +/* > > +** f_s32: > > +** ... > > +** movi v[0-9]\.2s, 0x1 > > +** dup v[0-9]\.4s, w[0-9]+ > > +** ins v[0-9]+\.s\[3\], v[0-9]+\.s\[0\] > > +** ... > > +** ret > > +*/ > > + > > +int32x4_t f_s32(int32_t x) > > +{ > > + return (int32x4_t) { x, x, x, 1 }; > > +} > > + > > +/* > > +** f_s64: > > +** ... > > +** adrp x[0-9]+, .LC[0-9]+ > > +** ldr q[0-9]+, \[x[0-9]+, #:lo12:.LC[0-9]+\] > > +** ins v[0-9]+\.d\[0\], x[0-9]+ > > +** ... > > +** ret > > +*/ > > + > > +int64x2_t f_s64(int64_t x) > > +{ > > + return (int64x2_t) { x, 1 }; > > +} --0000000000008894d605fab5395a Content-Type: text/plain; charset="US-ASCII"; name="gnu-780-5.txt" Content-Disposition: attachment; filename="gnu-780-5.txt" Content-Transfer-Encoding: base64 Content-ID: X-Attachment-Id: f_lh693m6m0 W2FhcmNoNjRdIEltcHJvdmUgY29kZS1nZW4gZm9yIHZlY3RvciBpbml0aWFsaXphdGlvbiB3aXRo IHNpbmdsZSBjb25zdGFudCBlbGVtZW50LgoKZ2NjL0NoYW5nZUxvZzoKCSogY29uZmlnL2FhcmNo NjQvYWFyYzY0LmNjIChhYXJjaDY0X2V4cGFuZF92ZWN0b3JfaW5pdCk6IFR3ZWFrIGNvbmRpdGlv bgoJaWYgKG5fdmFyID09IG5fZWx0cyAmJiBuX2VsdHMgPD0gMTYpIHRvIGFsbG93IGEgc2luZ2xl IGNvbnN0YW50LAoJYW5kIGlmIG1heHYgPT0gMSwgdXNlIGNvbnN0YW50IGVsZW1lbnQgZm9yIGR1 cGxpY2F0aW5nIGludG8gcmVnaXN0ZXIuCgpnY2MvdGVzdHN1aXRlL0NoYW5nZUxvZzoKCSogZ2Nj LnRhcmdldC9hYXJjaDY0L3ZlYy1pbml0LXNpbmdsZS1jb25zdC5jOiBOZXcgdGVzdC4KCmRpZmYg LS1naXQgYS9nY2MvY29uZmlnL2FhcmNoNjQvYWFyY2g2NC5jYyBiL2djYy9jb25maWcvYWFyY2g2 NC9hYXJjaDY0LmNjCmluZGV4IDJiMGRlN2NhMDM4Li4zMTMxOTk3N2ZmZCAxMDA2NDQKLS0tIGEv Z2NjL2NvbmZpZy9hYXJjaDY0L2FhcmNoNjQuY2MKKysrIGIvZ2NjL2NvbmZpZy9hYXJjaDY0L2Fh cmNoNjQuY2MKQEAgLTIyMTY3LDcgKzIyMTY3LDcgQEAgYWFyY2g2NF9leHBhbmRfdmVjdG9yX2lu aXQgKHJ0eCB0YXJnZXQsIHJ0eCB2YWxzKQogICAgICBhbmQgbWF0Y2hlc1tYXVsxXSB3aXRoIHRo ZSBjb3VudCBvZiBkdXBsaWNhdGUgZWxlbWVudHMgKGlmIFggaXMgdGhlCiAgICAgIGVhcmxpZXN0 IGVsZW1lbnQgd2hpY2ggaGFzIGR1cGxpY2F0ZXMpLiAgKi8KIAotICBpZiAobl92YXIgPT0gbl9l bHRzICYmIG5fZWx0cyA8PSAxNikKKyAgaWYgKG5fdmFyID49IG5fZWx0cyAtIDEgJiYgbl9lbHRz IDw9IDE2KQogICAgIHsKICAgICAgIGludCBtYXRjaGVzWzE2XVsyXSA9IHswfTsKICAgICAgIGZv ciAoaW50IGkgPSAwOyBpIDwgbl9lbHRzOyBpKyspCkBAIC0yMjIyNyw4ICsyMjIyNywyNyBAQCBh YXJjaDY0X2V4cGFuZF92ZWN0b3JfaW5pdCAocnR4IHRhcmdldCwgcnR4IHZhbHMpCiAJICAgICB2 ZWN0b3IgcmVnaXN0ZXIuICBGb3IgYmlnLWVuZGlhbiB3ZSB3YW50IHRoYXQgcG9zaXRpb24gdG8g aG9sZAogCSAgICAgdGhlIGxhc3QgZWxlbWVudCBvZiBWQUxTLiAgKi8KIAkgIG1heGVsZW1lbnQg PSBCWVRFU19CSUdfRU5ESUFOID8gbl9lbHRzIC0gMSA6IDA7Ci0JICBydHggeCA9IGZvcmNlX3Jl ZyAoaW5uZXJfbW9kZSwgWFZFQ0VYUCAodmFscywgMCwgbWF4ZWxlbWVudCkpOwotCSAgYWFyY2g2 NF9lbWl0X21vdmUgKHRhcmdldCwgbG93cGFydF9zdWJyZWcgKG1vZGUsIHgsIGlubmVyX21vZGUp KTsKKworCSAgLyogSWYgd2UgaGF2ZSBhIHNpbmdsZSBjb25zdGFudCBlbGVtZW50LCB1c2UgdGhh dCBmb3IgZHVwbGljYXRpbmcKKwkgICAgIGluc3RlYWQuICAqLworCSAgaWYgKG5fdmFyID09IG5f ZWx0cyAtIDEpCisJICAgIHsKKwkgICAgICBmb3IgKGludCBpID0gMDsgaSA8IG5fZWx0czsgaSsr KQorCQlpZiAoQ09OU1RfSU5UX1AgKFhWRUNFWFAgKHZhbHMsIDAsIGkpKQorCQkgICAgfHwgQ09O U1RfRE9VQkxFX1AgKFhWRUNFWFAgKHZhbHMsIDAsIGkpKSkKKwkJICB7CisJCSAgICBtYXhlbGVt ZW50ID0gaTsKKwkJICAgIHJ0eCBjb25zdF9lbGVtID0gWFZFQ0VYUCAodmFscywgMCwgbWF4ZWxl bWVudCk7CisJCSAgICBhYXJjaDY0X2VtaXRfbW92ZSAodGFyZ2V0LAorCQkJCSAgICAgICBnZW5f dmVjX2R1cGxpY2F0ZSAobW9kZSwgY29uc3RfZWxlbSkpOworCQkgICAgYnJlYWs7CisJCSAgfQor CSAgICB9CisJICBlbHNlCisJICAgIHsKKwkgICAgICBydHggeCA9IGZvcmNlX3JlZyAoaW5uZXJf bW9kZSwgWFZFQ0VYUCAodmFscywgMCwgbWF4ZWxlbWVudCkpOworCSAgICAgIGFhcmNoNjRfZW1p dF9tb3ZlICh0YXJnZXQsIGxvd3BhcnRfc3VicmVnIChtb2RlLCB4LCBpbm5lcl9tb2RlKSk7CisJ ICAgIH0KIAl9CiAgICAgICBlbHNlCiAJewpkaWZmIC0tZ2l0IGEvZ2NjL3Rlc3RzdWl0ZS9nY2Mu dGFyZ2V0L2FhcmNoNjQvdmVjLWluaXQtc2luZ2xlLWNvbnN0LmMgYi9nY2MvdGVzdHN1aXRlL2dj Yy50YXJnZXQvYWFyY2g2NC92ZWMtaW5pdC1zaW5nbGUtY29uc3QuYwpuZXcgZmlsZSBtb2RlIDEw MDY0NAppbmRleCAwMDAwMDAwMDAwMC4uNzkwYzkwYjQ4Y2UKLS0tIC9kZXYvbnVsbAorKysgYi9n Y2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYWFyY2g2NC92ZWMtaW5pdC1zaW5nbGUtY29uc3QuYwpA QCAtMCwwICsxLDU4IEBACisvKiB7IGRnLWRvIGNvbXBpbGUgfSAqLworLyogeyBkZy1vcHRpb25z ICItTzIgLWZuby1zY2hlZHVsZS1pbnNucyAtZm5vLXNjaGVkdWxlLWluc25zMiIgfSAqLworLyog eyBkZy1maW5hbCB7IGNoZWNrLWZ1bmN0aW9uLWJvZGllcyAiKioiICIiICIiIH0gfSAqLworCisj aW5jbHVkZSA8YXJtX25lb24uaD4KKworLyoKKyoqIGZfczg6CisqKglkdXAJdlswLTldK1wuMTZi LCB3WzAtOV0rCisqKgltb3ZpCXZbMC05XStcLjhiLCAweDEKKyoqCWlucwl2WzAtOV0rXC5iXFsx NVxdLCB2WzAtOV0rXC5iXFswXF0KKyoqCXJldAorKi8KKworaW50OHgxNl90IGZfczgoaW50OF90 IHgpCit7CisgIHJldHVybiAoaW50OHgxNl90KSB7IHgsIHgsIHgsIHgsIHgsIHgsIHgsIHgsCisg ICAgICAgICAgICAgICAgICAgICAgIHgsIHgsIHgsIHgsIHgsIHgsIHgsIDEgfTsKK30KKworLyoK KyoqIGZfczE2OgorKioJZHVwCXZbMC05XStcLjhoLCB3WzAtOV0rCisqKgltb3ZpCXZbMC05XStc LjRoLCAweDEKKyoqCWlucwl2WzAtOV0rXC5oXFs3XF0sIHZbMC05XStcLmhcWzBcXQorKioJcmV0 CisqLworCitpbnQxNng4X3QgZl9zMTYoaW50MTZfdCB4KQoreworICByZXR1cm4gKGludDE2eDhf dCkgeyB4LCB4LCB4LCB4LCB4LCB4LCB4LCAxIH07Cit9CisKKy8qCisqKiBmX3MzMjoKKyoqCWR1 cAl2WzAtOV1cLjRzLCB3WzAtOV0rCisqKgltb3ZpCXZbMC05XVwuMnMsIDB4MQorKioJaW5zCXZb MC05XStcLnNcWzNcXSwgdlswLTldK1wuc1xbMFxdCisqKglyZXQKKyovCisKK2ludDMyeDRfdCBm X3MzMihpbnQzMl90IHgpCit7CisgIHJldHVybiAoaW50MzJ4NF90KSB7IHgsIHgsIHgsIDEgfTsK K30KKworLyoKKyoqIGZfczY0OgorKioJYWRycAl4WzAtOV0rLCAuTENbMC05XSsKKyoqCWxkcglx WzAtOV0rLCBcW3hbMC05XSssICM6bG8xMjouTENbMC05XStcXQorKioJaW5zCXZbMC05XStcLmRc WzBcXSwgeFswLTldKworKioJcmV0CisqLworCitpbnQ2NHgyX3QgZl9zNjQoaW50NjRfdCB4KQor eworICByZXR1cm4gKGludDY0eDJfdCkgeyB4LCAxIH07Cit9Cg== --0000000000008894d605fab5395a--