From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by sourceware.org (Postfix) with ESMTPS id 25FA73858D20 for ; Mon, 12 Jun 2023 17:52:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 25FA73858D20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-30fca48b473so271775f8f.3 for ; Mon, 12 Jun 2023 10:52:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686592358; x=1689184358; h=to:subject:message-id:date:from:in-reply-to:references:mime-version :from:to:cc:subject:date:message-id:reply-to; bh=OZ77cyvCMcylJF0ZDdBvoZK7LMILGeQoI5HKquQX7Os=; b=Hmo1wOv1n3NIHrcNVKRn3IKHGJucDE49j9nHrsseVj2SR0+axEYSCoYRa2Tad9pmpp QXDRjdQAkBBMNx4SBottkzL0ZEhFP/8/VvQiUa725l27GtRHTupkf7OmBO0cwsdt/KYj NJixGZ8xOfQ4MxYdn0tGoM4n/0Qg27MF3kQouJFXUjS7jLYlq8gb4GQ80TxMUFW7Kblq P1vZpS3FfiQ5r689pAYHiclJ796ZDd3a905Pv+rUNPhTLUlsTz/FJPPe3sq6jhLJ3n4V JXjNk5AasPaxYXOdctXIG1f5TjwFx03AZBxdjfgANagQ2dJKk4E11Cngqz5z1WPUz4Rj FNkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686592358; x=1689184358; h=to:subject:message-id:date:from:in-reply-to:references:mime-version :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=OZ77cyvCMcylJF0ZDdBvoZK7LMILGeQoI5HKquQX7Os=; b=LESJnYqW7ahrqUMCqUFTMh9mlYorAr3zCwpBJKpvXwqvPLpe865YkFhK+9dtlNjaSb oN72L+osf5e2U0DBv4RB3J5+5wlkSfZPOEKY8WdVoKhYFn/L159jFMQzbBlZbE6PI94T /gkHqQqH5HldezKDFznWgAexF5zgZqaRGUIpNnpQuiTU5zveUqDfs8kpYfMkNguOk4N8 xwT8vhSsFia9VhE71c9F1jg9he3SW9q10d45tBKdfC2QDEEWy3ZgqpxaEckCZSVFawhJ TpQhmk3vnyR0YyR1Oed1a4afyQp416t9PK/dWyd9CGVSfNXd6rXNX3k3QxlsGuYxmm6D m50A== X-Gm-Message-State: AC+VfDwVh7qxcUhP8QPSwrSsbQZCFKTd1JLIbpjYVuCzNCqixHq9quK/ HWqzH47NG/kvx0jTAoXtx4xiMiz2fUBUiDs/xEFymg== X-Google-Smtp-Source: ACHHUZ4gPelIRj+EsjVmaaG1+pVbs6CCYTp7oumL6uKwul8fH2TeuhECOs8LYkdwv6fUTcUHwp1qJHZvnGQMmq6nGcQ= X-Received: by 2002:adf:f649:0:b0:30a:9014:838d with SMTP id x9-20020adff649000000b0030a9014838dmr5322183wrp.11.1686592357967; Mon, 12 Jun 2023 10:52:37 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Prathamesh Kulkarni Date: Mon, 12 Jun 2023 23:22:00 +0530 Message-ID: Subject: Re: [aarch64] Code-gen for vector initialization involving constants To: Prathamesh Kulkarni , gcc Patches , richard.sandiford@arm.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, 31 May 2023 at 00:23, Richard Sandiford wrote: > > Prathamesh Kulkarni writes: > > Hi Richard, > > The s32 case for single constant patch doesn't regress now after the > > above commit. > > Bootstrapped+tested on aarch64-linux-gnu, and verified that the new > > tests pass for aarch64_be-linux-gnu. > > Is it OK to commit ? > > > > Thanks, > > Prathamesh > > > > [aarch64] Improve code-gen for vector initialization with single constant element. > > > > gcc/ChangeLog: > > * config/aarch64/aarc64.cc (aarch64_expand_vector_init): Tweak condition > > if (n_var == n_elts && n_elts <= 16) to allow a single constant, > > and if maxv == 1, use constant element for duplicating into register. > > > > gcc/testsuite/ChangeLog: > > * gcc.target/aarch64/vec-init-single-const.c: New test. > > * gcc.target/aarch64/vec-init-single-const-be.c: Likewise. > > * gcc.target/aarch64/vec-init-single-const-2.c: Likewise. > > OK, thanks. Hi Richard, Sorry for the delay, I was away on vacation. Committed the patch after rebasing on ToT, and verifying bootstrap+test passes on aarch64-linux-gnu: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=9eb757d11746c006c044ff45538b956be7f5859c Thanks, Prathamesh > > Richard > > > diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc > > index 5b046d32b37..30d6e3e8d83 100644 > > --- a/gcc/config/aarch64/aarch64.cc > > +++ b/gcc/config/aarch64/aarch64.cc > > @@ -22192,7 +22192,7 @@ aarch64_expand_vector_init_fallback (rtx target, rtx vals) > > and matches[X][1] with the count of duplicate elements (if X is the > > earliest element which has duplicates). */ > > > > - if (n_var == n_elts && n_elts <= 16) > > + if (n_var >= n_elts - 1 && n_elts <= 16) > > { > > int matches[16][2] = {0}; > > for (int i = 0; i < n_elts; i++) > > @@ -22209,12 +22209,23 @@ aarch64_expand_vector_init_fallback (rtx target, rtx vals) > > } > > int maxelement = 0; > > int maxv = 0; > > + rtx const_elem = NULL_RTX; > > + int const_elem_pos = 0; > > + > > for (int i = 0; i < n_elts; i++) > > - if (matches[i][1] > maxv) > > - { > > - maxelement = i; > > - maxv = matches[i][1]; > > - } > > + { > > + if (matches[i][1] > maxv) > > + { > > + maxelement = i; > > + maxv = matches[i][1]; > > + } > > + if (CONST_INT_P (XVECEXP (vals, 0, i)) > > + || CONST_DOUBLE_P (XVECEXP (vals, 0, i))) > > + { > > + const_elem_pos = i; > > + const_elem = XVECEXP (vals, 0, i); > > + } > > + } > > > > /* Create a duplicate of the most common element, unless all elements > > are equally useless to us, in which case just immediately set the > > @@ -22252,8 +22263,19 @@ aarch64_expand_vector_init_fallback (rtx target, rtx vals) > > vector register. For big-endian we want that position to hold > > the last element of VALS. */ > > maxelement = BYTES_BIG_ENDIAN ? n_elts - 1 : 0; > > - rtx x = force_reg (inner_mode, XVECEXP (vals, 0, maxelement)); > > - aarch64_emit_move (target, lowpart_subreg (mode, x, inner_mode)); > > + > > + /* If we have a single constant element, use that for duplicating > > + instead. */ > > + if (const_elem) > > + { > > + maxelement = const_elem_pos; > > + aarch64_emit_move (target, gen_vec_duplicate (mode, const_elem)); > > + } > > + else > > + { > > + rtx x = force_reg (inner_mode, XVECEXP (vals, 0, maxelement)); > > + aarch64_emit_move (target, lowpart_subreg (mode, x, inner_mode)); > > + } > > } > > else > > { > > diff --git a/gcc/testsuite/gcc.target/aarch64/vec-init-single-const-2.c b/gcc/testsuite/gcc.target/aarch64/vec-init-single-const-2.c > > new file mode 100644 > > index 00000000000..f4dcab429c1 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/aarch64/vec-init-single-const-2.c > > @@ -0,0 +1,30 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-O2" } */ > > + > > +#include > > + > > +/* In case where there are no duplicate elements in vector initializer, > > + check that the constant is used for duplication. */ > > + > > +int8x16_t f_s8(int8_t a0, int8_t a1, int8_t a2, int8_t a3, int8_t a4, > > + int8_t a5, int8_t a6, int8_t a7, int8_t a8, int8_t a9, > > + int8_t a10, int8_t a11, int8_t a12, int8_t a13, int8_t a14) > > +{ > > + return (int8x16_t) { a0, a1, a2, a3, a4, a5, a6, a7, > > + a8, a9, a10, a11, a12, a13, a14, 1 }; > > +} > > + > > +int16x8_t f_s16(int16_t a0, int16_t a1, int16_t a2, int16_t a3, int16_t a4, > > + int16_t a5, int16_t a6) > > +{ > > + return (int16x8_t) { a0, a1, a2, a3, a4, a5, a6, 1 }; > > +} > > + > > +int32x4_t f_s32(int32_t a0, int32_t a1, int32_t a2) > > +{ > > + return (int32x4_t) { a0, a1, a2, 1 }; > > +} > > + > > +/* { dg-final { scan-assembler {\tmovi\tv[0-9]+\.8b, 0x1} } } */ > > +/* { dg-final { scan-assembler {\tmovi\tv[0-9]+\.4h, 0x1} } } */ > > +/* { dg-final { scan-assembler {\tmovi\tv[0-9]+\.2s, 0x1} } } */ > > diff --git a/gcc/testsuite/gcc.target/aarch64/vec-init-single-const-be.c b/gcc/testsuite/gcc.target/aarch64/vec-init-single-const-be.c > > new file mode 100644 > > index 00000000000..3140e007b5d > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/aarch64/vec-init-single-const-be.c > > @@ -0,0 +1,58 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-O2 -fno-schedule-insns -fno-schedule-insns2" } */ > > +/* { dg-final { check-function-bodies "**" "" "" { target { be } } } } */ > > + > > +#include > > + > > +/* > > +** f_s8: > > +** dup v0.16b, w0 > > +** movi (v[0-9]+)\.8b, 0x1 > > +** ins v0.b\[0\], \1\.b\[0\] > > +** ret > > +*/ > > + > > +int8x16_t f_s8(int8_t x) > > +{ > > + return (int8x16_t) { x, x, x, x, x, x, x, x, > > + x, x, x, x, x, x, x, 1 }; > > +} > > + > > +/* > > +** f_s16: > > +** dup v0.8h, w0 > > +** movi (v[0-9]+)\.4h, 0x1 > > +** ins v0.h\[0\], \1\.h\[0\] > > +** ret > > +*/ > > + > > +int16x8_t f_s16(int16_t x) > > +{ > > + return (int16x8_t) { x, x, x, x, x, x, x, 1 }; > > +} > > + > > +/* > > +** f_s32: > > +** dup v0.4s, w0 > > +** movi (v[0-9]+)\.2s, 0x1 > > +** ins v0.s\[0\], \1\.s\[0\] > > +** ret > > +*/ > > + > > +int32x4_t f_s32(int32_t x) > > +{ > > + return (int32x4_t) { x, x, x, 1 }; > > +} > > + > > +/* > > +** f_s64: > > +** adrp x[0-9]+, .LC[0-9]+ > > +** ldr q0, \[x[0-9]+, #:lo12:.LC[0-9]+\] > > +** ins v0\.d\[1\], x0 > > +** ret > > +*/ > > + > > +int64x2_t f_s64(int64_t x) > > +{ > > + return (int64x2_t) { x, 1 }; > > +} > > diff --git a/gcc/testsuite/gcc.target/aarch64/vec-init-single-const.c b/gcc/testsuite/gcc.target/aarch64/vec-init-single-const.c > > new file mode 100644 > > index 00000000000..274b0b39ac4 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/aarch64/vec-init-single-const.c > > @@ -0,0 +1,58 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-O2 -fno-schedule-insns -fno-schedule-insns2" } */ > > +/* { dg-final { check-function-bodies "**" "" "" { target { le } } } } */ > > + > > +#include > > + > > +/* > > +** f_s8: > > +** dup v0.16b, w0 > > +** movi (v[0-9]+)\.8b, 0x1 > > +** ins v0.b\[15\], \1\.b\[0\] > > +** ret > > +*/ > > + > > +int8x16_t f_s8(int8_t x) > > +{ > > + return (int8x16_t) { x, x, x, x, x, x, x, x, > > + x, x, x, x, x, x, x, 1 }; > > +} > > + > > +/* > > +** f_s16: > > +** dup v0.8h, w0 > > +** movi (v[0-9]+)\.4h, 0x1 > > +** ins v0.h\[7\], \1\.h\[0\] > > +** ret > > +*/ > > + > > +int16x8_t f_s16(int16_t x) > > +{ > > + return (int16x8_t) { x, x, x, x, x, x, x, 1 }; > > +} > > + > > +/* > > +** f_s32: > > +** dup v0.4s, w0 > > +** movi (v[0-9]+)\.2s, 0x1 > > +** ins v0.s\[3\], \1\.s\[0\] > > +** ret > > +*/ > > + > > +int32x4_t f_s32(int32_t x) > > +{ > > + return (int32x4_t) { x, x, x, 1 }; > > +} > > + > > +/* > > +** f_s64: > > +** adrp x[0-9]+, .LC[0-9]+ > > +** ldr q0, \[x[0-9]+, #:lo12:.LC[0-9]+\] > > +** ins v0\.d\[0\], x0 > > +** ret > > +*/ > > + > > +int64x2_t f_s64(int64_t x) > > +{ > > + return (int64x2_t) { x, 1 }; > > +}