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Sun, 31 Jul 2022 20:17:12 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Prathamesh Kulkarni Date: Mon, 1 Aug 2022 08:46:36 +0530 Message-ID: Subject: Re: ICE after folding svld1rq to vec_perm_expr duing forwprop To: Richard Biener Cc: gcc Patches , Richard Sandiford Content-Type: multipart/mixed; boundary="000000000000a11fa305e5256f36" X-Spam-Status: No, score=-9.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_PASS, TXREP, WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 01 Aug 2022 03:17:18 -0000 --000000000000a11fa305e5256f36 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, 21 Jul 2022 at 12:21, Richard Biener w= rote: > > On Wed, Jul 20, 2022 at 5:36 PM Prathamesh Kulkarni > wrote: > > > > On Mon, 18 Jul 2022 at 11:57, Richard Biener wrote: > > > > > > On Fri, Jul 15, 2022 at 3:49 PM Prathamesh Kulkarni > > > wrote: > > > > > > > > On Thu, 14 Jul 2022 at 17:22, Richard Sandiford > > > > wrote: > > > > > > > > > > Richard Biener writes: > > > > > > On Thu, Jul 14, 2022 at 9:55 AM Prathamesh Kulkarni > > > > > > wrote: > > > > > >> > > > > > >> On Wed, 13 Jul 2022 at 12:22, Richard Biener wrote: > > > > > >> > > > > > > >> > On Tue, Jul 12, 2022 at 9:12 PM Prathamesh Kulkarni via Gcc-= patches > > > > > >> > wrote: > > > > > >> > > > > > > > >> > > Hi Richard, > > > > > >> > > For the following test: > > > > > >> > > > > > > > >> > > svint32_t f2(int a, int b, int c, int d) > > > > > >> > > { > > > > > >> > > int32x4_t v =3D (int32x4_t) {a, b, c, d}; > > > > > >> > > return svld1rq_s32 (svptrue_b8 (), &v[0]); > > > > > >> > > } > > > > > >> > > > > > > > >> > > The compiler emits following ICE with -O3 -mcpu=3Dgeneric+= sve: > > > > > >> > > foo.c: In function =E2=80=98f2=E2=80=99: > > > > > >> > > foo.c:4:11: error: non-trivial conversion in =E2=80=98view= _convert_expr=E2=80=99 > > > > > >> > > 4 | svint32_t f2(int a, int b, int c, int d) > > > > > >> > > | ^~ > > > > > >> > > svint32_t > > > > > >> > > __Int32x4_t > > > > > >> > > _7 =3D VIEW_CONVERT_EXPR<__Int32x4_t>(_8); > > > > > >> > > during GIMPLE pass: forwprop > > > > > >> > > dump file: foo.c.109t.forwprop2 > > > > > >> > > foo.c:4:11: internal compiler error: verify_gimple failed > > > > > >> > > 0xfda04a verify_gimple_in_cfg(function*, bool) > > > > > >> > > ../../gcc/gcc/tree-cfg.cc:5568 > > > > > >> > > 0xe9371f execute_function_todo > > > > > >> > > ../../gcc/gcc/passes.cc:2091 > > > > > >> > > 0xe93ccb execute_todo > > > > > >> > > ../../gcc/gcc/passes.cc:2145 > > > > > >> > > > > > > > >> > > This happens because, after folding svld1rq_s32 to vec_per= m_expr, we have: > > > > > >> > > int32x4_t v; > > > > > >> > > __Int32x4_t _1; > > > > > >> > > svint32_t _9; > > > > > >> > > vector(4) int _11; > > > > > >> > > > > > > > >> > > : > > > > > >> > > _1 =3D {a_3(D), b_4(D), c_5(D), d_6(D)}; > > > > > >> > > v_12 =3D _1; > > > > > >> > > _11 =3D v_12; > > > > > >> > > _9 =3D VEC_PERM_EXPR <_11, _11, { 0, 1, 2, 3, ... }>; > > > > > >> > > return _9; > > > > > >> > > > > > > > >> > > During forwprop, simplify_permutation simplifies vec_perm_= expr to > > > > > >> > > view_convert_expr, > > > > > >> > > and the end result becomes: > > > > > >> > > svint32_t _7; > > > > > >> > > __Int32x4_t _8; > > > > > >> > > > > > > > >> > > ;; basic block 2, loop depth 0 > > > > > >> > > ;; pred: ENTRY > > > > > >> > > _8 =3D {a_2(D), b_3(D), c_4(D), d_5(D)}; > > > > > >> > > _7 =3D VIEW_CONVERT_EXPR<__Int32x4_t>(_8); > > > > > >> > > return _7; > > > > > >> > > ;; succ: EXIT > > > > > >> > > > > > > > >> > > which causes the error duing verify_gimple since VIEW_CONV= ERT_EXPR > > > > > >> > > has incompatible types (svint32_t, int32x4_t). > > > > > >> > > > > > > > >> > > The attached patch disables simplification of VEC_PERM_EXP= R > > > > > >> > > in simplify_permutation, if lhs and rhs have non compatibl= e types, > > > > > >> > > which resolves ICE, but am not sure if it's the correct ap= proach ? > > > > > >> > > > > > > >> > It for sure papers over the issue. I think the error happen= s earlier, > > > > > >> > the V_C_E should have been built with the type of the VEC_PE= RM_EXPR > > > > > >> > which is the type of the LHS. But then you probably run int= o the > > > > > >> > different sizes ICE (VLA vs constant size). I think for thi= s case you > > > > > >> > want a BIT_FIELD_REF instead of a VIEW_CONVERT_EXPR, > > > > > >> > selecting the "low" part of the VLA vector. > > > > > >> Hi Richard, > > > > > >> Sorry I don't quite follow. In this case, we use VEC_PERM_EXPR= to > > > > > >> represent dup operation > > > > > >> from fixed width to VLA vector. I am not sure how folding it t= o > > > > > >> BIT_FIELD_REF will work. > > > > > >> Could you please elaborate ? > > > > > >> > > > > > >> Also, the issue doesn't seem restricted to this case. > > > > > >> The following test case also ICE's during forwprop: > > > > > >> svint32_t foo() > > > > > >> { > > > > > >> int32x4_t v =3D (int32x4_t) {1, 2, 3, 4}; > > > > > >> svint32_t v2 =3D svld1rq_s32 (svptrue_b8 (), &v[0]); > > > > > >> return v2; > > > > > >> } > > > > > >> > > > > > >> foo2.c: In function =E2=80=98foo=E2=80=99: > > > > > >> foo2.c:9:1: error: non-trivial conversion in =E2=80=98vector_c= st=E2=80=99 > > > > > >> 9 | } > > > > > >> | ^ > > > > > >> svint32_t > > > > > >> int32x4_t > > > > > >> v2_4 =3D { 1, 2, 3, 4 }; > > > > > >> > > > > > >> because simplify_permutation folds > > > > > >> VEC_PERM_EXPR< {1, 2, 3, 4}, {1, 2, 3, 4}, {0, 1, 2, 3, ...} > > > > > > >> into: > > > > > >> vector_cst {1, 2, 3, 4} > > > > > >> > > > > > >> and it complains during verify_gimple_assign_single because we= don't > > > > > >> support assignment of vector_cst to VLA vector. > > > > > >> > > > > > >> I guess the issue really is that currently, only VEC_PERM_EXPR > > > > > >> supports lhs and rhs > > > > > >> to have vector types with differing lengths, and simplifying i= t to > > > > > >> other tree codes, like above, > > > > > >> will result in type errors ? > > > > > > > > > > > > That might be the case - Richard should know. > > > > > > > > > > I don't see anything particularly special about VEC_PERM_EXPR her= e, > > > > > or about the VLA vs. VLS thing. We would have the same issue try= ing > > > > > to build a 128-bit vector from 2 64-bit vectors. And there are o= ther > > > > > tree codes whose input types are/can be different from their outp= ut > > > > > types. > > > > > > > > > > So it just seems like a normal type correctness issue: a VEC_PERM= _EXPR > > > > > of type T needs to be replaced by something of type T. Whether T= has a > > > > > constant size or a variable size doesn't matter. > > > > > > > > > > > If so your type check > > > > > > is still too late, you should instead recognize that we are per= muting > > > > > > a VLA vector and then refuse to go any of the non-VEC_PERM gene= rating > > > > > > paths - that probably means just allowing the code =3D=3D VEC_P= ERM_EXPR > > > > > > case and not any of the CTOR/CST/VIEW_CONVERT_EXPR cases? > > > > > > > > > > Yeah. If we're talking about the match.pd code, I think only: > > > > > > > > > > (if (sel.series_p (0, 1, 0, 1)) > > > > > { op0; } > > > > > (if (sel.series_p (0, 1, nelts, 1)) > > > > > { op1; } > > > > > > > > > > need a type compatibility check. For fold_vec_perm I think > > > > > we should just rearrange: > > > > > > > > > > gcc_assert (known_eq (TYPE_VECTOR_SUBPARTS (type), nelts) > > > > > && known_eq (TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg0)= ), nelts) > > > > > && known_eq (TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg1)= ), nelts)); > > > > > if (TREE_TYPE (TREE_TYPE (arg0)) !=3D TREE_TYPE (type) > > > > > || TREE_TYPE (TREE_TYPE (arg1)) !=3D TREE_TYPE (type)) > > > > > return NULL_TREE; > > > > > > > > > > so that the assert comes after the early-out. > > > > > > > > > > It would be good at some point to relax fold_vec_perm to cases wh= ere the > > > > > outputs are a different length from the inputs, since the all-con= stant > > > > > VEC_PERM_EXPR above could be folded to a VECTOR_CST. > > > > Hi, > > > > For the above case, I think the issue is that simplify_permutation > > > > uses TREE_TYPE (arg0) for res_type, > > > > while it should now use type for lhs. > > > > > > > > /* Shuffle of a constructor. */ > > > > bool ret =3D false; > > > > tree res_type =3D TREE_TYPE (arg0); > > > > tree opt =3D fold_ternary (VEC_PERM_EXPR, res_type, arg0, arg= 1, op2); > > > > > > > > Using, res_type =3D TREE_TYPE (gimple_get_lhs (stmt)), > > > > resolves the ICE, and emits all constant VEC_PERM_EXPR: > > > > > > > > v2_4 =3D VEC_PERM_EXPR <{ 1, 2, 3, 4 }, { 1, 2, 3, 4 }, { 0, 1, 2= , 3, ... }>; > > > > return v2_4; > > > > > > > > Does the patch look OK to commit after bootstrap+test ? > > > > > > Ok with using gimple_assign_lhs (stmt) instead of gimple_get_lhs (stm= t). > > Hi, > > I committed the patch but unfortunately it caused PR106360. > > The issue is that for slp-reduc-sad-2.c on ppc64le, > > simplify_permutation sees the following during forwprop4: > > > > _78 =3D (void *) ivtmp.21_73; > > _92 =3D MEM [(uint8_t *)_78]; > > _91 =3D {_92, 0}; > > vect__1.6_90 =3D VIEW_CONVERT_EXPR(_91); > > _88 =3D MEM [(uint8_t *)_78 + 16B]; > > _87 =3D {_88, 0}; > > vect__1.7_86 =3D VIEW_CONVERT_EXPR(_87); > > vect__1.8_85 =3D VEC_PERM_EXPR > 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23 }>; > > > > So for, > > tree res_type =3D TREE_TYPE (gimple_assign_lhs (stmt)); > > tree opt =3D fold_ternary (VEC_PERM_EXPR, res_type, arg0, arg1, op2); > > > > we have: > > res_type =3D V16QI > > arg0 =3D {_92, 0} > > arg1 =3D {_88, 0} > > op2 =3D {0, 2} > > > > and thus we hit the following assert in fold_vec_perm: > > > > gcc_assert (known_eq (TYPE_VECTOR_SUBPARTS (type), nelts) > > && known_eq (TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg0)), nel= ts) > > && known_eq (TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg1)), nel= ts)); > > > > since nelts =3D=3D 2, and TYPE_VECTOR_SUBPARTS (type) =3D=3D 16. > > > > If we revert the committed patch so we pass res_type =3D TREE_TYPE (arg= 0) instead, > > it simplifies the above VEC_PERM_EXPR to VIEW_CONVERT_EXPR: > > _92 =3D MEM [(uint8_t *)_78]; > > _88 =3D MEM [(uint8_t *)_78 + 16B]; > > _5 =3D {_92, _88}; > > vect__1.8_85 =3D VIEW_CONVERT_EXPR(_5); > > > > I suppose it's legal to cast vector of one type to another as long as > > sizes match ? > > > > IIUC, the above VIEW_CONVERT_EXPR will result in: > > vect__1.8_85 =3D { (uint8_t) _92, 0, 0, 0, 0, 0, 0, 0, (uint8_t) _88, 0= , > > 0, 0, 0, 0, 0, 0 } ? > > > > In the attached patch, it restores res_type to TREE_TYPE (arg0), and ch= ecks > > if lhs_type and res_type differ but have same size, and in that case em= it: > > lhs =3D VIEW_CONVERT_EXPR (opt), > > instead of: > > lhs =3D VIEW_CONVERT_EXPR (opt) > > where opt is result of folding VEC_PERM_EXPR > > > > Does it look OK ? > > Definitely the original change was bogus. > > + if (!operand_equal_p (TYPE_SIZE (lhs_type), TYPE_SIZE (res_type= ))) > + return 0; > > just repeats your very original change though ... I'll note that > fold_ternary will > ICE on now valid VEC_PERM_EXPRs so we should fix it, possibly by > returning NULL_TREE on cases it does not handle. > > I think what should be done is, in the > > /* If there are any VIEW_CONVERT_EXPRs found when finding permutati= on > operands source, check whether it's valid to transform and prepa= re > the required new operands. */ > if (code =3D=3D VIEW_CONVERT_EXPR || code2 =3D=3D VIEW_CONVERT_EXPR= ) > { > ... > > path also transform the expected result type. It should remain V_C_E com= patible > to TREE_TYPE (lhs) but get a new element type. > > But as said, > > tree > fold_vec_perm (tree type, tree arg0, tree arg1, const vec_perm_indices &s= el) > { > unsigned int i; > unsigned HOST_WIDE_INT nelts; > bool need_ctor =3D false; > > if (!sel.length ().is_constant (&nelts)) > return NULL_TREE; > gcc_assert (known_eq (TYPE_VECTOR_SUBPARTS (type), nelts) > && known_eq (TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg0)), nelts= ) > && known_eq (TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg1)), nelts= )); > > ^^^ this doesn't match what we allow for VEC_PERM_EXPRs now and fold_tern= ary > doesn't guard according to those asserts (I think we should extend fold_v= ec_perm > to support the new constraints). Hi Richard, Thanks for the suggestions and sorry for late reply. I reverted the change = to simplify_permutaton which resolved the ppc64le case ICE. The attached patch extends fold_vec_perm to handle vectors with differing lengths. For, lhs =3D vec_perm_expr, the patch: (a) asserts lhs and mask have same vector length. (b) asserts arg0 and arg1 have same vector length. (c) returns NULL_TREE if element type differs for lhs, arg0 and arg1. (d) if len(lhs) > len(arg0), then the patch allows permuting arg0, arg1 if the mask has npatterns =3D=3D len(arg0) and nelts_per_pattern =3D=3D 1. The intent is to permute arg0 and arg1, and then to dup elements in result to target vector length. So for eg: vec_perm_expr< {1, 2, 3, 4}, {5, 6, 7, 8}, {0, 4, 1, 5, ...}> will result in vla vector {1, 5, 2, 6, ....} with {1, 5, 2, 6} replicated thru-out. Does it look OK ? With the patch, we don't ICE for either of the aarch64 tests above. For, svint32_t f1() { int32x4_t v =3D {1, 2, 3, 4}; return svld1rq_s32 (svptrue_b8 (), &v[0]); } optimized dump shows: svint32_t f1 () { int32x4_t v; : return { 1, 2, 3, 4, ... }; } code-gen: f1: .LFB3900: .cfi_startproc ptrue p0.b, all adrp x0, .LC0 add x0, x0, :lo12:.LC0 ld1rqw z0.s, p0/z, [x0] ret .LC0: .word 1 .word 2 .word 3 .word 4 I guess for this particular case, we could use index instead. For, svint32_t f2(int a, int b, int c, int d) { int32x4_t v =3D {a, b, c, d}; return svld1rq_s32 (svptrue_b8 (), &v[0]); } optimized dump shows: svint32_t f2 (int a, int b, int c, int d) { svint32_t _6; [local count: 1073741824]: _6 =3D {a_1(D), b_2(D), c_3(D), d_4(D), ... }; return _6; The code-gen seems pretty bad however: f2: .LFB3901: .cfi_startproc addvl sp, sp, #-4 .cfi_escape 0xf,0x9,0x8f,0,0x92,0x2e,0,0x8,0x20,0x1e,0x22 ptrue p0.b, all addvl x4, sp, #3 mov z0.b, #0 st1w z0.s, p0, [sp, #3, mul vl] str w0, [x4] addvl x0, sp, #2 ld1w z0.s, p0/z, [sp, #3, mul vl] st1w z0.s, p0, [sp, #2, mul vl] str w1, [x0, 4] addvl x0, sp, #1 ld1w z0.s, p0/z, [sp, #2, mul vl] st1w z0.s, p0, [sp, #1, mul vl] str w2, [x0, 8] ld1w z0.s, p0/z, [sp, #1, mul vl] st1w z0.s, p0, [sp] str w3, [sp, 12] ld1w z0.s, p0/z, [sp] addvl sp, sp, #4 .cfi_def_cfa_offset 0 ret I will try to address code-gen issues in follow up patches. Bootstrapped+tested on x64_64-linux-gnu and aarch64-linux-gnu. Thanks, Prathamesh > > Richard. > > > Thanks, > > Prathamesh > > > > > > > > > I will try to address the folding for above VEC_PERM_EXPR in follow= -up patch. > > > > > > > > Thanks, > > > > Prathamesh > > > > > > > > > > Thanks, > > > > > Richard --000000000000a11fa305e5256f36 Content-Type: text/plain; charset="US-ASCII"; name="gnu-790-3.txt" Content-Disposition: attachment; filename="gnu-790-3.txt" Content-Transfer-Encoding: base64 Content-ID: X-Attachment-Id: f_l6a3rwdy0 ZGlmZiAtLWdpdCBhL2djYy9mb2xkLWNvbnN0LmNjIGIvZ2NjL2ZvbGQtY29uc3QuY2MKaW5kZXgg OTkwMjFhODJkZjQuLjY5MTJkZTliNDNjIDEwMDY0NAotLS0gYS9nY2MvZm9sZC1jb25zdC5jYwor KysgYi9nY2MvZm9sZC1jb25zdC5jYwpAQCAtMTA1NDEsMTUgKzEwNTQxLDMzIEBAIGZvbGRfdmVj X3Blcm0gKHRyZWUgdHlwZSwgdHJlZSBhcmcwLCB0cmVlIGFyZzEsIGNvbnN0IHZlY19wZXJtX2lu ZGljZXMgJnNlbCkKICAgdW5zaWduZWQgSE9TVF9XSURFX0lOVCBuZWx0czsKICAgYm9vbCBuZWVk X2N0b3IgPSBmYWxzZTsKIAotICBpZiAoIXNlbC5sZW5ndGggKCkuaXNfY29uc3RhbnQgKCZuZWx0 cykpCi0gICAgcmV0dXJuIE5VTExfVFJFRTsKLSAgZ2NjX2Fzc2VydCAoa25vd25fZXEgKFRZUEVf VkVDVE9SX1NVQlBBUlRTICh0eXBlKSwgbmVsdHMpCi0JICAgICAgJiYga25vd25fZXEgKFRZUEVf VkVDVE9SX1NVQlBBUlRTIChUUkVFX1RZUEUgKGFyZzApKSwgbmVsdHMpCi0JICAgICAgJiYga25v d25fZXEgKFRZUEVfVkVDVE9SX1NVQlBBUlRTIChUUkVFX1RZUEUgKGFyZzEpKSwgbmVsdHMpKTsK KyAgZ2NjX2Fzc2VydCAoa25vd25fZXEgKFRZUEVfVkVDVE9SX1NVQlBBUlRTICh0eXBlKSwKKwkJ CXNlbC5sZW5ndGggKCkpKTsKKyAgZ2NjX2Fzc2VydCAoa25vd25fZXEgKFRZUEVfVkVDVE9SX1NV QlBBUlRTIChUUkVFX1RZUEUgKGFyZzApKSwKKwkJCVRZUEVfVkVDVE9SX1NVQlBBUlRTIChUUkVF X1RZUEUgKGFyZzEpKSkpOworCiAgIGlmIChUUkVFX1RZUEUgKFRSRUVfVFlQRSAoYXJnMCkpICE9 IFRSRUVfVFlQRSAodHlwZSkKICAgICAgIHx8IFRSRUVfVFlQRSAoVFJFRV9UWVBFIChhcmcxKSkg IT0gVFJFRV9UWVBFICh0eXBlKSkKICAgICByZXR1cm4gTlVMTF9UUkVFOwogCisgIC8qIElmIHJl c3VsdCB2ZWN0b3IgaGFzIGdyZWF0ZXIgbGVuZ3RoIHRoYW4gaW5wdXQgdmVjdG9yLAorICAgICB0 aGVuIGFsbG93IHBlcm11dGluZyB0d28gdmVjdG9ycyBhcyBsb25nIGFzOgorICAgICBhKSBzZWwu bmVsdHNfcGVyX3BhdHRlcm4gPT0gMQorICAgICBiKSBzZWwubnBhdHRlcm5zID09IGxlbiBvZiBp bnB1dCB2ZWN0b3IuCisgICAgIFRoZSBpbnRlbnQgaXMgdG8gcGVybXV0ZSBpbnB1dCB2ZWN0b3Jz LCBhbmQKKyAgICAgZHVwIHRoZSBlbGVtZW50cyBpbiByZXN1bHRpbmcgdmVjdG9yIHRvIHRhcmdl dCB2ZWN0b3IgbGVuZ3RoLiAgKi8KKworICBpZiAobWF5YmVfZ3QgKFRZUEVfVkVDVE9SX1NVQlBB UlRTICh0eXBlKSwKKwkJVFlQRV9WRUNUT1JfU1VCUEFSVFMgKFRSRUVfVFlQRSAoYXJnMCkpKSkK KyAgICB7CisgICAgICBuZWx0cyA9IHNlbC5lbmNvZGluZyAoKS5ucGF0dGVybnMgKCk7CisgICAg ICBpZiAoc2VsLmVuY29kaW5nICgpLm5lbHRzX3Blcl9wYXR0ZXJuICgpICE9IDEKKwkgIHx8ICgh a25vd25fZXEgKG5lbHRzLCBUWVBFX1ZFQ1RPUl9TVUJQQVJUUyAoVFJFRV9UWVBFIChhcmcwKSkp KSkKKwlyZXR1cm4gTlVMTF9UUkVFOworICAgIH0KKyAgZWxzZSBpZiAoIXNlbC5sZW5ndGggKCku aXNfY29uc3RhbnQgKCZuZWx0cykpCisgICAgcmV0dXJuIE5VTExfVFJFRTsKKwogICB0cmVlICpp bl9lbHRzID0gWEFMTE9DQVZFQyAodHJlZSwgbmVsdHMgKiAyKTsKICAgaWYgKCF2ZWNfY3N0X2N0 b3JfdG9fYXJyYXkgKGFyZzAsIG5lbHRzLCBpbl9lbHRzKQogICAgICAgfHwgIXZlY19jc3RfY3Rv cl90b19hcnJheSAoYXJnMSwgbmVsdHMsIGluX2VsdHMgKyBuZWx0cykpCmRpZmYgLS1naXQgYS9n Y2MvdHJlZS1wcmV0dHktcHJpbnQuY2MgYi9nY2MvdHJlZS1wcmV0dHktcHJpbnQuY2MKaW5kZXgg NDczNzFkOGJjYmUuLjdlNzA2ODU3ZjQzIDEwMDY0NAotLS0gYS9nY2MvdHJlZS1wcmV0dHktcHJp bnQuY2MKKysrIGIvZ2NjL3RyZWUtcHJldHR5LXByaW50LmNjCkBAIC0yNjAyLDYgKzI2MDIsOSBA QCBkdW1wX2dlbmVyaWNfbm9kZSAocHJldHR5X3ByaW50ZXIgKnBwLCB0cmVlIG5vZGUsIGludCBz cGMsIGR1bXBfZmxhZ3NfdCBmbGFncywKIAkJcHBfc3BhY2UgKHBwKTsKIAkgICAgICB9CiAJICB9 CisJaWYgKFZFQ1RPUl9UWVBFX1AgKFRSRUVfVFlQRSAobm9kZSkpCisJICAgICYmICFUWVBFX1ZF Q1RPUl9TVUJQQVJUUyAoVFJFRV9UWVBFIChub2RlKSkuaXNfY29uc3RhbnQgKCkpCisJICBwcF9z dHJpbmcgKHBwLCAiLCAuLi4gIik7CiAJcHBfcmlnaHRfYnJhY2UgKHBwKTsKICAgICAgIH0KICAg ICAgIGJyZWFrOwo= --000000000000a11fa305e5256f36--