From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 117253 invoked by alias); 3 Jun 2019 12:15:26 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 117178 invoked by uid 89); 3 Jun 2019 12:15:19 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.3 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mail-lj1-f169.google.com Received: from mail-lj1-f169.google.com (HELO mail-lj1-f169.google.com) (209.85.208.169) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 03 Jun 2019 12:15:16 +0000 Received: by mail-lj1-f169.google.com with SMTP id 131so3397768ljf.4 for ; Mon, 03 Jun 2019 05:15:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to; bh=0iLUXG6x8bW158yQEbNgv2qJQ2+MnVpdSkJrGAlFLcI=; b=EhswuratrT5D2vj+hZrrn8BJN9oqWb5u8cr/PrEm9Iq39tnt3lo5UyjjifZzyKf6pX /Jyzj2hHKK8Zjnlj/kmCrFAAcRZb2CZUbvKvnK4wa7Vl8hDMBYFkQApN7X82GGLAwL3S pgRXh89BvHSS4YDTsLbhCe0XXKO79CTZHEqy03ewq7eLkxozfVg5wLX8RrFxNXuN6ZKk /eoMP0d0aPlKqzCZf8qvQFL9chtLixSE9EDBwbcy1s+ufdPIomMLanCVq4uBZ3Lv+EQg iqy6ktm1fNhmB0N7avm/qqUQXs55dEI/D18a0//lImf8cVFaG1VhttSbGhGHxlASRdXM EVDw== MIME-Version: 1.0 References: In-Reply-To: From: Prathamesh Kulkarni Date: Mon, 03 Jun 2019 12:15:00 -0000 Message-ID: Subject: Re: [AArch64] [SVE] PR88837 - Poor vector construction code in VL-specific mode To: Prathamesh Kulkarni , gcc Patches , Richard Sandiford Content-Type: text/plain; charset="UTF-8" X-IsSubscribed: yes X-SW-Source: 2019-06/txt/msg00069.txt.bz2 On Mon, 3 Jun 2019 at 16:25, Richard Sandiford wrote: > > Prathamesh Kulkarni writes: > >> > diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp > >> > index 3bd6e815715..0ff0d8fb757 100644 > >> > --- a/gcc/testsuite/lib/target-supports.exp > >> > +++ b/gcc/testsuite/lib/target-supports.exp > >> > @@ -3846,6 +3846,10 @@ proc add_options_for_arm_neon_softfp_fp16 { flags } { > >> > return "$flags $et_arm_neon_softfp_fp16_flags" > >> > } > >> > > >> > +proc add_options_for_arm_sve { flags } { > >> > + return "$flags -march=armv8.2-a+sve" > >> > >> ...this I think we should avoid overriding the flags if they already > >> select SVE, so probably: > >> > >> if { ![istarget aarch64*-*-*] || [check_effective_target_aarch64_sve] } { > >> return "$flags" > >> } > >> > >> Should be "aarch64_sve" rather than "arm_sve". > >> > >> > +} > >> > + > >> > # Return 1 if this is an ARM target supporting the FP16 alternative > >> > # format. Some multilibs may be incompatible with the options needed. Also > >> > # set et_arm_neon_fp16_flags to the best options to add. > >> > @@ -4323,7 +4327,7 @@ proc check_effective_target_aarch64_sve_hw { } { > >> > asm volatile ("ptrue p0.b"); > >> > return 0; > >> > } > >> > - }] > >> > + } [ add_options_for_arm_sve "" ]] > >> > } > >> > > >> > # Return true if this is an AArch64 target that can run SVE code and > >> > @@ -4343,7 +4347,7 @@ proc aarch64_sve_hw_bits { bits } { > >> > __builtin_abort (); > >> > return 0; > >> > } > >> > - }]] > >> > + }] [add_options_for_arm_sve ""] ] > >> > } > >> > > >> > # Return true if this is an AArch64 target that can run SVE code and > >> > >> Think the formatting in the second is preferred over the first (i.e. > >> no spaces inside the [...]). > > Does the attached patch look OK ? > > Yes, thanks. (With a suitable changelog of course :-)) Thanks, committed to trunk. I filed following PR's based on the testsuite fallout: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90722 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90723 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90724 Thanks, Prathamesh > > Richard > > > > > Thanks, > > Prathamesh > >> > >> Thanks, > >> Richard > > > > diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp > > index 3bd6e815715..2b3e5d26004 100644 > > --- a/gcc/testsuite/lib/target-supports.exp > > +++ b/gcc/testsuite/lib/target-supports.exp > > @@ -3846,6 +3846,13 @@ proc add_options_for_arm_neon_softfp_fp16 { flags } { > > return "$flags $et_arm_neon_softfp_fp16_flags" > > } > > > > +proc add_options_for_aarch64_sve { flags } { > > + if { ![istarget aarch64*-*-*] || [check_effective_target_aarch64_sve] } { > > + return "$flags" > > + } > > + return "$flags -march=armv8.2-a+sve" > > +} > > + > > # Return 1 if this is an ARM target supporting the FP16 alternative > > # format. Some multilibs may be incompatible with the options needed. Also > > # set et_arm_neon_fp16_flags to the best options to add. > > @@ -4323,7 +4330,7 @@ proc check_effective_target_aarch64_sve_hw { } { > > asm volatile ("ptrue p0.b"); > > return 0; > > } > > - }] > > + } [add_options_for_aarch64_sve ""]] > > } > > > > # Return true if this is an AArch64 target that can run SVE code and > > @@ -4343,7 +4350,7 @@ proc aarch64_sve_hw_bits { bits } { > > __builtin_abort (); > > return 0; > > } > > - }]] > > + }] [add_options_for_aarch64_sve ""]] > > } > > > > # Return true if this is an AArch64 target that can run SVE code and