From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 32345 invoked by alias); 30 Mar 2012 00:13:37 -0000 Received: (qmail 32331 invoked by uid 22791); 30 Mar 2012 00:13:32 -0000 X-SWARE-Spam-Status: No, hits=-3.9 required=5.0 tests=AWL,BAYES_50,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,KHOP_RCVD_TRUST,KHOP_THREADED,RCVD_IN_DNSWL_LOW,RCVD_IN_HOSTKARMA_YE,TW_CP,TW_EB,TW_FN,TW_FX,TW_XF,T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail-ob0-f175.google.com (HELO mail-ob0-f175.google.com) (209.85.214.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 30 Mar 2012 00:13:14 +0000 Received: by obbwc20 with SMTP id wc20so183121obb.20 for ; Thu, 29 Mar 2012 17:13:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:x-system-of-record:x-gm-message-state:content-type :content-transfer-encoding; bh=Nvm1BbOWRNtuyP3MeN6SUKFxSzh1b1VvlsZ5rFfYDcM=; b=SMrRtmfy+t+DlzeS/bPmir4Gz4zIq7Ewuz2JPz9QEZbCCXYa0685o+Yn0SG1eqfKS9 oSaSGDCJlIFfXgczL593byXFeVNtWvzFY0TLDAO96kFyVXelOaky/6oZfUtbZAoMPTtq 1p3W62q/KEswlMUkwZA/1Xe6uIZn8y4VHuaF5/JFHxLsNZYggEylnSIUcVrBUXkNBm82 4UsfxOM1Zp6syo14OyEoUb9FUVfZEVBAcvKaeL2C8eDZp5vN5iFaO8aeqYHlLHi/1YqW Y/Ualwobuk+ywM1zopVnCgbkj2FrQxC4IQwAFr/yQvqH1G2zPlY0cvAJu5+iTKnBwXqU P+gg== Received: by 10.182.141.9 with SMTP id rk9mr117081obb.50.1333066393233; Thu, 29 Mar 2012 17:13:13 -0700 (PDT) MIME-Version: 1.0 Received: by 10.182.141.9 with SMTP id rk9mr117068obb.50.1333066393034; Thu, 29 Mar 2012 17:13:13 -0700 (PDT) Received: by 10.182.52.164 with HTTP; Thu, 29 Mar 2012 17:13:12 -0700 (PDT) In-Reply-To: References: <20120307004905.CEDCCB21B6@azwildcat.mtv.corp.google.com> Date: Fri, 30 Mar 2012 00:13:00 -0000 Message-ID: Subject: Re: Support for Runtime CPU type detection via builtins (issue5754058) From: Sriraman Tallam To: Richard Guenther Cc: Xinliang David Li , reply@codereview.appspotmail.com, gcc-patches@gcc.gnu.org X-System-Of-Record: true X-Gm-Message-State: ALoCoQkXj00Gm4tn9UCc8b6dbxTI5CZVxyBUJTN7Sc/wPi8cj43Qq79e/1OtwKxtvVPmQC25ETofkQG7l/vHvcol3vpMuOqvy+b6bAiQiBTgcaUdmIg4Y7/NcifPWFUHLsycUOTyRyIRihIu5sSx506Vkml1habgBw== Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2012-03/txt/msg01892.txt.bz2 Subject:Support for Runtime CPU type detection via builtins Hi, I have uploaded a new patch to only have two builtins : * __builtin_cpu_is ("") * __builtin_cpu_supports ("") apart from the cpu init builtin, __builtin_cpu_init. List of CPU names : * "amd" * "intel" * "atom" * "core2" * "corei7" * "nehalem" * "westmere" * "sandybridge" * "amdfam10h" * "barcelona" * "shanghai" * "istanbul" * "bdver1" * "bdver2" List of CPU features : * "cmov" * "mmx" * "popcnt" * "sse" * "sse2" * "sse3" * "ssse3" * "sse4.1" * "sse4.2" As an example, to check if CPU is corei7, call __builtin_cpu_is ("corei7") Comments? Thanks. On Mon, Mar 12, 2012 at 4:16 AM, Richard Guenther wrote: > On Thu, Mar 8, 2012 at 9:35 PM, Xinliang David Li wr= ote: >> On Wed, Mar 7, 2012 at 5:51 AM, Richard Guenther >> wrote: >>> On Wed, Mar 7, 2012 at 1:49 AM, Sriraman Tallam w= rote: >>>> Patch for CPU detection at run-time. >>>> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >>>> >>>> Patch for CPU detection at run-time, to be used in dispatching of >>>> multi-versioned functions. =A0 Please see this discussion: >>>> http://gcc.gnu.org/ml/gcc-patches/2011-08/msg01355.html >>>> when this patch for reviewed the last time. >>>> >>>> For more detailed description: >>>> http://gcc.gnu.org/ml/gcc/2012-03/msg00074.html >>>> >>>> One of the main concerns was about making CPU detection initialization= a >>>> constructor. The main point raised was about constructor ordering. I h= ave >>>> added a priority value to the CPU detection constructor to make it ver= y high >>>> priority so that it is guaranteed to fire before every constructor wit= hout >>>> an explicitly marked priority value of 101. =A0However, IFUNC initiali= zers >>>> will still fire before this constructor, so the cpu initialization rou= tine >>>> has to be explicitly called in such initializers for which I have adde= d a >>>> builtin: __builtin_cpu_init (). >>>> >>>> This patch adds the following new builtins: >>>> >>>> * __builtin_cpu_init >>>> * __builtin_cpu_supports_cmov >>>> * __builtin_cpu_supports_mmx >>>> * __builtin_cpu_supports_popcount >>>> * __builtin_cpu_supports_sse >>>> * __builtin_cpu_supports_sse2 >>>> * __builtin_cpu_supports_sse3 >>>> * __builtin_cpu_supports_ssse3 >>>> * __builtin_cpu_supports_sse4_1 >>>> * __builtin_cpu_supports_sse4_2 >>>> * __builtin_cpu_is_amd >>>> * __builtin_cpu_is_intel_atom >>>> * __builtin_cpu_is_intel_core2 >>>> * __builtin_cpu_is_intel >>>> * __builtin_cpu_is_intel_corei7 >>>> * __builtin_cpu_is_intel_corei7_nehalem >>>> * __builtin_cpu_is_intel_corei7_westmere >>>> * __builtin_cpu_is_intel_corei7_sandybridge >>>> * __builtin_cpu_is_amdfam10 >>>> * __builtin_cpu_is_amdfam10_barcelona >>>> * __builtin_cpu_is_amdfam10_shanghai >>>> * __builtin_cpu_is_amdfam10_istanbul >>>> * __builtin_cpu_is_amdfam15_bdver1 >>>> * __builtin_cpu_is_amdfam15_bdver2 >>> >>> I think the non-feature detection functions are not necessary at all. >> >> They are useful if compiler needs to do auto versioning based on cpu mod= el. >> >>> Builtin functions are not exactly cheap, nor is the scheme you invent >>> backward/forward compatible. =A0Instead, why not add a single builtin >>> function, __builtin_cpu_supports(const char *), and decode from >>> a comma-separated list of features? =A0Unknown features are simply >>> "not present". =A0So I can write code with only a single configure chec= k, >> >> This is a good idea. >> >> __builtin_is_cpu (const char* ); >> __builtin_cpu_supports (char char*); > > That looks good to me. > > Richard. > >> thanks, >> >> David >> >> >>> for __builtin_cpu_supports, and cater for future features or older comp= ilers. >>> >>> And of course that builtin would be even cross-platform. >>> >>> Implementation-wise I'll leave this to x86 maintainers to comment on. >>> >>> Richard. >>> >>>> >>>> =A0 =A0 =A0 =A0* config/i386/i386.c (build_struct_with_one_bit_fields)= : New function. >>>> =A0 =A0 =A0 =A0(make_var_decl): New function. >>>> =A0 =A0 =A0 =A0(get_field_from_struct): New function. >>>> =A0 =A0 =A0 =A0(fold_builtin_target): New function. >>>> =A0 =A0 =A0 =A0(ix86_fold_builtin): New function. >>>> =A0 =A0 =A0 =A0(ix86_expand_builtin): Expand new builtins by folding t= hem. >>>> =A0 =A0 =A0 =A0(make_platform_builtin): New functions. >>>> =A0 =A0 =A0 =A0(ix86_init_platform_type_builtins): Make the new builti= ns. >>>> =A0 =A0 =A0 =A0(ix86_init_builtins): Make new builtins to detect CPU t= ype. >>>> =A0 =A0 =A0 =A0(TARGET_FOLD_BUILTIN): New macro. >>>> =A0 =A0 =A0 =A0(IX86_BUILTIN_CPU_SUPPORTS_CMOV): New enum value. >>>> =A0 =A0 =A0 =A0(IX86_BUILTIN_CPU_SUPPORTS_MMX): New enum value. >>>> =A0 =A0 =A0 =A0(IX86_BUILTIN_CPU_SUPPORTS_POPCOUNT): New enum value. >>>> =A0 =A0 =A0 =A0(IX86_BUILTIN_CPU_SUPPORTS_SSE): New enum value. >>>> =A0 =A0 =A0 =A0(IX86_BUILTIN_CPU_SUPPORTS_SSE2): New enum value. >>>> =A0 =A0 =A0 =A0(IX86_BUILTIN_CPU_SUPPORTS_SSE3): New enum value. >>>> =A0 =A0 =A0 =A0(IX86_BUILTIN_CPU_SUPPORTS_SSSE3): New enum value. >>>> =A0 =A0 =A0 =A0(IX86_BUILTIN_CPU_SUPPORTS_SSE4_1): New enum value. >>>> =A0 =A0 =A0 =A0(IX86_BUILTIN_CPU_SUPPORTS_SSE4_2): New enum value. >>>> =A0 =A0 =A0 =A0(IX86_BUILTIN_CPU_INIT): New enum value. >>>> =A0 =A0 =A0 =A0(IX86_BUILTIN_CPU_IS_AMD): New enum value. >>>> =A0 =A0 =A0 =A0(IX86_BUILTIN_CPU_IS_INTEL): New enum value. >>>> =A0 =A0 =A0 =A0(IX86_BUILTIN_CPU_IS_INTEL_ATOM): New enum value. >>>> =A0 =A0 =A0 =A0(IX86_BUILTIN_CPU_IS_INTEL_CORE2): New enum value. >>>> =A0 =A0 =A0 =A0(IX86_BUILTIN_CPU_IS_INTEL_COREI7_NEHALEM): New enum va= lue. >>>> =A0 =A0 =A0 =A0(IX86_BUILTIN_CPU_IS_INTEL_COREI7_WESTMERE): New enum v= alue. >>>> =A0 =A0 =A0 =A0(IX86_BUILTIN_CPU_IS_INTEL_COREI7_SANDYBRIDGE): New enu= m value. >>>> =A0 =A0 =A0 =A0(IX86_BUILTIN_CPU_IS_AMDFAM10_BARCELONA): New enum valu= e. >>>> =A0 =A0 =A0 =A0(IX86_BUILTIN_CPU_IS_AMDFAM10_SHANGHAI): New enum value. >>>> =A0 =A0 =A0 =A0(IX86_BUILTIN_CPU_IS_AMDFAM10_ISTANBUL): New enum value. >>>> =A0 =A0 =A0 =A0(IX86_BUILTIN_CPU_IS_AMDFAM15H_BDVER1): New enum value. >>>> =A0 =A0 =A0 =A0(IX86_BUILTIN_CPU_IS_AMDFAM15H_BDVER2): New enum value. >>>> =A0 =A0 =A0 =A0* config/i386/i386-builtin-types.def: New function type. >>>> =A0 =A0 =A0 =A0* testsuite/gcc.target/builtin_target.c: New testcase. >>>> >>>> =A0 =A0 =A0 =A0* libgcc/config/i386/i386-cpuinfo.c: New file. >>>> =A0 =A0 =A0 =A0* libgcc/config/i386/t-cpuinfo: New file. >>>> =A0 =A0 =A0 =A0* libgcc/config.host: Include t-cpuinfo. >>>> =A0 =A0 =A0 =A0* libgcc/config/i386/libgcc-glibc.ver: Version symbols = __cpu_model >>>> =A0 =A0 =A0 =A0and __cpu_features. >>>> >>>> Index: libgcc/config.host >>>> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >>>> --- libgcc/config.host =A0(revision 184971) >>>> +++ libgcc/config.host =A0(working copy) >>>> @@ -1142,7 +1142,7 @@ i[34567]86-*-linux* | x86_64-*-linux* | \ >>>> =A0 i[34567]86-*-kfreebsd*-gnu | x86_64-*-kfreebsd*-gnu | \ >>>> =A0 i[34567]86-*-knetbsd*-gnu | \ >>>> =A0 i[34567]86-*-gnu*) >>>> - =A0 =A0 =A0 tmake_file=3D"${tmake_file} t-tls i386/t-linux" >>>> + =A0 =A0 =A0 tmake_file=3D"${tmake_file} t-tls i386/t-linux i386/t-cp= uinfo" >>>> =A0 =A0 =A0 =A0if test "$libgcc_cv_cfi" =3D "yes"; then >>>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0tmake_file=3D"${tmake_file} t-stack i38= 6/t-stack-i386" >>>> =A0 =A0 =A0 =A0fi >>>> Index: libgcc/config/i386/t-cpuinfo >>>> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >>>> --- libgcc/config/i386/t-cpuinfo =A0 =A0 =A0 =A0(revision 0) >>>> +++ libgcc/config/i386/t-cpuinfo =A0 =A0 =A0 =A0(revision 0) >>>> @@ -0,0 +1 @@ >>>> +LIB2ADD +=3D $(srcdir)/config/i386/i386-cpuinfo.c >>>> Index: libgcc/config/i386/i386-cpuinfo.c >>>> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >>>> --- libgcc/config/i386/i386-cpuinfo.c =A0 (revision 0) >>>> +++ libgcc/config/i386/i386-cpuinfo.c =A0 (revision 0) >>>> @@ -0,0 +1,306 @@ >>>> +/* Get CPU type and Features for x86 processors. >>>> + =A0 Copyright (C) 2011 Free Software Foundation, Inc. >>>> + =A0 Contributed by Sriraman Tallam (tmsriram@google.com) >>>> + >>>> +This file is part of GCC. >>>> + >>>> +GCC is free software; you can redistribute it and/or modify it under >>>> +the terms of the GNU General Public License as published by the Free >>>> +Software Foundation; either version 3, or (at your option) any later >>>> +version. >>>> + >>>> +GCC is distributed in the hope that it will be useful, but WITHOUT ANY >>>> +WARRANTY; without even the implied warranty of MERCHANTABILITY or >>>> +FITNESS FOR A PARTICULAR PURPOSE. =A0See the GNU General Public Licen= se >>>> +for more details. >>>> + >>>> +You should have received a copy of the GNU General Public License >>>> +along with GCC; see the file COPYING3. =A0If not see >>>> +. */ >>>> + >>>> +#include "cpuid.h" >>>> +#include "tsystem.h" >>>> + >>>> +int __cpu_indicator_init (void) __attribute__ ((constructor (101))); >>>> + >>>> +enum vendor_signatures >>>> +{ >>>> + =A0SIG_INTEL =3D =A00x756e6547 /* Genu */, >>>> + =A0SIG_AMD =3D =A0 =A00x68747541 /* Auth */ >>>> +}; >>>> + >>>> +/* ISA Features supported. */ >>>> + >>>> +struct __processor_features >>>> +{ >>>> + =A0unsigned int __cpu_cmov : 1; >>>> + =A0unsigned int __cpu_mmx : 1; >>>> + =A0unsigned int __cpu_popcnt : 1; >>>> + =A0unsigned int __cpu_sse : 1; >>>> + =A0unsigned int __cpu_sse2 : 1; >>>> + =A0unsigned int __cpu_sse3 : 1; >>>> + =A0unsigned int __cpu_ssse3 : 1; >>>> + =A0unsigned int __cpu_sse4_1 : 1; >>>> + =A0unsigned int __cpu_sse4_2 : 1; >>>> +} __cpu_features; >>>> + >>>> +/* Processor Model. */ >>>> + >>>> +struct __processor_model >>>> +{ >>>> + =A0/* Vendor. */ >>>> + =A0unsigned int __cpu_is_amd : 1; >>>> + =A0unsigned int __cpu_is_intel : 1; >>>> + =A0/* CPU type. */ >>>> + =A0unsigned int __cpu_is_intel_atom : 1; >>>> + =A0unsigned int __cpu_is_intel_core2 : 1; >>>> + =A0unsigned int __cpu_is_intel_corei7 : 1; >>>> + =A0unsigned int __cpu_is_intel_corei7_nehalem : 1; >>>> + =A0unsigned int __cpu_is_intel_corei7_westmere : 1; >>>> + =A0unsigned int __cpu_is_intel_corei7_sandybridge : 1; >>>> + =A0unsigned int __cpu_is_amdfam10h : 1; >>>> + =A0unsigned int __cpu_is_amdfam10h_barcelona : 1; >>>> + =A0unsigned int __cpu_is_amdfam10h_shanghai : 1; >>>> + =A0unsigned int __cpu_is_amdfam10h_istanbul : 1; >>>> + =A0unsigned int __cpu_is_amdfam15h_bdver1 : 1; >>>> + =A0unsigned int __cpu_is_amdfam15h_bdver2 : 1; >>>> +} __cpu_model; >>>> + >>>> +/* Get the specific type of AMD CPU. =A0*/ >>>> + >>>> +static void >>>> +get_amd_cpu (unsigned int family, unsigned int model) >>>> +{ >>>> + =A0switch (family) >>>> + =A0 =A0{ >>>> + =A0 =A0/* AMD Family 10h. =A0*/ >>>> + =A0 =A0case 0x10: >>>> + =A0 =A0 =A0switch (model) >>>> + =A0 =A0 =A0 { >>>> + =A0 =A0 =A0 case 0x2: >>>> + =A0 =A0 =A0 =A0 /* Barcelona. =A0*/ >>>> + =A0 =A0 =A0 =A0 __cpu_model.__cpu_is_amdfam10h =3D 1; >>>> + =A0 =A0 =A0 =A0 __cpu_model.__cpu_is_amdfam10h_barcelona =3D 1; >>>> + =A0 =A0 =A0 =A0 break; >>>> + =A0 =A0 =A0 case 0x4: >>>> + =A0 =A0 =A0 =A0 /* Shanghai. =A0*/ >>>> + =A0 =A0 =A0 =A0 __cpu_model.__cpu_is_amdfam10h =3D 1; >>>> + =A0 =A0 =A0 =A0 __cpu_model.__cpu_is_amdfam10h_shanghai =3D 1; >>>> + =A0 =A0 =A0 =A0 break; >>>> + =A0 =A0 =A0 case 0x8: >>>> + =A0 =A0 =A0 =A0 /* Istanbul. =A0*/ >>>> + =A0 =A0 =A0 =A0 __cpu_model.__cpu_is_amdfam10h =3D 1; >>>> + =A0 =A0 =A0 =A0 __cpu_model.__cpu_is_amdfam10h_istanbul =3D 1; >>>> + =A0 =A0 =A0 =A0 break; >>>> + =A0 =A0 =A0 default: >>>> + =A0 =A0 =A0 =A0 break; >>>> + =A0 =A0 =A0 } >>>> + =A0 =A0 =A0break; >>>> + =A0 =A0/* AMD Family 15h. =A0*/ >>>> + =A0 =A0case 0x15: >>>> + =A0 =A0 =A0/* Bulldozer version 1. =A0*/ >>>> + =A0 =A0 =A0if (model >=3D 0 && model <=3D 0xf) >>>> + =A0 =A0 =A0 =A0__cpu_model.__cpu_is_amdfam15h_bdver1 =3D 1; >>>> + =A0 =A0 =A0/* Bulldozer version 2. =A0*/ >>>> + =A0 =A0 =A0if (model >=3D 0x10 && model <=3D 0x1f) >>>> + =A0 =A0 =A0 =A0__cpu_model.__cpu_is_amdfam15h_bdver2 =3D 1; >>>> + =A0 =A0 =A0break; >>>> + =A0 =A0default: >>>> + =A0 =A0 =A0break; >>>> + =A0 =A0} >>>> +} >>>> + >>>> +/* Get the specific type of Intel CPU. =A0*/ >>>> + >>>> +static void >>>> +get_intel_cpu (unsigned int family, unsigned int model, unsigned int = brand_id) >>>> +{ >>>> + =A0/* Parse family and model only if brand ID is 0. */ >>>> + =A0if (brand_id =3D=3D 0) >>>> + =A0 =A0{ >>>> + =A0 =A0 =A0switch (family) >>>> + =A0 =A0 =A0 { >>>> + =A0 =A0 =A0 case 0x5: >>>> + =A0 =A0 =A0 =A0 /* Pentium. =A0*/ >>>> + =A0 =A0 =A0 =A0 break; >>>> + =A0 =A0 =A0 case 0x6: >>>> + =A0 =A0 =A0 =A0 switch (model) >>>> + =A0 =A0 =A0 =A0 =A0 { >>>> + =A0 =A0 =A0 =A0 =A0 case 0x1c: >>>> + =A0 =A0 =A0 =A0 =A0 case 0x26: >>>> + =A0 =A0 =A0 =A0 =A0 =A0 /* Atom. =A0*/ >>>> + =A0 =A0 =A0 =A0 =A0 =A0 __cpu_model.__cpu_is_intel_atom =3D 1; >>>> + =A0 =A0 =A0 =A0 =A0 =A0 break; >>>> + =A0 =A0 =A0 =A0 =A0 case 0x1a: >>>> + =A0 =A0 =A0 =A0 =A0 case 0x1e: >>>> + =A0 =A0 =A0 =A0 =A0 case 0x1f: >>>> + =A0 =A0 =A0 =A0 =A0 case 0x2e: >>>> + =A0 =A0 =A0 =A0 =A0 =A0 /* Nehalem. =A0*/ >>>> + =A0 =A0 =A0 =A0 =A0 =A0 __cpu_model.__cpu_is_intel_corei7 =3D 1; >>>> + =A0 =A0 =A0 =A0 =A0 =A0 __cpu_model.__cpu_is_intel_corei7_nehalem = =3D 1; >>>> + =A0 =A0 =A0 =A0 =A0 =A0 break; >>>> + =A0 =A0 =A0 =A0 =A0 case 0x25: >>>> + =A0 =A0 =A0 =A0 =A0 case 0x2c: >>>> + =A0 =A0 =A0 =A0 =A0 case 0x2f: >>>> + =A0 =A0 =A0 =A0 =A0 =A0 /* Westmere. =A0*/ >>>> + =A0 =A0 =A0 =A0 =A0 =A0 __cpu_model.__cpu_is_intel_corei7 =3D 1; >>>> + =A0 =A0 =A0 =A0 =A0 =A0 __cpu_model.__cpu_is_intel_corei7_westmere = =3D 1; >>>> + =A0 =A0 =A0 =A0 =A0 =A0 break; >>>> + =A0 =A0 =A0 =A0 =A0 case 0x2a: >>>> + =A0 =A0 =A0 =A0 =A0 =A0 /* Sandy Bridge. =A0*/ >>>> + =A0 =A0 =A0 =A0 =A0 =A0 __cpu_model.__cpu_is_intel_corei7 =3D 1; >>>> + =A0 =A0 =A0 =A0 =A0 =A0 __cpu_model.__cpu_is_intel_corei7_sandybridg= e =3D 1; >>>> + =A0 =A0 =A0 =A0 =A0 =A0 break; >>>> + =A0 =A0 =A0 =A0 =A0 case 0x17: >>>> + =A0 =A0 =A0 =A0 =A0 case 0x1d: >>>> + =A0 =A0 =A0 =A0 =A0 =A0 /* Penryn. =A0*/ >>>> + =A0 =A0 =A0 =A0 =A0 case 0x0f: >>>> + =A0 =A0 =A0 =A0 =A0 =A0 /* Merom. =A0*/ >>>> + =A0 =A0 =A0 =A0 =A0 =A0 __cpu_model.__cpu_is_intel_core2 =3D 1; >>>> + =A0 =A0 =A0 =A0 =A0 =A0 break; >>>> + =A0 =A0 =A0 =A0 =A0 default: >>>> + =A0 =A0 =A0 =A0 =A0 =A0 break; >>>> + =A0 =A0 =A0 =A0 =A0 } >>>> + =A0 =A0 =A0 =A0 break; >>>> + =A0 =A0 =A0 default: >>>> + =A0 =A0 =A0 =A0 /* We have no idea. =A0*/ >>>> + =A0 =A0 =A0 =A0 break; >>>> + =A0 =A0 =A0 } >>>> + =A0 =A0} >>>> +} >>>> + >>>> +static void >>>> +get_available_features (unsigned int ecx, unsigned int edx) >>>> +{ >>>> + =A0__cpu_features.__cpu_cmov =3D (edx & bit_CMOV) ? 1 : 0; >>>> + =A0__cpu_features.__cpu_mmx =3D (edx & bit_MMX) ? 1 : 0; >>>> + =A0__cpu_features.__cpu_sse =3D (edx & bit_SSE) ? 1 : 0; >>>> + =A0__cpu_features.__cpu_sse2 =3D (edx & bit_SSE2) ? 1 : 0; >>>> + =A0__cpu_features.__cpu_popcnt =3D (ecx & bit_POPCNT) ? 1 : 0; >>>> + =A0__cpu_features.__cpu_sse3 =3D (ecx & bit_SSE3) ? 1 : 0; >>>> + =A0__cpu_features.__cpu_ssse3 =3D (ecx & bit_SSSE3) ? 1 : 0; >>>> + =A0__cpu_features.__cpu_sse4_1 =3D (ecx & bit_SSE4_1) ? 1 : 0; >>>> + =A0__cpu_features.__cpu_sse4_2 =3D (ecx & bit_SSE4_2) ? 1 : 0; >>>> +} >>>> + >>>> + >>>> +/* Sanity check for the vendor and cpu type flags. =A0*/ >>>> + >>>> +static int >>>> +sanity_check (void) >>>> +{ >>>> + =A0unsigned int one_type =3D 0; >>>> + >>>> + =A0/* Vendor cannot be Intel and AMD. */ >>>> + =A0gcc_assert((__cpu_model.__cpu_is_intel =3D=3D 0) >>>> + =A0 =A0 =A0 =A0 =A0 =A0 || (__cpu_model.__cpu_is_amd =3D=3D 0)); >>>> + >>>> + =A0/* Only one CPU type can be set. */ >>>> + =A0one_type =3D (__cpu_model.__cpu_is_intel_atom >>>> + =A0 =A0 =A0 =A0 =A0 =A0 + __cpu_model.__cpu_is_intel_core2 >>>> + =A0 =A0 =A0 =A0 =A0 =A0 + __cpu_model.__cpu_is_intel_corei7_nehalem >>>> + =A0 =A0 =A0 =A0 =A0 =A0 + __cpu_model.__cpu_is_intel_corei7_westmere >>>> + =A0 =A0 =A0 =A0 =A0 =A0 + __cpu_model.__cpu_is_intel_corei7_sandybri= dge >>>> + =A0 =A0 =A0 =A0 =A0 =A0 + __cpu_model.__cpu_is_amdfam10h_barcelona >>>> + =A0 =A0 =A0 =A0 =A0 =A0 + __cpu_model.__cpu_is_amdfam10h_shanghai >>>> + =A0 =A0 =A0 =A0 =A0 =A0 + __cpu_model.__cpu_is_amdfam10h_istanbul >>>> + =A0 =A0 =A0 =A0 =A0 =A0 + __cpu_model.__cpu_is_amdfam15h_bdver1 >>>> + =A0 =A0 =A0 =A0 =A0 =A0 + __cpu_model.__cpu_is_amdfam15h_bdver2); >>>> + >>>> + =A0gcc_assert (one_type <=3D 1); >>>> + =A0return 0; >>>> +} >>>> + >>>> +/* A noinline function calling __get_cpuid. Having many calls to >>>> + =A0 cpuid in one function in 32-bit mode causes GCC to complain: >>>> + =A0 "can=92t find a register in class =91CLOBBERED_REGS=92". =A0This= is >>>> + =A0 related to PR rtl-optimization 44174. */ >>>> + >>>> +static int __attribute__ ((noinline)) >>>> +__get_cpuid_output (unsigned int __level, >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 unsigned int *__eax, unsigned in= t *__ebx, >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 unsigned int *__ecx, unsigned in= t *__edx) >>>> +{ >>>> + =A0return __get_cpuid (__level, __eax, __ebx, __ecx, __edx); >>>> +} >>>> + >>>> + >>>> +/* A constructor function that is sets __cpu_model and __cpu_features= with >>>> + =A0 the right values. =A0This needs to run only once. =A0This constr= uctor is >>>> + =A0 given the highest priority and it should run before constructors= without >>>> + =A0 the priority set. =A0However, it still runs after ifunc initiali= zers and >>>> + =A0 needs to be called explicitly there. =A0*/ >>>> + >>>> +int __attribute__ ((constructor (101))) >>>> +__cpu_indicator_init (void) >>>> +{ >>>> + =A0unsigned int eax, ebx, ecx, edx; >>>> + >>>> + =A0int max_level =3D 5; >>>> + =A0unsigned int vendor; >>>> + =A0unsigned int model, family, brand_id; >>>> + =A0unsigned int extended_model, extended_family; >>>> + =A0static int called =3D 0; >>>> + >>>> + =A0/* This function needs to run just once. =A0*/ >>>> + =A0if (called) >>>> + =A0 =A0return 0; >>>> + =A0else >>>> + =A0 =A0called =3D 1; >>>> + >>>> + =A0/* Assume cpuid insn present. Run in level 0 to get vendor id. */ >>>> + =A0if (!__get_cpuid_output (0, &eax, &ebx, &ecx, &edx)) >>>> + =A0 =A0return -1; >>>> + >>>> + =A0vendor =3D ebx; >>>> + =A0max_level =3D eax; >>>> + >>>> + =A0if (max_level < 1) >>>> + =A0 =A0return -1; >>>> + >>>> + =A0if (!__get_cpuid_output (1, &eax, &ebx, &ecx, &edx)) >>>> + =A0 =A0return -1; >>>> + >>>> + =A0model =3D (eax >> 4) & 0x0f; >>>> + =A0family =3D (eax >> 8) & 0x0f; >>>> + =A0brand_id =3D ebx & 0xff; >>>> + =A0extended_model =3D (eax >> 12) & 0xf0; >>>> + =A0extended_family =3D (eax >> 20) & 0xff; >>>> + >>>> + =A0if (vendor =3D=3D SIG_INTEL) >>>> + =A0 =A0{ >>>> + =A0 =A0 =A0/* Adjust model and family for Intel CPUS. */ >>>> + =A0 =A0 =A0if (family =3D=3D 0x0f) >>>> + =A0 =A0 =A0 { >>>> + =A0 =A0 =A0 =A0 family +=3D extended_family; >>>> + =A0 =A0 =A0 =A0 model +=3D extended_model; >>>> + =A0 =A0 =A0 } >>>> + =A0 =A0 =A0else if (family =3D=3D 0x06) >>>> + =A0 =A0 =A0 model +=3D extended_model; >>>> + >>>> + =A0 =A0 =A0/* Get CPU type. =A0*/ >>>> + =A0 =A0 =A0__cpu_model.__cpu_is_intel =3D 1; >>>> + =A0 =A0 =A0get_intel_cpu (family, model, brand_id); >>>> + =A0 =A0} >>>> + >>>> + =A0if (vendor =3D=3D SIG_AMD) >>>> + =A0 =A0{ >>>> + =A0 =A0 =A0/* Adjust model and family for AMD CPUS. */ >>>> + =A0 =A0 =A0if (family =3D=3D 0x0f) >>>> + =A0 =A0 =A0 { >>>> + =A0 =A0 =A0 =A0 family +=3D extended_family; >>>> + =A0 =A0 =A0 =A0 model +=3D (extended_model << 4); >>>> + =A0 =A0 =A0 } >>>> + >>>> + =A0 =A0 =A0/* Get CPU type. =A0*/ >>>> + =A0 =A0 =A0__cpu_model.__cpu_is_amd =3D 1; >>>> + =A0 =A0 =A0get_amd_cpu (family, model); >>>> + =A0 =A0} >>>> + >>>> + =A0/* Find available features. */ >>>> + =A0get_available_features (ecx, edx); >>>> + >>>> + =A0sanity_check (); >>>> + >>>> + =A0return 0; >>>> +} >>>> Index: libgcc/config/i386/libgcc-glibc.ver >>>> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >>>> --- libgcc/config/i386/libgcc-glibc.ver (revision 184971) >>>> +++ libgcc/config/i386/libgcc-glibc.ver (working copy) >>>> @@ -147,6 +147,11 @@ GCC_4.3.0 { >>>> =A0 __trunctfxf2 >>>> =A0 __unordtf2 >>>> =A0} >>>> + >>>> +GCC_4.8.0 { >>>> + =A0__cpu_model >>>> + =A0__cpu_features >>>> +} >>>> =A0%else >>>> =A0GCC_4.4.0 { >>>> =A0 __addtf3 >>>> @@ -183,4 +188,9 @@ GCC_4.4.0 { >>>> =A0GCC_4.5.0 { >>>> =A0 __extendxftf2 >>>> =A0} >>>> + >>>> +GCC_4.8.0 { >>>> + =A0__cpu_model >>>> + =A0__cpu_features >>>> +} >>>> =A0%endif >>>> Index: gcc/config/i386/i386-builtin-types.def >>>> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >>>> --- gcc/config/i386/i386-builtin-types.def =A0 =A0 =A0(revision 184971) >>>> +++ gcc/config/i386/i386-builtin-types.def =A0 =A0 =A0(working copy) >>>> @@ -143,6 +143,7 @@ DEF_FUNCTION_TYPE (UINT64) >>>> =A0DEF_FUNCTION_TYPE (UNSIGNED) >>>> =A0DEF_FUNCTION_TYPE (VOID) >>>> =A0DEF_FUNCTION_TYPE (PVOID) >>>> +DEF_FUNCTION_TYPE (INT) >>>> >>>> =A0DEF_FUNCTION_TYPE (FLOAT, FLOAT) >>>> =A0DEF_FUNCTION_TYPE (FLOAT128, FLOAT128) >>>> Index: gcc/config/i386/i386.c >>>> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >>>> --- gcc/config/i386/i386.c =A0 =A0 =A0(revision 184971) >>>> +++ gcc/config/i386/i386.c =A0 =A0 =A0(working copy) >>>> @@ -25637,6 +25637,33 @@ enum ix86_builtins >>>> =A0 /* CFString built-in for darwin */ >>>> =A0 IX86_BUILTIN_CFSTRING, >>>> >>>> + =A0/* Builtins to get CPU features. */ >>>> + =A0IX86_BUILTIN_CPU_SUPPORTS_CMOV, >>>> + =A0IX86_BUILTIN_CPU_SUPPORTS_MMX, >>>> + =A0IX86_BUILTIN_CPU_SUPPORTS_POPCOUNT, >>>> + =A0IX86_BUILTIN_CPU_SUPPORTS_SSE, >>>> + =A0IX86_BUILTIN_CPU_SUPPORTS_SSE2, >>>> + =A0IX86_BUILTIN_CPU_SUPPORTS_SSE3, >>>> + =A0IX86_BUILTIN_CPU_SUPPORTS_SSSE3, >>>> + =A0IX86_BUILTIN_CPU_SUPPORTS_SSE4_1, >>>> + =A0IX86_BUILTIN_CPU_SUPPORTS_SSE4_2, >>>> + =A0/* Builtins to get CPU type. */ >>>> + =A0IX86_BUILTIN_CPU_INIT, >>>> + =A0IX86_BUILTIN_CPU_IS_AMD, >>>> + =A0IX86_BUILTIN_CPU_IS_INTEL, >>>> + =A0IX86_BUILTIN_CPU_IS_INTEL_ATOM, >>>> + =A0IX86_BUILTIN_CPU_IS_INTEL_CORE2, >>>> + =A0IX86_BUILTIN_CPU_IS_INTEL_COREI7, >>>> + =A0IX86_BUILTIN_CPU_IS_INTEL_COREI7_NEHALEM, >>>> + =A0IX86_BUILTIN_CPU_IS_INTEL_COREI7_WESTMERE, >>>> + =A0IX86_BUILTIN_CPU_IS_INTEL_COREI7_SANDYBRIDGE, >>>> + =A0IX86_BUILTIN_CPU_IS_AMDFAM10H, >>>> + =A0IX86_BUILTIN_CPU_IS_AMDFAM10H_BARCELONA, >>>> + =A0IX86_BUILTIN_CPU_IS_AMDFAM10H_SHANGHAI, >>>> + =A0IX86_BUILTIN_CPU_IS_AMDFAM10H_ISTANBUL, >>>> + =A0IX86_BUILTIN_CPU_IS_AMDFAM15H_BDVER1, >>>> + =A0IX86_BUILTIN_CPU_IS_AMDFAM15H_BDVER2, >>>> + >>>> =A0 IX86_BUILTIN_MAX >>>> =A0}; >>>> >>>> @@ -27446,6 +27473,593 @@ ix86_init_mmx_sse_builtins (void) >>>> =A0 =A0 } >>>> =A0} >>>> >>>> +/* Returns a struct type with name NAME and number of fields equal to >>>> + =A0 NUM_FIELDS. =A0Each field is a unsigned int bit field of length = 1 bit. */ >>>> + >>>> +static tree >>>> +build_struct_with_one_bit_fields (int num_fields, const char *name) >>>> +{ >>>> + =A0int i; >>>> + =A0char field_name [10]; >>>> + =A0tree field =3D NULL_TREE, field_chain =3D NULL_TREE; >>>> + =A0tree type =3D make_node (RECORD_TYPE); >>>> + >>>> + =A0strcpy (field_name, "k_field"); >>>> + >>>> + =A0for (i =3D 0; i < num_fields; i++) >>>> + =A0 =A0{ >>>> + =A0 =A0 =A0/* Name the fields, 0_field, 1_field, ... */ >>>> + =A0 =A0 =A0field_name [0] =3D '0' + i; >>>> + =A0 =A0 =A0field =3D build_decl (UNKNOWN_LOCATION, FIELD_DECL, >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 get_identifier (fiel= d_name), unsigned_type_node); >>>> + =A0 =A0 =A0DECL_BIT_FIELD (field) =3D 1; >>>> + =A0 =A0 =A0DECL_SIZE (field) =3D bitsize_one_node; >>>> + =A0 =A0 =A0if (field_chain !=3D NULL_TREE) >>>> + =A0 =A0 =A0 DECL_CHAIN (field) =3D field_chain; >>>> + =A0 =A0 =A0field_chain =3D field; >>>> + =A0 =A0} >>>> + =A0finish_builtin_struct (type, name, field_chain, NULL_TREE); >>>> + =A0return type; >>>> +} >>>> + >>>> +/* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */ >>>> + >>>> +static tree >>>> +make_var_decl (tree type, const char *name) >>>> +{ >>>> + =A0tree new_decl; >>>> + =A0struct varpool_node *vnode; >>>> + >>>> + =A0new_decl =3D build_decl (UNKNOWN_LOCATION, >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0VAR_DECL, >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0get_identifier(name), >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0type); >>>> + >>>> + =A0DECL_EXTERNAL (new_decl) =3D 1; >>>> + =A0TREE_STATIC (new_decl) =3D 1; >>>> + =A0TREE_PUBLIC (new_decl) =3D 1; >>>> + =A0DECL_INITIAL (new_decl) =3D 0; >>>> + =A0DECL_ARTIFICIAL (new_decl) =3D 0; >>>> + =A0DECL_PRESERVE_P (new_decl) =3D 1; >>>> + >>>> + =A0make_decl_one_only (new_decl, DECL_ASSEMBLER_NAME (new_decl)); >>>> + =A0assemble_variable (new_decl, 0, 0, 0); >>>> + >>>> + =A0vnode =3D varpool_node (new_decl); >>>> + =A0gcc_assert (vnode !=3D NULL); >>>> + =A0/* Set finalized to 1, otherwise it asserts in function "write_sy= mbol" in >>>> + =A0 =A0 lto-streamer-out.c. */ >>>> + =A0vnode->finalized =3D 1; >>>> + >>>> + =A0return new_decl; >>>> +} >>>> + >>>> +/* Traverses the chain of fields in STRUCT_TYPE and returns the FIELD= _NUM >>>> + =A0 numbered field. */ >>>> + >>>> +static tree >>>> +get_field_from_struct (tree struct_type, int field_num) >>>> +{ >>>> + =A0int i; >>>> + =A0tree field =3D TYPE_FIELDS (struct_type); >>>> + >>>> + =A0for (i =3D 0; i < field_num; i++, field =3D DECL_CHAIN(field)) >>>> + =A0 =A0{ >>>> + =A0 =A0 =A0gcc_assert (field !=3D NULL_TREE); >>>> + =A0 =A0} >>>> + >>>> + =A0return field; >>>> +} >>>> + >>>> +/* FNDECL is a __builtin_cpu_* call that is folded into an integer de= fined >>>> + =A0 in libgcc/config/i386/i386-cpuinfo.c */ >>>> + >>>> +static tree >>>> +fold_builtin_cpu (enum ix86_builtins fn_code) >>>> +{ >>>> + =A0/* This is the order of bit-fields in __processor_features in >>>> + =A0 =A0 i386-cpuinfo.c */ >>>> + =A0enum processor_features >>>> + =A0{ >>>> + =A0 =A0F_CMOV =3D 0, >>>> + =A0 =A0F_MMX, >>>> + =A0 =A0F_POPCNT, >>>> + =A0 =A0F_SSE, >>>> + =A0 =A0F_SSE2, >>>> + =A0 =A0F_SSE3, >>>> + =A0 =A0F_SSSE3, >>>> + =A0 =A0F_SSE4_1, >>>> + =A0 =A0F_SSE4_2, >>>> + =A0 =A0F_MAX >>>> + =A0}; >>>> + >>>> + =A0/* This is the order of bit-fields in __processor_model in >>>> + =A0 =A0 i386-cpuinfo.c */ >>>> + =A0enum processor_model >>>> + =A0{ >>>> + =A0 =A0M_AMD =3D 0, >>>> + =A0 =A0M_INTEL, >>>> + =A0 =A0M_INTEL_ATOM, >>>> + =A0 =A0M_INTEL_CORE2, >>>> + =A0 =A0M_INTEL_COREI7, >>>> + =A0 =A0M_INTEL_COREI7_NEHALEM, >>>> + =A0 =A0M_INTEL_COREI7_WESTMERE, >>>> + =A0 =A0M_INTEL_COREI7_SANDYBRIDGE, >>>> + =A0 =A0M_AMDFAM10H, >>>> + =A0 =A0M_AMDFAM10H_BARCELONA, >>>> + =A0 =A0M_AMDFAM10H_SHANGHAI, >>>> + =A0 =A0M_AMDFAM10H_ISTANBUL, >>>> + =A0 =A0M_AMDFAM15H_BDVER1, >>>> + =A0 =A0M_AMDFAM15H_BDVER2, >>>> + =A0 =A0M_MAX >>>> + =A0}; >>>> + >>>> + =A0static tree __processor_features_type =3D NULL_TREE; >>>> + =A0static tree __cpu_features_var =3D NULL_TREE; >>>> + =A0static tree __processor_model_type =3D NULL_TREE; >>>> + =A0static tree __cpu_model_var =3D NULL_TREE; >>>> + =A0static tree field; >>>> + =A0static tree which_struct; >>>> + >>>> + =A0if (__processor_features_type =3D=3D NULL_TREE) >>>> + =A0 =A0__processor_features_type =3D build_struct_with_one_bit_field= s (F_MAX, >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 "__p= rocessor_features"); >>>> + >>>> + =A0if (__processor_model_type =3D=3D NULL_TREE) >>>> + =A0 =A0__processor_model_type =3D build_struct_with_one_bit_fields (= M_MAX, >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 "__p= rocessor_model"); >>>> + >>>> + =A0if (__cpu_features_var =3D=3D NULL_TREE) >>>> + =A0 =A0__cpu_features_var =3D make_var_decl (__processor_features_ty= pe, >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 "__cpu_features"); >>>> + >>>> + =A0if (__cpu_model_var =3D=3D NULL_TREE) >>>> + =A0 =A0__cpu_model_var =3D make_var_decl (__processor_model_type, >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0"__cpu_model"); >>>> + >>>> + =A0/* Look at the code to identify the field requested. */ >>>> + =A0switch (fn_code) >>>> + =A0 =A0{ >>>> + =A0 =A0case IX86_BUILTIN_CPU_SUPPORTS_CMOV: >>>> + =A0 =A0 =A0field =3D get_field_from_struct (__processor_features_typ= e, F_CMOV); >>>> + =A0 =A0 =A0which_struct =3D __cpu_features_var; >>>> + =A0 =A0 =A0break; >>>> + =A0 =A0case IX86_BUILTIN_CPU_SUPPORTS_MMX: >>>> + =A0 =A0 =A0field =3D get_field_from_struct (__processor_features_typ= e, F_MMX); >>>> + =A0 =A0 =A0which_struct =3D __cpu_features_var; >>>> + =A0 =A0 =A0break; >>>> + =A0 =A0case IX86_BUILTIN_CPU_SUPPORTS_POPCOUNT: >>>> + =A0 =A0 =A0field =3D get_field_from_struct (__processor_features_typ= e, F_POPCNT); >>>> + =A0 =A0 =A0which_struct =3D __cpu_features_var; >>>> + =A0 =A0 =A0break; >>>> + =A0 =A0case IX86_BUILTIN_CPU_SUPPORTS_SSE: >>>> + =A0 =A0 =A0field =3D get_field_from_struct (__processor_features_typ= e, F_SSE); >>>> + =A0 =A0 =A0which_struct =3D __cpu_features_var; >>>> + =A0 =A0 =A0break; >>>> + =A0 =A0case IX86_BUILTIN_CPU_SUPPORTS_SSE2: >>>> + =A0 =A0 =A0field =3D get_field_from_struct (__processor_features_typ= e, F_SSE2); >>>> + =A0 =A0 =A0which_struct =3D __cpu_features_var; >>>> + =A0 =A0 =A0break; >>>> + =A0 =A0case IX86_BUILTIN_CPU_SUPPORTS_SSE3: >>>> + =A0 =A0 =A0field =3D get_field_from_struct (__processor_features_typ= e, F_SSE3); >>>> + =A0 =A0 =A0which_struct =3D __cpu_features_var; >>>> + =A0 =A0 =A0break; >>>> + =A0 =A0case IX86_BUILTIN_CPU_SUPPORTS_SSSE3: >>>> + =A0 =A0 =A0field =3D get_field_from_struct (__processor_features_typ= e, F_SSSE3); >>>> + =A0 =A0 =A0which_struct =3D __cpu_features_var; >>>> + =A0 =A0 =A0break; >>>> + =A0 =A0case IX86_BUILTIN_CPU_SUPPORTS_SSE4_1: >>>> + =A0 =A0 =A0field =3D get_field_from_struct (__processor_features_typ= e, F_SSE4_1); >>>> + =A0 =A0 =A0which_struct =3D __cpu_features_var; >>>> + =A0 =A0 =A0break; >>>> + =A0 =A0case IX86_BUILTIN_CPU_SUPPORTS_SSE4_2: >>>> + =A0 =A0 =A0field =3D get_field_from_struct (__processor_features_typ= e, F_SSE4_2); >>>> + =A0 =A0 =A0which_struct =3D __cpu_features_var; >>>> + =A0 =A0 =A0break; >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_AMD: >>>> + =A0 =A0 =A0field =3D get_field_from_struct (__processor_model_type, = M_AMD); >>>> + =A0 =A0 =A0which_struct =3D __cpu_model_var; >>>> + =A0 =A0 =A0break; >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_INTEL: >>>> + =A0 =A0 =A0field =3D get_field_from_struct (__processor_model_type, = M_INTEL); >>>> + =A0 =A0 =A0which_struct =3D __cpu_model_var; >>>> + =A0 =A0 =A0break; >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_INTEL_ATOM: >>>> + =A0 =A0 =A0field =3D get_field_from_struct (__processor_model_type, = M_INTEL_ATOM); >>>> + =A0 =A0 =A0which_struct =3D __cpu_model_var; >>>> + =A0 =A0 =A0break; >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_INTEL_CORE2: >>>> + =A0 =A0 =A0field =3D get_field_from_struct (__processor_model_type, = M_INTEL_CORE2); >>>> + =A0 =A0 =A0which_struct =3D __cpu_model_var; >>>> + =A0 =A0 =A0break; >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_INTEL_COREI7: >>>> + =A0 =A0 =A0field =3D get_field_from_struct (__processor_model_type, >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0M_INTEL_COREI7); >>>> + =A0 =A0 =A0which_struct =3D __cpu_model_var; >>>> + =A0 =A0 =A0break; >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_INTEL_COREI7_NEHALEM: >>>> + =A0 =A0 =A0field =3D get_field_from_struct (__processor_model_type, >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0M_INTEL_COREI7_NEHALEM); >>>> + =A0 =A0 =A0which_struct =3D __cpu_model_var; >>>> + =A0 =A0 =A0break; >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_INTEL_COREI7_WESTMERE: >>>> + =A0 =A0 =A0field =3D get_field_from_struct (__processor_model_type, >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0M_INTEL_COREI7_WESTMERE); >>>> + =A0 =A0 =A0which_struct =3D __cpu_model_var; >>>> + =A0 =A0 =A0break; >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_INTEL_COREI7_SANDYBRIDGE: >>>> + =A0 =A0 =A0field =3D get_field_from_struct (__processor_model_type, >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0M_INTEL_COREI7_SANDYBRIDGE); >>>> + =A0 =A0 =A0which_struct =3D __cpu_model_var; >>>> + =A0 =A0 =A0break; >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_AMDFAM10H: >>>> + =A0 =A0 =A0field =3D get_field_from_struct (__processor_model_type, >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0M_AMDFAM10H); >>>> + =A0 =A0 =A0which_struct =3D __cpu_model_var; >>>> + =A0 =A0 =A0break; >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_AMDFAM10H_BARCELONA: >>>> + =A0 =A0 =A0field =3D get_field_from_struct (__processor_model_type, >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0M_AMDFAM10H_BARCELONA); >>>> + =A0 =A0 =A0which_struct =3D __cpu_model_var; >>>> + =A0 =A0 =A0break; >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_AMDFAM10H_SHANGHAI: >>>> + =A0 =A0 =A0field =3D get_field_from_struct (__processor_model_type, >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0M_AMDFAM10H_SHANGHAI); >>>> + =A0 =A0 =A0which_struct =3D __cpu_model_var; >>>> + =A0 =A0 =A0break; >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_AMDFAM10H_ISTANBUL: >>>> + =A0 =A0 =A0field =3D get_field_from_struct (__processor_model_type, >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0M_AMDFAM10H_ISTANBUL); >>>> + =A0 =A0 =A0which_struct =3D __cpu_model_var; >>>> + =A0 =A0 =A0break; >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_AMDFAM15H_BDVER1: >>>> + =A0 =A0 =A0field =3D get_field_from_struct (__processor_model_type, >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0M_AMDFAM15H_BDVER1); >>>> + =A0 =A0 =A0which_struct =3D __cpu_model_var; >>>> + =A0 =A0 =A0break; >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_AMDFAM15H_BDVER2: >>>> + =A0 =A0 =A0field =3D get_field_from_struct (__processor_model_type, >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0M_AMDFAM15H_BDVER2); >>>> + =A0 =A0 =A0which_struct =3D __cpu_model_var; >>>> + =A0 =A0 =A0break; >>>> + =A0 =A0default: >>>> + =A0 =A0 =A0return NULL_TREE; >>>> + =A0 =A0} >>>> + >>>> + =A0return build3 (COMPONENT_REF, TREE_TYPE (field), which_struct, fi= eld, NULL_TREE); >>>> +} >>>> + >>>> +static tree >>>> +ix86_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0tree *args ATTRIBUTE_UNUSED, bool= ignore ATTRIBUTE_UNUSED) >>>> +{ >>>> + =A0const char* decl_name =3D IDENTIFIER_POINTER (DECL_NAME (fndecl)); >>>> + =A0if (DECL_BUILT_IN_CLASS (fndecl) =3D=3D BUILT_IN_MD >>>> + =A0 =A0 =A0&& strstr(decl_name, "__builtin_cpu") !=3D NULL) >>>> + =A0 =A0{ >>>> + =A0 =A0 =A0enum ix86_builtins code =3D (enum ix86_builtins) >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 DECL_FUN= CTION_CODE (fndecl); >>>> + =A0 =A0 =A0return fold_builtin_cpu (code); >>>> + =A0 =A0} >>>> + =A0return NULL_TREE; >>>> +} >>>> + >>>> +/* A builtin to init/return the cpu type or feature. =A0Returns an >>>> + =A0 integer and the type is a const if IS_CONST is set. */ >>>> + >>>> +static void >>>> +make_platform_builtin (const char* name, int code, int is_const) >>>> +{ >>>> + =A0tree decl; >>>> + =A0tree type; >>>> + >>>> + =A0type =3D ix86_get_builtin_func_type (INT_FTYPE_VOID); >>>> + =A0decl =3D add_builtin_function (name, type, code, BUILT_IN_MD, >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0NULL, NUL= L_TREE); >>>> + =A0gcc_assert (decl !=3D NULL_TREE); >>>> + =A0ix86_builtins[(int) code] =3D decl; >>>> + =A0if (is_const) >>>> + =A0 =A0TREE_READONLY (decl) =3D 1; >>>> +} >>>> + >>>> +/* Builtins to get CPU type and features supported. */ >>>> + >>>> +static void >>>> +ix86_init_platform_type_builtins (void) >>>> +{ >>>> + =A0make_platform_builtin ("__builtin_cpu_init", >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IX86_BUILTIN_CPU_INIT= , 0); >>>> + =A0make_platform_builtin ("__builtin_cpu_supports_cmov", >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IX86_BUILTIN_CPU_SUPP= ORTS_CMOV, 1); >>>> + =A0make_platform_builtin ("__builtin_cpu_supports_mmx", >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IX86_BUILTIN_CPU_SUPP= ORTS_MMX, 1); >>>> + =A0make_platform_builtin ("__builtin_cpu_supports_popcount", >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IX86_BUILTIN_CPU_SUPP= ORTS_POPCOUNT, 1); >>>> + =A0make_platform_builtin ("__builtin_cpu_supports_sse", >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IX86_BUILTIN_CPU_SUPP= ORTS_SSE, 1); >>>> + =A0make_platform_builtin ("__builtin_cpu_supports_sse2", >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IX86_BUILTIN_CPU_SUPP= ORTS_SSE2, 1); >>>> + =A0make_platform_builtin ("__builtin_cpu_supports_sse3", >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IX86_BUILTIN_CPU_SUPP= ORTS_SSE3, 1); >>>> + =A0make_platform_builtin ("__builtin_cpu_supports_ssse3", >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IX86_BUILTIN_CPU_SUPP= ORTS_SSSE3, 1); >>>> + =A0make_platform_builtin ("__builtin_cpu_supports_sse4_1", >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IX86_BUILTIN_CPU_SUPP= ORTS_SSE4_1, 1); >>>> + =A0make_platform_builtin ("__builtin_cpu_supports_sse4_2", >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IX86_BUILTIN_CPU_SUPP= ORTS_SSE4_2, 1); >>>> + =A0make_platform_builtin ("__builtin_cpu_is_amd", >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IX86_BUILTIN_CPU_IS_A= MD, 1); >>>> + =A0make_platform_builtin ("__builtin_cpu_is_intel_atom", >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IX86_BUILTIN_CPU_IS_I= NTEL_ATOM, 1); >>>> + =A0make_platform_builtin ("__builtin_cpu_is_intel_core2", >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IX86_BUILTIN_CPU_IS_I= NTEL_CORE2, 1); >>>> + =A0make_platform_builtin ("__builtin_cpu_is_intel", >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IX86_BUILTIN_CPU_IS_I= NTEL, 1); >>>> + =A0make_platform_builtin ("__builtin_cpu_is_intel_corei7", >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IX86_BUILTIN_CPU_IS_I= NTEL_COREI7, 1); >>>> + =A0make_platform_builtin ("__builtin_cpu_is_intel_corei7_nehalem", >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IX86_BUILTIN_CPU_IS_I= NTEL_COREI7_NEHALEM, 1); >>>> + =A0make_platform_builtin ("__builtin_cpu_is_intel_corei7_westmere", >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IX86_BUILTIN_CPU_IS_I= NTEL_COREI7_WESTMERE, 1); >>>> + =A0make_platform_builtin ("__builtin_cpu_is_intel_corei7_sandybridge= ", >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IX86_BUILTIN_CPU_IS_I= NTEL_COREI7_SANDYBRIDGE, 1); >>>> + =A0make_platform_builtin ("__builtin_cpu_is_amdfam10", >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IX86_BUILTIN_CPU_IS_A= MDFAM10H, 1); >>>> + =A0make_platform_builtin ("__builtin_cpu_is_amdfam10_barcelona", >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IX86_BUILTIN_CPU_IS_A= MDFAM10H_BARCELONA, 1); >>>> + =A0make_platform_builtin ("__builtin_cpu_is_amdfam10_shanghai", >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IX86_BUILTIN_CPU_IS_A= MDFAM10H_SHANGHAI, 1); >>>> + =A0make_platform_builtin ("__builtin_cpu_is_amdfam10_istanbul", >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IX86_BUILTIN_CPU_IS_A= MDFAM10H_ISTANBUL, 1); >>>> + =A0make_platform_builtin ("__builtin_cpu_is_amdfam15_bdver1", >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IX86_BUILTIN_CPU_IS_A= MDFAM15H_BDVER1, 1); >>>> + =A0make_platform_builtin ("__builtin_cpu_is_amdfam15_bdver2", >>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IX86_BUILTIN_CPU_IS_A= MDFAM15H_BDVER2, 1); >>>> +} >>>> + >>>> =A0/* Internal method for ix86_init_builtins. =A0*/ >>>> >>>> =A0static void >>>> @@ -27529,6 +28143,9 @@ ix86_init_builtins (void) >>>> >>>> =A0 ix86_init_builtin_types (); >>>> >>>> + =A0/* Builtins to get CPU type and features. */ >>>> + =A0ix86_init_platform_type_builtins (); >>>> + >>>> =A0 /* TFmode support builtins. =A0*/ >>>> =A0 def_builtin_const (0, "__builtin_infq", >>>> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FLOAT128_FTYPE_VOID, IX86_BUIL= TIN_INFQ); >>>> @@ -29145,6 +29762,48 @@ ix86_expand_builtin (tree exp, rtx target, rt= x sub >>>> =A0 enum machine_mode mode0, mode1, mode2, mode3, mode4; >>>> =A0 unsigned int fcode =3D DECL_FUNCTION_CODE (fndecl); >>>> >>>> + =A0/* For CPU builtins that can be folded, fold first and expand the= fold. =A0*/ >>>> + =A0switch (fcode) >>>> + =A0 =A0{ >>>> + =A0 =A0case IX86_BUILTIN_CPU_SUPPORTS_CMOV: >>>> + =A0 =A0case IX86_BUILTIN_CPU_SUPPORTS_MMX: >>>> + =A0 =A0case IX86_BUILTIN_CPU_SUPPORTS_POPCOUNT: >>>> + =A0 =A0case IX86_BUILTIN_CPU_SUPPORTS_SSE: >>>> + =A0 =A0case IX86_BUILTIN_CPU_SUPPORTS_SSE2: >>>> + =A0 =A0case IX86_BUILTIN_CPU_SUPPORTS_SSE3: >>>> + =A0 =A0case IX86_BUILTIN_CPU_SUPPORTS_SSSE3: >>>> + =A0 =A0case IX86_BUILTIN_CPU_SUPPORTS_SSE4_1: >>>> + =A0 =A0case IX86_BUILTIN_CPU_SUPPORTS_SSE4_2: >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_AMD: >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_INTEL: >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_INTEL_ATOM: >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_INTEL_CORE2: >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_INTEL_COREI7: >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_INTEL_COREI7_NEHALEM: >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_INTEL_COREI7_WESTMERE: >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_INTEL_COREI7_SANDYBRIDGE: >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_AMDFAM10H: >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_AMDFAM10H_BARCELONA: >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_AMDFAM10H_SHANGHAI: >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_AMDFAM10H_ISTANBUL: >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_AMDFAM15H_BDVER1: >>>> + =A0 =A0case IX86_BUILTIN_CPU_IS_AMDFAM15H_BDVER2: >>>> + =A0 =A0 =A0{ >>>> + =A0 =A0 =A0 =A0tree fold_expr =3D fold_builtin_cpu ((enum ix86_built= ins) fcode); >>>> + =A0 =A0 =A0 gcc_assert (fold_expr !=3D NULL_TREE); >>>> + =A0 =A0 =A0 =A0return expand_expr (fold_expr, target, mode, EXPAND_N= ORMAL); >>>> + =A0 =A0 =A0} >>>> + =A0 =A0case IX86_BUILTIN_CPU_INIT: >>>> + =A0 =A0 =A0{ >>>> + =A0 =A0 =A0 /* Make it call __cpu_indicator_init in libgcc. */ >>>> + =A0 =A0 =A0 tree call_expr, fndecl, type; >>>> + =A0 =A0 =A0 =A0type =3D build_function_type_list (integer_type_node,= NULL_TREE); >>>> + =A0 =A0 =A0 fndecl =3D build_fn_decl ("__cpu_indicator_init", type); >>>> + =A0 =A0 =A0 call_expr =3D build_call_expr (fndecl, 0); >>>> + =A0 =A0 =A0 return expand_expr (call_expr, target, mode, EXPAND_NORM= AL); >>>> + =A0 =A0 =A0} >>>> + =A0 =A0} >>>> + >>>> =A0 /* Determine whether the builtin function is available under the c= urrent ISA. >>>> =A0 =A0 =A0Originally the builtin was not created if it wasn't applica= ble to the >>>> =A0 =A0 =A0current ISA based on the command line switches. =A0With fun= ction specific >>>> @@ -38610,6 +39269,12 @@ ix86_autovectorize_vector_sizes (void) >>>> =A0#undef TARGET_BUILD_BUILTIN_VA_LIST >>>> =A0#define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list >>>> >>>> +#undef TARGET_FOLD_BUILTIN >>>> +#define TARGET_FOLD_BUILTIN ix86_fold_builtin >>>> + >>>> =A0#undef TARGET_ENUM_VA_LIST_P >>>> =A0#define TARGET_ENUM_VA_LIST_P ix86_enum_va_list >>>> Index: gcc/testsuite/gcc.target/i386/builtin_target.c >>>> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >>>> --- gcc/testsuite/gcc.target/i386/builtin_target.c =A0 =A0 =A0(revisio= n 0) >>>> +++ gcc/testsuite/gcc.target/i386/builtin_target.c =A0 =A0 =A0(revisio= n 0) >>>> @@ -0,0 +1,61 @@ >>>> +/* This test checks if the __builtin_cpu_* calls are recognized. */ >>>> + >>>> +/* { dg-do run } */ >>>> + >>>> +int >>>> +fn1 () >>>> +{ >>>> + =A0if (__builtin_cpu_supports_cmov () < 0) >>>> + =A0 =A0return -1; >>>> + =A0if (__builtin_cpu_supports_mmx () < 0) >>>> + =A0 =A0return -1; >>>> + =A0if (__builtin_cpu_supports_popcount () < 0) >>>> + =A0 =A0return -1; >>>> + =A0if (__builtin_cpu_supports_sse () < 0) >>>> + =A0 =A0return -1; >>>> + =A0if (__builtin_cpu_supports_sse2 () < 0) >>>> + =A0 =A0return -1; >>>> + =A0if (__builtin_cpu_supports_sse3 () < 0) >>>> + =A0 =A0return -1; >>>> + =A0if (__builtin_cpu_supports_ssse3 () < 0) >>>> + =A0 =A0return -1; >>>> + =A0if (__builtin_cpu_supports_sse4_1 () < 0) >>>> + =A0 =A0return -1; >>>> + =A0if (__builtin_cpu_supports_sse4_2 () < 0) >>>> + =A0 =A0return -1; >>>> + =A0if (__builtin_cpu_is_amd () < 0) >>>> + =A0 =A0return -1; >>>> + =A0if (__builtin_cpu_is_intel () < 0) >>>> + =A0 =A0return -1; >>>> + =A0if (__builtin_cpu_is_intel_atom () < 0) >>>> + =A0 =A0return -1; >>>> + =A0if (__builtin_cpu_is_intel_core2 () < 0) >>>> + =A0 =A0return -1; >>>> + =A0if (__builtin_cpu_is_intel_corei7 () < 0) >>>> + =A0 =A0return -1; >>>> + =A0if (__builtin_cpu_is_intel_corei7_nehalem () < 0) >>>> + =A0 =A0return -1; >>>> + =A0if (__builtin_cpu_is_intel_corei7_westmere () < 0) >>>> + =A0 =A0return -1; >>>> + =A0if (__builtin_cpu_is_intel_corei7_sandybridge () < 0) >>>> + =A0 =A0return -1; >>>> + =A0if (__builtin_cpu_is_amdfam10 () < 0) >>>> + =A0 =A0return -1; >>>> + =A0if (__builtin_cpu_is_amdfam10_barcelona () < 0) >>>> + =A0 =A0return -1; >>>> + =A0if (__builtin_cpu_is_amdfam10_shanghai () < 0) >>>> + =A0 =A0return -1; >>>> + =A0if (__builtin_cpu_is_amdfam10_istanbul () < 0) >>>> + =A0 =A0return -1; >>>> + =A0if (__builtin_cpu_is_amdfam15_bdver1 () < 0) >>>> + =A0 =A0return -1; >>>> + =A0if (__builtin_cpu_is_amdfam15_bdver2 () < 0) >>>> + =A0 =A0return -1; >>>> + >>>> + =A0return 0; >>>> +} >>>> + >>>> +int main () >>>> +{ >>>> + =A0return fn1 (); >>>> +} >>>> >>>> -- >>>> This patch is available for review at http://codereview.appspot.com/57= 54058