From: Jim Wilson <jim.wilson@linaro.org>
To: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Subject: Re: [PATCH] [ARM/Aarch64] add initial Qualcomm support
Date: Wed, 11 Nov 2015 19:55:00 -0000 [thread overview]
Message-ID: <CABXYE2Un2i=2E5Csgd5-Sy3JF9OETsz-kVpFyTsw9bmL3nsgtg@mail.gmail.com> (raw)
In-Reply-To: <CABXYE2UE0G9sT_wc+nuzmjpqUCf+2wZZEhh1VcNjO2ON8F-06w@mail.gmail.com>
On Wed, Nov 11, 2015 at 10:34 AM, Jim Wilson <jim.wilson@linaro.org> wrote:
> I had to disable the cortex-a57 fma steering pass in the aarch64 port
> while testing the patch. A bootstrap for aarch64 configured
> --with-cpu=cortex-a57 gives multiple ICEs while building the stage1
> libstdc++. The ICEs are in scan_rtx_reg at regrename.c:1074. This
> looks vaguely similar to PR 66785.
It looks like there is already a discussion of this issue in the
"Preferred rename register in regrename pass" thread, though I'm not
sure yet if it is the same issue or a closely related one.
Jim
next prev parent reply other threads:[~2015-11-11 19:55 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-11 18:34 Jim Wilson
2015-11-11 19:55 ` Jim Wilson [this message]
2015-11-12 11:42 ` James Greenhalgh
2015-11-12 16:15 ` Ramana Radhakrishnan
2015-11-13 16:59 ` Jim Wilson
2015-11-13 17:02 ` Kyrill Tkachov
2015-11-13 17:20 ` Jim Wilson
2015-11-13 17:53 ` Jim Wilson
2015-11-16 9:04 ` Kyrill Tkachov
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