* [PATCH, ARM/AArch64] drop aarch32 support for falkor/qdf24xx
@ 2017-05-12 3:52 Jim Wilson
2017-05-24 14:12 ` Richard Earnshaw (lists)
0 siblings, 1 reply; 11+ messages in thread
From: Jim Wilson @ 2017-05-12 3:52 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 528 bytes --]
Early steppings had aarch32 support, current steppings don't, so the
aarch32 support for falkor/qdf24xx needs to be dropped. This mostly
involves removing falkor/qdf24xx references from the arm port. The
qdf24xx_extra_costs structure moves from the arm port to the aarch64
port.
This was tested with aarch64-linux and armv8-linux bootstraps and make
checks. There were no regressions. Also verified by hand that the
-mcpu=falkor and -mqdf24xx options no longer work in the arm port but
still work in the aarch64 port.
Jim
[-- Attachment #2: patch.falkor-aarch32 --]
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gcc/
* config/aarch64/aarch64-cost-tables.h (qdf24xx_extra_costs): Move to
here.
* config/arm/aarch-cost-tables.h (qdf24xx_extra_costs): From here.
* config/arm/arm-cpu-cdata.h: Regenerate.
* config/arm/arm-cpu-data.h, config/arm/arm-cpu.h: Likewise.
* config/arm/arm-tables.opt, config/arm/arm-tune.md: Likewise.
* config/arm/arm-cpus.in: Delete falkor and qdf24xx entries.
* config/arm/arm.c (arm_qdf24xx_tune): Delete.
* config/arm/bpabi.h (BE8_LINK_SPEC): Delete falkor and qdf24xx
support.
* config/arm/t-aprofile (MULTILIB_MATCHES): Delete falkor and qdf24xx
support.
* config/arm/t-rmprofile: Likewise.
* doc/invoke.texi (ARM Options): Drop falkor and qdf24xx support.
Index: gcc/config/aarch64/aarch64-cost-tables.h
===================================================================
--- gcc/config/aarch64/aarch64-cost-tables.h (revision 247864)
+++ gcc/config/aarch64/aarch64-cost-tables.h (working copy)
@@ -23,7 +23,111 @@
#include "config/arm/aarch-cost-tables.h"
-/* ThunderX does not have implement AArch32. */
+/* QDF24xx does not implement AArch32. */
+const struct cpu_cost_table qdf24xx_extra_costs =
+{
+ /* ALU */
+ {
+ 0, /* arith. */
+ 0, /* logical. */
+ 0, /* shift. */
+ 0, /* shift_reg. */
+ COSTS_N_INSNS (1), /* arith_shift. */
+ COSTS_N_INSNS (1), /* arith_shift_reg. */
+ 0, /* log_shift. */
+ 0, /* log_shift_reg. */
+ 0, /* extend. */
+ 0, /* extend_arith. */
+ 0, /* bfi. */
+ 0, /* bfx. */
+ 0, /* clz. */
+ 0, /* rev. */
+ 0, /* non_exec. */
+ true /* non_exec_costs_exec. */
+ },
+ {
+ /* MULT SImode */
+ {
+ COSTS_N_INSNS (2), /* simple. */
+ COSTS_N_INSNS (2), /* flag_setting. */
+ COSTS_N_INSNS (2), /* extend. */
+ COSTS_N_INSNS (2), /* add. */
+ COSTS_N_INSNS (2), /* extend_add. */
+ COSTS_N_INSNS (4) /* idiv. */
+ },
+ /* MULT DImode */
+ {
+ COSTS_N_INSNS (3), /* simple. */
+ 0, /* flag_setting (N/A). */
+ COSTS_N_INSNS (3), /* extend. */
+ COSTS_N_INSNS (3), /* add. */
+ COSTS_N_INSNS (3), /* extend_add. */
+ COSTS_N_INSNS (9) /* idiv. */
+ }
+ },
+ /* LD/ST */
+ {
+ COSTS_N_INSNS (2), /* load. */
+ COSTS_N_INSNS (2), /* load_sign_extend. */
+ COSTS_N_INSNS (2), /* ldrd. */
+ COSTS_N_INSNS (2), /* ldm_1st. */
+ 1, /* ldm_regs_per_insn_1st. */
+ 2, /* ldm_regs_per_insn_subsequent. */
+ COSTS_N_INSNS (2), /* loadf. */
+ COSTS_N_INSNS (2), /* loadd. */
+ COSTS_N_INSNS (3), /* load_unaligned. */
+ 0, /* store. */
+ 0, /* strd. */
+ 0, /* stm_1st. */
+ 1, /* stm_regs_per_insn_1st. */
+ 2, /* stm_regs_per_insn_subsequent. */
+ 0, /* storef. */
+ 0, /* stored. */
+ COSTS_N_INSNS (1), /* store_unaligned. */
+ COSTS_N_INSNS (1), /* loadv. */
+ COSTS_N_INSNS (1) /* storev. */
+ },
+ {
+ /* FP SFmode */
+ {
+ COSTS_N_INSNS (6), /* div. */
+ COSTS_N_INSNS (5), /* mult. */
+ COSTS_N_INSNS (5), /* mult_addsub. */
+ COSTS_N_INSNS (5), /* fma. */
+ COSTS_N_INSNS (3), /* addsub. */
+ COSTS_N_INSNS (1), /* fpconst. */
+ COSTS_N_INSNS (1), /* neg. */
+ COSTS_N_INSNS (2), /* compare. */
+ COSTS_N_INSNS (4), /* widen. */
+ COSTS_N_INSNS (4), /* narrow. */
+ COSTS_N_INSNS (4), /* toint. */
+ COSTS_N_INSNS (4), /* fromint. */
+ COSTS_N_INSNS (2) /* roundint. */
+ },
+ /* FP DFmode */
+ {
+ COSTS_N_INSNS (11), /* div. */
+ COSTS_N_INSNS (6), /* mult. */
+ COSTS_N_INSNS (6), /* mult_addsub. */
+ COSTS_N_INSNS (6), /* fma. */
+ COSTS_N_INSNS (3), /* addsub. */
+ COSTS_N_INSNS (1), /* fpconst. */
+ COSTS_N_INSNS (1), /* neg. */
+ COSTS_N_INSNS (2), /* compare. */
+ COSTS_N_INSNS (4), /* widen. */
+ COSTS_N_INSNS (4), /* narrow. */
+ COSTS_N_INSNS (4), /* toint. */
+ COSTS_N_INSNS (4), /* fromint. */
+ COSTS_N_INSNS (2) /* roundint. */
+ }
+ },
+ /* Vector */
+ {
+ COSTS_N_INSNS (1) /* alu. */
+ }
+};
+
+/* ThunderX does not implement AArch32. */
const struct cpu_cost_table thunderx_extra_costs =
{
/* ALU */
@@ -230,6 +334,4 @@ const struct cpu_cost_table thunderx2t99_extra_cos
}
};
-
#endif
-
Index: gcc/config/arm/aarch-cost-tables.h
===================================================================
--- gcc/config/arm/aarch-cost-tables.h (revision 247864)
+++ gcc/config/arm/aarch-cost-tables.h (working copy)
@@ -537,107 +537,4 @@ const struct cpu_cost_table xgene1_extra_costs =
}
};
-const struct cpu_cost_table qdf24xx_extra_costs =
-{
- /* ALU */
- {
- 0, /* arith. */
- 0, /* logical. */
- 0, /* shift. */
- 0, /* shift_reg. */
- COSTS_N_INSNS (1), /* arith_shift. */
- COSTS_N_INSNS (1), /* arith_shift_reg. */
- 0, /* log_shift. */
- 0, /* log_shift_reg. */
- 0, /* extend. */
- 0, /* extend_arith. */
- 0, /* bfi. */
- 0, /* bfx. */
- 0, /* clz. */
- 0, /* rev. */
- 0, /* non_exec. */
- true /* non_exec_costs_exec. */
- },
- {
- /* MULT SImode */
- {
- COSTS_N_INSNS (2), /* simple. */
- COSTS_N_INSNS (2), /* flag_setting. */
- COSTS_N_INSNS (2), /* extend. */
- COSTS_N_INSNS (2), /* add. */
- COSTS_N_INSNS (2), /* extend_add. */
- COSTS_N_INSNS (4) /* idiv. */
- },
- /* MULT DImode */
- {
- COSTS_N_INSNS (3), /* simple. */
- 0, /* flag_setting (N/A). */
- COSTS_N_INSNS (3), /* extend. */
- COSTS_N_INSNS (3), /* add. */
- COSTS_N_INSNS (3), /* extend_add. */
- COSTS_N_INSNS (9) /* idiv. */
- }
- },
- /* LD/ST */
- {
- COSTS_N_INSNS (2), /* load. */
- COSTS_N_INSNS (2), /* load_sign_extend. */
- COSTS_N_INSNS (2), /* ldrd. */
- COSTS_N_INSNS (2), /* ldm_1st. */
- 1, /* ldm_regs_per_insn_1st. */
- 2, /* ldm_regs_per_insn_subsequent. */
- COSTS_N_INSNS (2), /* loadf. */
- COSTS_N_INSNS (2), /* loadd. */
- COSTS_N_INSNS (3), /* load_unaligned. */
- 0, /* store. */
- 0, /* strd. */
- 0, /* stm_1st. */
- 1, /* stm_regs_per_insn_1st. */
- 2, /* stm_regs_per_insn_subsequent. */
- 0, /* storef. */
- 0, /* stored. */
- COSTS_N_INSNS (1), /* store_unaligned. */
- COSTS_N_INSNS (1), /* loadv. */
- COSTS_N_INSNS (1) /* storev. */
- },
- {
- /* FP SFmode */
- {
- COSTS_N_INSNS (6), /* div. */
- COSTS_N_INSNS (5), /* mult. */
- COSTS_N_INSNS (5), /* mult_addsub. */
- COSTS_N_INSNS (5), /* fma. */
- COSTS_N_INSNS (3), /* addsub. */
- COSTS_N_INSNS (1), /* fpconst. */
- COSTS_N_INSNS (1), /* neg. */
- COSTS_N_INSNS (2), /* compare. */
- COSTS_N_INSNS (4), /* widen. */
- COSTS_N_INSNS (4), /* narrow. */
- COSTS_N_INSNS (4), /* toint. */
- COSTS_N_INSNS (4), /* fromint. */
- COSTS_N_INSNS (2) /* roundint. */
- },
- /* FP DFmode */
- {
- COSTS_N_INSNS (11), /* div. */
- COSTS_N_INSNS (6), /* mult. */
- COSTS_N_INSNS (6), /* mult_addsub. */
- COSTS_N_INSNS (6), /* fma. */
- COSTS_N_INSNS (3), /* addsub. */
- COSTS_N_INSNS (1), /* fpconst. */
- COSTS_N_INSNS (1), /* neg. */
- COSTS_N_INSNS (2), /* compare. */
- COSTS_N_INSNS (4), /* widen. */
- COSTS_N_INSNS (4), /* narrow. */
- COSTS_N_INSNS (4), /* toint. */
- COSTS_N_INSNS (4), /* fromint. */
- COSTS_N_INSNS (2) /* roundint. */
- }
- },
- /* Vector */
- {
- COSTS_N_INSNS (1) /* alu. */
- }
-};
-
#endif /* GCC_AARCH_COST_TABLES_H */
Index: gcc/config/arm/arm-cpu-cdata.h
===================================================================
--- gcc/config/arm/arm-cpu-cdata.h (revision 247864)
+++ gcc/config/arm/arm-cpu-cdata.h (working copy)
@@ -740,20 +740,6 @@ static const struct arm_arch_core_flag arm_arch_co
},
},
{
- "falkor",
- {
- ISA_ARMv8a,isa_bit_crc32,
- isa_nobit
- },
- },
- {
- "qdf24xx",
- {
- ISA_ARMv8a,isa_bit_crc32,
- isa_nobit
- },
- },
- {
"xgene1",
{
ISA_ARMv8a,
Index: gcc/config/arm/arm-cpu-data.h
===================================================================
--- gcc/config/arm/arm-cpu-data.h (revision 247864)
+++ gcc/config/arm/arm-cpu-data.h (working copy)
@@ -1144,28 +1144,6 @@ static const struct processors all_cores[] =
&arm_exynosm1_tune
},
{
- "falkor",
- TARGET_CPU_cortexa57,
- (TF_LDSCHED),
- "8A", BASE_ARCH_8A,
- {
- ISA_ARMv8a,isa_bit_crc32,
- isa_nobit
- },
- &arm_qdf24xx_tune
- },
- {
- "qdf24xx",
- TARGET_CPU_cortexa57,
- (TF_LDSCHED),
- "8A", BASE_ARCH_8A,
- {
- ISA_ARMv8a,isa_bit_crc32,
- isa_nobit
- },
- &arm_qdf24xx_tune
- },
- {
"xgene1",
TARGET_CPU_xgene1,
(TF_LDSCHED),
Index: gcc/config/arm/arm-cpu.h
===================================================================
--- gcc/config/arm/arm-cpu.h (revision 247864)
+++ gcc/config/arm/arm-cpu.h (working copy)
@@ -123,8 +123,6 @@ enum processor_type
TARGET_CPU_cortexa72,
TARGET_CPU_cortexa73,
TARGET_CPU_exynosm1,
- TARGET_CPU_falkor,
- TARGET_CPU_qdf24xx,
TARGET_CPU_xgene1,
TARGET_CPU_cortexa57cortexa53,
TARGET_CPU_cortexa72cortexa53,
Index: gcc/config/arm/arm-cpus.in
===================================================================
--- gcc/config/arm/arm-cpus.in (revision 247864)
+++ gcc/config/arm/arm-cpus.in (working copy)
@@ -1020,20 +1020,6 @@ begin cpu exynos-m1
costs exynosm1
end cpu exynos-m1
-begin cpu falkor
- tune for cortex-a57
- tune flags LDSCHED
- architecture armv8-a+crc
- costs qdf24xx
-end cpu falkor
-
-begin cpu qdf24xx
- tune for cortex-a57
- tune flags LDSCHED
- architecture armv8-a+crc
- costs qdf24xx
-end cpu qdf24xx
-
begin cpu xgene1
tune flags LDSCHED
architecture armv8-a
Index: gcc/config/arm/arm-tables.opt
===================================================================
--- gcc/config/arm/arm-tables.opt (revision 247864)
+++ gcc/config/arm/arm-tables.opt (working copy)
@@ -328,12 +328,6 @@ EnumValue
Enum(processor_type) String(exynos-m1) Value( TARGET_CPU_exynosm1)
EnumValue
-Enum(processor_type) String(falkor) Value( TARGET_CPU_falkor)
-
-EnumValue
-Enum(processor_type) String(qdf24xx) Value( TARGET_CPU_qdf24xx)
-
-EnumValue
Enum(processor_type) String(xgene1) Value( TARGET_CPU_xgene1)
EnumValue
Index: gcc/config/arm/arm-tune.md
===================================================================
--- gcc/config/arm/arm-tune.md (revision 247864)
+++ gcc/config/arm/arm-tune.md (working copy)
@@ -54,8 +54,7 @@
cortexm3,marvell_pj4,cortexa15cortexa7,
cortexa17cortexa7,cortexa32,cortexa35,
cortexa53,cortexa57,cortexa72,
- cortexa73,exynosm1,falkor,
- qdf24xx,xgene1,cortexa57cortexa53,
- cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,
- cortexm23,cortexm33"
+ cortexa73,exynosm1,xgene1,
+ cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,
+ cortexa73cortexa53,cortexm23,cortexm33"
(const (symbol_ref "((enum attr_tune) arm_tune)")))
Index: gcc/config/arm/arm.c
===================================================================
--- gcc/config/arm/arm.c (revision 247864)
+++ gcc/config/arm/arm.c (working copy)
@@ -2094,28 +2094,6 @@ const struct tune_params arm_xgene1_tune =
tune_params::SCHED_AUTOPREF_OFF
};
-const struct tune_params arm_qdf24xx_tune =
-{
- &qdf24xx_extra_costs,
- NULL, /* Scheduler cost adjustment. */
- arm_default_branch_cost,
- &arm_default_vec_cost, /* Vectorizer costs. */
- 1, /* Constant limit. */
- 2, /* Max cond insns. */
- 8, /* Memset max inline. */
- 4, /* Issue rate. */
- ARM_PREFETCH_BENEFICIAL (0, -1, 64),
- tune_params::PREF_CONST_POOL_FALSE,
- tune_params::PREF_LDRD_TRUE,
- tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE, /* Thumb. */
- tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE, /* ARM. */
- tune_params::DISPARAGE_FLAGS_ALL,
- tune_params::PREF_NEON_64_FALSE,
- tune_params::PREF_NEON_STRINGOPS_TRUE,
- FUSE_OPS (tune_params::FUSE_MOVW_MOVT),
- tune_params::SCHED_AUTOPREF_FULL
-};
-
/* Branches can be dual-issued on Cortex-A5, so conditional execution is
less appealing. Set max_insns_skipped to a low value. */
Index: gcc/config/arm/bpabi.h
===================================================================
--- gcc/config/arm/bpabi.h (revision 247864)
+++ gcc/config/arm/bpabi.h (working copy)
@@ -79,8 +79,6 @@
|mcpu=cortex-a73.cortex-a35 \
|mcpu=cortex-a73.cortex-a53 \
|mcpu=exynos-m1 \
- |mcpu=falkor \
- |mcpu=qdf24xx \
|mcpu=xgene1 \
|mcpu=cortex-m1.small-multiply \
|mcpu=cortex-m0.small-multiply \
@@ -118,8 +116,6 @@
|mcpu=cortex-a73.cortex-a35 \
|mcpu=cortex-a73.cortex-a53 \
|mcpu=exynos-m1 \
- |mcpu=falkor \
- |mcpu=qdf24xx \
|mcpu=xgene1 \
|mcpu=cortex-m1.small-multiply \
|mcpu=cortex-m0.small-multiply \
Index: gcc/config/arm/t-aprofile
===================================================================
--- gcc/config/arm/t-aprofile (revision 247864)
+++ gcc/config/arm/t-aprofile (working copy)
@@ -79,8 +79,6 @@ MULTILIB_MATCHES += march?armv8-a=mcpu?corte
MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73.cortex-a35
MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73.cortex-a53
MULTILIB_MATCHES += march?armv8-a=mcpu?exynos-m1
-MULTILIB_MATCHES += march?armv8-a=mcpu?falkor
-MULTILIB_MATCHES += march?armv8-a=mcpu?qdf24xx
MULTILIB_MATCHES += march?armv8-a=mcpu?xgene1
# Arch Matches
Index: gcc/config/arm/t-rmprofile
===================================================================
--- gcc/config/arm/t-rmprofile (revision 247864)
+++ gcc/config/arm/t-rmprofile (working copy)
@@ -112,7 +112,6 @@ MULTILIB_MATCHES += march?armv7=mcpu?cortex-
MULTILIB_MATCHES += march?armv7=mcpu?cortex-a73.cortex-a35
MULTILIB_MATCHES += march?armv7=mcpu?cortex-a73.cortex-a53
MULTILIB_MATCHES += march?armv7=mcpu?exynos-m1
-MULTILIB_MATCHES += march?armv7=mcpu?qdf24xx
MULTILIB_MATCHES += march?armv7=mcpu?xgene1
# Arch Matches
Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi (revision 247864)
+++ gcc/doc/invoke.texi (working copy)
@@ -13971,8 +13971,8 @@ processors implementing the target architecture.
Specify the name of the target processor for which GCC should tune the
performance of the code. Permissible values for this option are:
@samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57},
-@samp{cortex-a72}, @samp{cortex-a73}, @samp{exynos-m1}, @samp{falkor},
-@samp{qdf24xx}, @samp{xgene1}, @samp{vulcan}, @samp{thunderx},
+@samp{cortex-a72}, @samp{cortex-a73}, @samp{exynos-m1},
+@samp{xgene1}, @samp{vulcan}, @samp{thunderx},
@samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81},
@samp{thunderxt83}, @samp{thunderx2t99}, @samp{cortex-a57.cortex-a53},
@samp{cortex-a72.cortex-a53}, @samp{cortex-a73.cortex-a35},
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH, ARM/AArch64] drop aarch32 support for falkor/qdf24xx
2017-05-12 3:52 [PATCH, ARM/AArch64] drop aarch32 support for falkor/qdf24xx Jim Wilson
@ 2017-05-24 14:12 ` Richard Earnshaw (lists)
2017-05-24 14:20 ` Jim Wilson
0 siblings, 1 reply; 11+ messages in thread
From: Richard Earnshaw (lists) @ 2017-05-24 14:12 UTC (permalink / raw)
To: Jim Wilson, gcc-patches
On 12/05/17 03:43, Jim Wilson wrote:
> Early steppings had aarch32 support, current steppings don't, so the
> aarch32 support for falkor/qdf24xx needs to be dropped. This mostly
> involves removing falkor/qdf24xx references from the arm port. The
> qdf24xx_extra_costs structure moves from the arm port to the aarch64
> port.
>
> This was tested with aarch64-linux and armv8-linux bootstraps and make
> checks. There were no regressions. Also verified by hand that the
> -mcpu=falkor and -mqdf24xx options no longer work in the arm port but
> still work in the aarch64 port.
>
> Jim
>
OK. does this need to go in the gcc-8 changes file?
R.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH, ARM/AArch64] drop aarch32 support for falkor/qdf24xx
2017-05-24 14:12 ` Richard Earnshaw (lists)
@ 2017-05-24 14:20 ` Jim Wilson
2017-05-24 15:20 ` Richard Earnshaw (lists)
0 siblings, 1 reply; 11+ messages in thread
From: Jim Wilson @ 2017-05-24 14:20 UTC (permalink / raw)
To: Richard Earnshaw (lists); +Cc: gcc-patches
On Wed, May 24, 2017 at 6:56 AM, Richard Earnshaw (lists)
<Richard.Earnshaw@arm.com> wrote:
> OK. does this need to go in the gcc-8 changes file?
Falkor hasn't shipped yet. I'm dropping features that only existed in
preproduction NDA hardware, so there isn't anything end user visible,
and hence I don't think that it needs to be in the release notes.
Jim
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH, ARM/AArch64] drop aarch32 support for falkor/qdf24xx
2017-05-24 14:20 ` Jim Wilson
@ 2017-05-24 15:20 ` Richard Earnshaw (lists)
2017-05-24 16:05 ` Jim Wilson
0 siblings, 1 reply; 11+ messages in thread
From: Richard Earnshaw (lists) @ 2017-05-24 15:20 UTC (permalink / raw)
To: Jim Wilson; +Cc: gcc-patches
On 24/05/17 15:18, Jim Wilson wrote:
> On Wed, May 24, 2017 at 6:56 AM, Richard Earnshaw (lists)
> <Richard.Earnshaw@arm.com> wrote:
>> OK. does this need to go in the gcc-8 changes file?
>
> Falkor hasn't shipped yet. I'm dropping features that only existed in
> preproduction NDA hardware, so there isn't anything end user visible,
> and hence I don't think that it needs to be in the release notes.
>
> Jim
>
Fair enough, so what about a minimal back-port to GCC-7 that just
disables the CPU name for aarch32?
R.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH, ARM/AArch64] drop aarch32 support for falkor/qdf24xx
2017-05-24 15:20 ` Richard Earnshaw (lists)
@ 2017-05-24 16:05 ` Jim Wilson
2017-05-24 16:30 ` Richard Earnshaw (lists)
0 siblings, 1 reply; 11+ messages in thread
From: Jim Wilson @ 2017-05-24 16:05 UTC (permalink / raw)
To: Richard Earnshaw (lists); +Cc: gcc-patches
On Wed, May 24, 2017 at 8:17 AM, Richard Earnshaw (lists)
<Richard.Earnshaw@arm.com> wrote:
> On 24/05/17 15:18, Jim Wilson wrote:
>> On Wed, May 24, 2017 at 6:56 AM, Richard Earnshaw (lists)
>> <Richard.Earnshaw@arm.com> wrote:
>>> OK. does this need to go in the gcc-8 changes file?
>>
>> Falkor hasn't shipped yet. I'm dropping features that only existed in
>> preproduction NDA hardware, so there isn't anything end user visible,
>> and hence I don't think that it needs to be in the release notes.
>>
>> Jim
>>
>
> Fair enough, so what about a minimal back-port to GCC-7 that just
> disables the CPU name for aarch32?
Not sure how to do that. If I remove the arm-cpus.in entry, then 5
files get automatically regenerated. That leaves us with a few minor
inconsistencies in specs handling and multilibs which are harmless but
we may as well fix anyways. The only part of the patch that is
optional if the part which moves the qdf24xx_extra_costs array from
the arm dir to the aarch64 dir. So the minimal patch ends up being
half the size of the original patch, changing 9 of the original 11
files, which isn't very minimal.
Another option might be to just remove the documentation and leave the
code in, i.e. only apply the doc/invoke.texi patch. That would be a
small and safe patch.
Jim
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH, ARM/AArch64] drop aarch32 support for falkor/qdf24xx
2017-05-24 16:05 ` Jim Wilson
@ 2017-05-24 16:30 ` Richard Earnshaw (lists)
2017-05-25 9:29 ` Richard Earnshaw (lists)
0 siblings, 1 reply; 11+ messages in thread
From: Richard Earnshaw (lists) @ 2017-05-24 16:30 UTC (permalink / raw)
To: Jim Wilson; +Cc: gcc-patches
On 24/05/17 17:03, Jim Wilson wrote:
> On Wed, May 24, 2017 at 8:17 AM, Richard Earnshaw (lists)
> <Richard.Earnshaw@arm.com> wrote:
>> On 24/05/17 15:18, Jim Wilson wrote:
>>> On Wed, May 24, 2017 at 6:56 AM, Richard Earnshaw (lists)
>>> <Richard.Earnshaw@arm.com> wrote:
>>>> OK. does this need to go in the gcc-8 changes file?
>>>
>>> Falkor hasn't shipped yet. I'm dropping features that only existed in
>>> preproduction NDA hardware, so there isn't anything end user visible,
>>> and hence I don't think that it needs to be in the release notes.
>>>
>>> Jim
>>>
>>
>> Fair enough, so what about a minimal back-port to GCC-7 that just
>> disables the CPU name for aarch32?
>
> Not sure how to do that. If I remove the arm-cpus.in entry, then 5
> files get automatically regenerated. That leaves us with a few minor
> inconsistencies in specs handling and multilibs which are harmless but
> we may as well fix anyways. The only part of the patch that is
> optional if the part which moves the qdf24xx_extra_costs array from
> the arm dir to the aarch64 dir. So the minimal patch ends up being
> half the size of the original patch, changing 9 of the original 11
> files, which isn't very minimal.
>
> Another option might be to just remove the documentation and leave the
> code in, i.e. only apply the doc/invoke.texi patch. That would be a
> small and safe patch.
>
> Jim
>
Certainly we should remove it from the documentation. That might be the
best idea.
I don't really regard the size of the changes to the auto-generated code
as being relevant - if we put the generated code directly in the build
directory and treated it like we do the output from gen*.c, then those
changes would never be even noticed.
R.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH, ARM/AArch64] drop aarch32 support for falkor/qdf24xx
2017-05-24 16:30 ` Richard Earnshaw (lists)
@ 2017-05-25 9:29 ` Richard Earnshaw (lists)
2017-06-09 20:03 ` Jim Wilson
0 siblings, 1 reply; 11+ messages in thread
From: Richard Earnshaw (lists) @ 2017-05-25 9:29 UTC (permalink / raw)
To: Jim Wilson; +Cc: gcc-patches
On 24/05/17 17:19, Richard Earnshaw (lists) wrote:
> On 24/05/17 17:03, Jim Wilson wrote:
>> On Wed, May 24, 2017 at 8:17 AM, Richard Earnshaw (lists)
>> <Richard.Earnshaw@arm.com> wrote:
>>> On 24/05/17 15:18, Jim Wilson wrote:
>>>> On Wed, May 24, 2017 at 6:56 AM, Richard Earnshaw (lists)
>>>> <Richard.Earnshaw@arm.com> wrote:
>>>>> OK. does this need to go in the gcc-8 changes file?
>>>>
>>>> Falkor hasn't shipped yet. I'm dropping features that only existed in
>>>> preproduction NDA hardware, so there isn't anything end user visible,
>>>> and hence I don't think that it needs to be in the release notes.
>>>>
>>>> Jim
>>>>
>>>
>>> Fair enough, so what about a minimal back-port to GCC-7 that just
>>> disables the CPU name for aarch32?
>>
>> Not sure how to do that. If I remove the arm-cpus.in entry, then 5
>> files get automatically regenerated. That leaves us with a few minor
>> inconsistencies in specs handling and multilibs which are harmless but
>> we may as well fix anyways. The only part of the patch that is
>> optional if the part which moves the qdf24xx_extra_costs array from
>> the arm dir to the aarch64 dir. So the minimal patch ends up being
>> half the size of the original patch, changing 9 of the original 11
>> files, which isn't very minimal.
>>
>> Another option might be to just remove the documentation and leave the
>> code in, i.e. only apply the doc/invoke.texi patch. That would be a
>> small and safe patch.
>>
>> Jim
>>
>
> Certainly we should remove it from the documentation. That might be the
> best idea.
>
> I don't really regard the size of the changes to the auto-generated code
> as being relevant - if we put the generated code directly in the build
> directory and treated it like we do the output from gen*.c, then those
> changes would never be even noticed.
>
> R.
>
Having pondered this over night, I think the lowest risk thing to do,
provided it applies cleanly to the gcc-7 branch, is just commit the
entire patch on the branch and be done with it. The risk from removing
this code is pretty minimal and removing it all is the best way of
avoiding things like unexpected compiler warnings breaking the build.
If it doesn't apply cleanly, then just drop the documentation.
R.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH, ARM/AArch64] drop aarch32 support for falkor/qdf24xx
2017-05-25 9:29 ` Richard Earnshaw (lists)
@ 2017-06-09 20:03 ` Jim Wilson
2017-06-10 9:44 ` Richard Earnshaw (lists)
2017-06-12 10:40 ` James Greenhalgh
0 siblings, 2 replies; 11+ messages in thread
From: Jim Wilson @ 2017-06-09 20:03 UTC (permalink / raw)
To: Richard Earnshaw (lists); +Cc: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 687 bytes --]
On Thu, May 25, 2017 at 2:25 AM, Richard Earnshaw (lists)
<Richard.Earnshaw@arm.com> wrote:
> Having pondered this over night, I think the lowest risk thing to do,
> provided it applies cleanly to the gcc-7 branch, is just commit the
> entire patch on the branch and be done with it. The risk from removing
> this code is pretty minimal and removing it all is the best way of
> avoiding things like unexpected compiler warnings breaking the build.
> If it doesn't apply cleanly, then just drop the documentation.
The patch backports cleanly. I've tested the patch on the
gcc-7-branch, with both armv8 and aarch64 bootstraps and make checks,
with no regressions. Ok to check in?
Jim
[-- Attachment #2: falkor-aarch32.patch --]
[-- Type: text/x-patch, Size: 16965 bytes --]
gcc/
* config/aarch64/aarch64-cost-tables.h (qdf24xx_extra_costs): Move to
here.
* config/arm/aarch-cost-tables.h (qdf24xx_extra_costs): From here.
* config/arm/arm-cpu-cdata.h: Regenerate.
* config/arm/arm-cpu-data.h, config/arm/arm-cpu.h: Likewise.
* config/arm/arm-tables.opt, config/arm/arm-tune.md: Likewise.
* config/arm/arm-cpus.in: Delete falkor and qdf24xx entries.
* config/arm/arm.c (arm_qdf24xx_tune): Delete.
* config/arm/bpabi.h (BE8_LINK_SPEC): Delete falkor and qdf24xx
support.
* config/arm/t-aprofile (MULTILIB_MATCHES): Delete falkor and qdf24xx
support.
* config/arm/t-rmprofile: Likewise.
* doc/invoke.texi (ARM Options): Drop falkor and qdf24xx support.
Index: gcc/config/aarch64/aarch64-cost-tables.h
===================================================================
--- gcc/config/aarch64/aarch64-cost-tables.h (revision 249025)
+++ gcc/config/aarch64/aarch64-cost-tables.h (working copy)
@@ -23,7 +23,111 @@
#include "config/arm/aarch-cost-tables.h"
-/* ThunderX does not have implement AArch32. */
+/* QDF24xx does not implement AArch32. */
+const struct cpu_cost_table qdf24xx_extra_costs =
+{
+ /* ALU */
+ {
+ 0, /* arith. */
+ 0, /* logical. */
+ 0, /* shift. */
+ 0, /* shift_reg. */
+ COSTS_N_INSNS (1), /* arith_shift. */
+ COSTS_N_INSNS (1), /* arith_shift_reg. */
+ 0, /* log_shift. */
+ 0, /* log_shift_reg. */
+ 0, /* extend. */
+ 0, /* extend_arith. */
+ 0, /* bfi. */
+ 0, /* bfx. */
+ 0, /* clz. */
+ 0, /* rev. */
+ 0, /* non_exec. */
+ true /* non_exec_costs_exec. */
+ },
+ {
+ /* MULT SImode */
+ {
+ COSTS_N_INSNS (2), /* simple. */
+ COSTS_N_INSNS (2), /* flag_setting. */
+ COSTS_N_INSNS (2), /* extend. */
+ COSTS_N_INSNS (2), /* add. */
+ COSTS_N_INSNS (2), /* extend_add. */
+ COSTS_N_INSNS (4) /* idiv. */
+ },
+ /* MULT DImode */
+ {
+ COSTS_N_INSNS (3), /* simple. */
+ 0, /* flag_setting (N/A). */
+ COSTS_N_INSNS (3), /* extend. */
+ COSTS_N_INSNS (3), /* add. */
+ COSTS_N_INSNS (3), /* extend_add. */
+ COSTS_N_INSNS (9) /* idiv. */
+ }
+ },
+ /* LD/ST */
+ {
+ COSTS_N_INSNS (2), /* load. */
+ COSTS_N_INSNS (2), /* load_sign_extend. */
+ COSTS_N_INSNS (2), /* ldrd. */
+ COSTS_N_INSNS (2), /* ldm_1st. */
+ 1, /* ldm_regs_per_insn_1st. */
+ 2, /* ldm_regs_per_insn_subsequent. */
+ COSTS_N_INSNS (2), /* loadf. */
+ COSTS_N_INSNS (2), /* loadd. */
+ COSTS_N_INSNS (3), /* load_unaligned. */
+ 0, /* store. */
+ 0, /* strd. */
+ 0, /* stm_1st. */
+ 1, /* stm_regs_per_insn_1st. */
+ 2, /* stm_regs_per_insn_subsequent. */
+ 0, /* storef. */
+ 0, /* stored. */
+ COSTS_N_INSNS (1), /* store_unaligned. */
+ COSTS_N_INSNS (1), /* loadv. */
+ COSTS_N_INSNS (1) /* storev. */
+ },
+ {
+ /* FP SFmode */
+ {
+ COSTS_N_INSNS (6), /* div. */
+ COSTS_N_INSNS (5), /* mult. */
+ COSTS_N_INSNS (5), /* mult_addsub. */
+ COSTS_N_INSNS (5), /* fma. */
+ COSTS_N_INSNS (3), /* addsub. */
+ COSTS_N_INSNS (1), /* fpconst. */
+ COSTS_N_INSNS (1), /* neg. */
+ COSTS_N_INSNS (2), /* compare. */
+ COSTS_N_INSNS (4), /* widen. */
+ COSTS_N_INSNS (4), /* narrow. */
+ COSTS_N_INSNS (4), /* toint. */
+ COSTS_N_INSNS (4), /* fromint. */
+ COSTS_N_INSNS (2) /* roundint. */
+ },
+ /* FP DFmode */
+ {
+ COSTS_N_INSNS (11), /* div. */
+ COSTS_N_INSNS (6), /* mult. */
+ COSTS_N_INSNS (6), /* mult_addsub. */
+ COSTS_N_INSNS (6), /* fma. */
+ COSTS_N_INSNS (3), /* addsub. */
+ COSTS_N_INSNS (1), /* fpconst. */
+ COSTS_N_INSNS (1), /* neg. */
+ COSTS_N_INSNS (2), /* compare. */
+ COSTS_N_INSNS (4), /* widen. */
+ COSTS_N_INSNS (4), /* narrow. */
+ COSTS_N_INSNS (4), /* toint. */
+ COSTS_N_INSNS (4), /* fromint. */
+ COSTS_N_INSNS (2) /* roundint. */
+ }
+ },
+ /* Vector */
+ {
+ COSTS_N_INSNS (1) /* alu. */
+ }
+};
+
+/* ThunderX does not implement AArch32. */
const struct cpu_cost_table thunderx_extra_costs =
{
/* ALU */
@@ -230,6 +334,4 @@ const struct cpu_cost_table thunderx2t99_extra_cos
}
};
-
#endif
-
Index: gcc/config/arm/aarch-cost-tables.h
===================================================================
--- gcc/config/arm/aarch-cost-tables.h (revision 249025)
+++ gcc/config/arm/aarch-cost-tables.h (working copy)
@@ -537,107 +537,4 @@ const struct cpu_cost_table xgene1_extra_costs =
}
};
-const struct cpu_cost_table qdf24xx_extra_costs =
-{
- /* ALU */
- {
- 0, /* arith. */
- 0, /* logical. */
- 0, /* shift. */
- 0, /* shift_reg. */
- COSTS_N_INSNS (1), /* arith_shift. */
- COSTS_N_INSNS (1), /* arith_shift_reg. */
- 0, /* log_shift. */
- 0, /* log_shift_reg. */
- 0, /* extend. */
- 0, /* extend_arith. */
- 0, /* bfi. */
- 0, /* bfx. */
- 0, /* clz. */
- 0, /* rev. */
- 0, /* non_exec. */
- true /* non_exec_costs_exec. */
- },
- {
- /* MULT SImode */
- {
- COSTS_N_INSNS (2), /* simple. */
- COSTS_N_INSNS (2), /* flag_setting. */
- COSTS_N_INSNS (2), /* extend. */
- COSTS_N_INSNS (2), /* add. */
- COSTS_N_INSNS (2), /* extend_add. */
- COSTS_N_INSNS (4) /* idiv. */
- },
- /* MULT DImode */
- {
- COSTS_N_INSNS (3), /* simple. */
- 0, /* flag_setting (N/A). */
- COSTS_N_INSNS (3), /* extend. */
- COSTS_N_INSNS (3), /* add. */
- COSTS_N_INSNS (3), /* extend_add. */
- COSTS_N_INSNS (9) /* idiv. */
- }
- },
- /* LD/ST */
- {
- COSTS_N_INSNS (2), /* load. */
- COSTS_N_INSNS (2), /* load_sign_extend. */
- COSTS_N_INSNS (2), /* ldrd. */
- COSTS_N_INSNS (2), /* ldm_1st. */
- 1, /* ldm_regs_per_insn_1st. */
- 2, /* ldm_regs_per_insn_subsequent. */
- COSTS_N_INSNS (2), /* loadf. */
- COSTS_N_INSNS (2), /* loadd. */
- COSTS_N_INSNS (3), /* load_unaligned. */
- 0, /* store. */
- 0, /* strd. */
- 0, /* stm_1st. */
- 1, /* stm_regs_per_insn_1st. */
- 2, /* stm_regs_per_insn_subsequent. */
- 0, /* storef. */
- 0, /* stored. */
- COSTS_N_INSNS (1), /* store_unaligned. */
- COSTS_N_INSNS (1), /* loadv. */
- COSTS_N_INSNS (1) /* storev. */
- },
- {
- /* FP SFmode */
- {
- COSTS_N_INSNS (6), /* div. */
- COSTS_N_INSNS (5), /* mult. */
- COSTS_N_INSNS (5), /* mult_addsub. */
- COSTS_N_INSNS (5), /* fma. */
- COSTS_N_INSNS (3), /* addsub. */
- COSTS_N_INSNS (1), /* fpconst. */
- COSTS_N_INSNS (1), /* neg. */
- COSTS_N_INSNS (2), /* compare. */
- COSTS_N_INSNS (4), /* widen. */
- COSTS_N_INSNS (4), /* narrow. */
- COSTS_N_INSNS (4), /* toint. */
- COSTS_N_INSNS (4), /* fromint. */
- COSTS_N_INSNS (2) /* roundint. */
- },
- /* FP DFmode */
- {
- COSTS_N_INSNS (11), /* div. */
- COSTS_N_INSNS (6), /* mult. */
- COSTS_N_INSNS (6), /* mult_addsub. */
- COSTS_N_INSNS (6), /* fma. */
- COSTS_N_INSNS (3), /* addsub. */
- COSTS_N_INSNS (1), /* fpconst. */
- COSTS_N_INSNS (1), /* neg. */
- COSTS_N_INSNS (2), /* compare. */
- COSTS_N_INSNS (4), /* widen. */
- COSTS_N_INSNS (4), /* narrow. */
- COSTS_N_INSNS (4), /* toint. */
- COSTS_N_INSNS (4), /* fromint. */
- COSTS_N_INSNS (2) /* roundint. */
- }
- },
- /* Vector */
- {
- COSTS_N_INSNS (1) /* alu. */
- }
-};
-
#endif /* GCC_AARCH_COST_TABLES_H */
Index: gcc/config/arm/arm-cpu-cdata.h
===================================================================
--- gcc/config/arm/arm-cpu-cdata.h (revision 249025)
+++ gcc/config/arm/arm-cpu-cdata.h (working copy)
@@ -740,20 +740,6 @@ static const struct arm_arch_core_flag arm_arch_co
},
},
{
- "falkor",
- {
- ISA_ARMv8a,isa_bit_crc32,
- isa_nobit
- },
- },
- {
- "qdf24xx",
- {
- ISA_ARMv8a,isa_bit_crc32,
- isa_nobit
- },
- },
- {
"xgene1",
{
ISA_ARMv8a,
Index: gcc/config/arm/arm-cpu-data.h
===================================================================
--- gcc/config/arm/arm-cpu-data.h (revision 249025)
+++ gcc/config/arm/arm-cpu-data.h (working copy)
@@ -1144,28 +1144,6 @@ static const struct processors all_cores[] =
&arm_exynosm1_tune
},
{
- "falkor",
- TARGET_CPU_cortexa57,
- (TF_LDSCHED),
- "8A", BASE_ARCH_8A,
- {
- ISA_ARMv8a,isa_bit_crc32,
- isa_nobit
- },
- &arm_qdf24xx_tune
- },
- {
- "qdf24xx",
- TARGET_CPU_cortexa57,
- (TF_LDSCHED),
- "8A", BASE_ARCH_8A,
- {
- ISA_ARMv8a,isa_bit_crc32,
- isa_nobit
- },
- &arm_qdf24xx_tune
- },
- {
"xgene1",
TARGET_CPU_xgene1,
(TF_LDSCHED),
Index: gcc/config/arm/arm-cpu.h
===================================================================
--- gcc/config/arm/arm-cpu.h (revision 249025)
+++ gcc/config/arm/arm-cpu.h (working copy)
@@ -123,8 +123,6 @@ enum processor_type
TARGET_CPU_cortexa72,
TARGET_CPU_cortexa73,
TARGET_CPU_exynosm1,
- TARGET_CPU_falkor,
- TARGET_CPU_qdf24xx,
TARGET_CPU_xgene1,
TARGET_CPU_cortexa57cortexa53,
TARGET_CPU_cortexa72cortexa53,
Index: gcc/config/arm/arm-cpus.in
===================================================================
--- gcc/config/arm/arm-cpus.in (revision 249025)
+++ gcc/config/arm/arm-cpus.in (working copy)
@@ -1020,20 +1020,6 @@ begin cpu exynos-m1
costs exynosm1
end cpu exynos-m1
-begin cpu falkor
- tune for cortex-a57
- tune flags LDSCHED
- architecture armv8-a+crc
- costs qdf24xx
-end cpu falkor
-
-begin cpu qdf24xx
- tune for cortex-a57
- tune flags LDSCHED
- architecture armv8-a+crc
- costs qdf24xx
-end cpu qdf24xx
-
begin cpu xgene1
tune flags LDSCHED
architecture armv8-a
Index: gcc/config/arm/arm-tables.opt
===================================================================
--- gcc/config/arm/arm-tables.opt (revision 249025)
+++ gcc/config/arm/arm-tables.opt (working copy)
@@ -328,12 +328,6 @@ EnumValue
Enum(processor_type) String(exynos-m1) Value( TARGET_CPU_exynosm1)
EnumValue
-Enum(processor_type) String(falkor) Value( TARGET_CPU_falkor)
-
-EnumValue
-Enum(processor_type) String(qdf24xx) Value( TARGET_CPU_qdf24xx)
-
-EnumValue
Enum(processor_type) String(xgene1) Value( TARGET_CPU_xgene1)
EnumValue
Index: gcc/config/arm/arm-tune.md
===================================================================
--- gcc/config/arm/arm-tune.md (revision 249025)
+++ gcc/config/arm/arm-tune.md (working copy)
@@ -54,8 +54,7 @@
cortexm3,marvell_pj4,cortexa15cortexa7,
cortexa17cortexa7,cortexa32,cortexa35,
cortexa53,cortexa57,cortexa72,
- cortexa73,exynosm1,falkor,
- qdf24xx,xgene1,cortexa57cortexa53,
- cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,
- cortexm23,cortexm33"
+ cortexa73,exynosm1,xgene1,
+ cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,
+ cortexa73cortexa53,cortexm23,cortexm33"
(const (symbol_ref "((enum attr_tune) arm_tune)")))
Index: gcc/config/arm/arm.c
===================================================================
--- gcc/config/arm/arm.c (revision 249025)
+++ gcc/config/arm/arm.c (working copy)
@@ -2090,28 +2090,6 @@ const struct tune_params arm_xgene1_tune =
tune_params::SCHED_AUTOPREF_OFF
};
-const struct tune_params arm_qdf24xx_tune =
-{
- &qdf24xx_extra_costs,
- NULL, /* Scheduler cost adjustment. */
- arm_default_branch_cost,
- &arm_default_vec_cost, /* Vectorizer costs. */
- 1, /* Constant limit. */
- 2, /* Max cond insns. */
- 8, /* Memset max inline. */
- 4, /* Issue rate. */
- ARM_PREFETCH_BENEFICIAL (0, -1, 64),
- tune_params::PREF_CONST_POOL_FALSE,
- tune_params::PREF_LDRD_TRUE,
- tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE, /* Thumb. */
- tune_params::LOG_OP_NON_SHORT_CIRCUIT_TRUE, /* ARM. */
- tune_params::DISPARAGE_FLAGS_ALL,
- tune_params::PREF_NEON_64_FALSE,
- tune_params::PREF_NEON_STRINGOPS_TRUE,
- FUSE_OPS (tune_params::FUSE_MOVW_MOVT),
- tune_params::SCHED_AUTOPREF_FULL
-};
-
/* Branches can be dual-issued on Cortex-A5, so conditional execution is
less appealing. Set max_insns_skipped to a low value. */
Index: gcc/config/arm/bpabi.h
===================================================================
--- gcc/config/arm/bpabi.h (revision 249025)
+++ gcc/config/arm/bpabi.h (working copy)
@@ -79,8 +79,6 @@
|mcpu=cortex-a73.cortex-a35 \
|mcpu=cortex-a73.cortex-a53 \
|mcpu=exynos-m1 \
- |mcpu=falkor \
- |mcpu=qdf24xx \
|mcpu=xgene1 \
|mcpu=cortex-m1.small-multiply \
|mcpu=cortex-m0.small-multiply \
@@ -118,8 +116,6 @@
|mcpu=cortex-a73.cortex-a35 \
|mcpu=cortex-a73.cortex-a53 \
|mcpu=exynos-m1 \
- |mcpu=falkor \
- |mcpu=qdf24xx \
|mcpu=xgene1 \
|mcpu=cortex-m1.small-multiply \
|mcpu=cortex-m0.small-multiply \
Index: gcc/config/arm/t-aprofile
===================================================================
--- gcc/config/arm/t-aprofile (revision 249025)
+++ gcc/config/arm/t-aprofile (working copy)
@@ -92,8 +92,6 @@ MULTILIB_MATCHES += march?armv8-a=mcpu?corte
MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73.cortex-a35
MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a73.cortex-a53
MULTILIB_MATCHES += march?armv8-a=mcpu?exynos-m1
-MULTILIB_MATCHES += march?armv8-a=mcpu?falkor
-MULTILIB_MATCHES += march?armv8-a=mcpu?qdf24xx
MULTILIB_MATCHES += march?armv8-a=mcpu?xgene1
# Arch Matches
Index: gcc/config/arm/t-rmprofile
===================================================================
--- gcc/config/arm/t-rmprofile (revision 249025)
+++ gcc/config/arm/t-rmprofile (working copy)
@@ -131,7 +131,6 @@ MULTILIB_MATCHES += march?armv7=mcpu?cortex-
MULTILIB_MATCHES += march?armv7=mcpu?cortex-a73.cortex-a35
MULTILIB_MATCHES += march?armv7=mcpu?cortex-a73.cortex-a53
MULTILIB_MATCHES += march?armv7=mcpu?exynos-m1
-MULTILIB_MATCHES += march?armv7=mcpu?qdf24xx
MULTILIB_MATCHES += march?armv7=mcpu?xgene1
# Arch Matches
Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi (revision 249025)
+++ gcc/doc/invoke.texi (working copy)
@@ -13983,8 +13983,8 @@ processors implementing the target architecture.
Specify the name of the target processor for which GCC should tune the
performance of the code. Permissible values for this option are:
@samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57},
-@samp{cortex-a72}, @samp{cortex-a73}, @samp{exynos-m1}, @samp{falkor},
-@samp{qdf24xx}, @samp{xgene1}, @samp{vulcan}, @samp{thunderx},
+@samp{cortex-a72}, @samp{cortex-a73}, @samp{exynos-m1},
+@samp{xgene1}, @samp{vulcan}, @samp{thunderx},
@samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81},
@samp{thunderxt83}, @samp{thunderx2t99}, @samp{cortex-a57.cortex-a53},
@samp{cortex-a72.cortex-a53}, @samp{cortex-a73.cortex-a35},
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH, ARM/AArch64] drop aarch32 support for falkor/qdf24xx
2017-06-09 20:03 ` Jim Wilson
@ 2017-06-10 9:44 ` Richard Earnshaw (lists)
2017-06-12 10:40 ` James Greenhalgh
1 sibling, 0 replies; 11+ messages in thread
From: Richard Earnshaw (lists) @ 2017-06-10 9:44 UTC (permalink / raw)
To: Jim Wilson; +Cc: gcc-patches
On 09/06/17 21:03, Jim Wilson wrote:
> On Thu, May 25, 2017 at 2:25 AM, Richard Earnshaw (lists)
> <Richard.Earnshaw@arm.com> wrote:
>> Having pondered this over night, I think the lowest risk thing to do,
>> provided it applies cleanly to the gcc-7 branch, is just commit the
>> entire patch on the branch and be done with it. The risk from removing
>> this code is pretty minimal and removing it all is the best way of
>> avoiding things like unexpected compiler warnings breaking the build.
>> If it doesn't apply cleanly, then just drop the documentation.
>
> The patch backports cleanly. I've tested the patch on the
> gcc-7-branch, with both armv8 and aarch64 bootstraps and make checks,
> with no regressions. Ok to check in?
>
> Jim
>
OK.
R.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH, ARM/AArch64] drop aarch32 support for falkor/qdf24xx
2017-06-09 20:03 ` Jim Wilson
2017-06-10 9:44 ` Richard Earnshaw (lists)
@ 2017-06-12 10:40 ` James Greenhalgh
2017-06-23 21:46 ` Jim Wilson
1 sibling, 1 reply; 11+ messages in thread
From: James Greenhalgh @ 2017-06-12 10:40 UTC (permalink / raw)
To: Jim Wilson; +Cc: Richard Earnshaw (lists), gcc-patches, nd
On Fri, Jun 09, 2017 at 01:03:34PM -0700, Jim Wilson wrote:
> # Arch Matches
> Index: gcc/doc/invoke.texi
> ===================================================================
> --- gcc/doc/invoke.texi (revision 249025)
> +++ gcc/doc/invoke.texi (working copy)
> @@ -13983,8 +13983,8 @@ processors implementing the target architecture.
> Specify the name of the target processor for which GCC should tune the
> performance of the code. Permissible values for this option are:
> @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57},
> -@samp{cortex-a72}, @samp{cortex-a73}, @samp{exynos-m1}, @samp{falkor},
> -@samp{qdf24xx}, @samp{xgene1}, @samp{vulcan}, @samp{thunderx},
> +@samp{cortex-a72}, @samp{cortex-a73}, @samp{exynos-m1},
> +@samp{xgene1}, @samp{vulcan}, @samp{thunderx},
> @samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81},
> @samp{thunderxt83}, @samp{thunderx2t99}, @samp{cortex-a57.cortex-a53},
> @samp{cortex-a72.cortex-a53}, @samp{cortex-a73.cortex-a35},
In both the original patch, and the backport, you're modifying the
AArch64 options here. I'd expect the edits to be to the AArch32 options
(these start somewhere around line 15,000).
Thanks,
James
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH, ARM/AArch64] drop aarch32 support for falkor/qdf24xx
2017-06-12 10:40 ` James Greenhalgh
@ 2017-06-23 21:46 ` Jim Wilson
0 siblings, 0 replies; 11+ messages in thread
From: Jim Wilson @ 2017-06-23 21:46 UTC (permalink / raw)
To: James Greenhalgh; +Cc: Richard Earnshaw (lists), gcc-patches, nd
[-- Attachment #1: Type: text/plain, Size: 603 bytes --]
On Mon, Jun 12, 2017 at 3:40 AM, James Greenhalgh
<james.greenhalgh@arm.com> wrote:
> In both the original patch, and the backport, you're modifying the
> AArch64 options here. I'd expect the edits to be to the AArch32 options
> (these start somewhere around line 15,000).
Yes, I screwed this up. Richard Earnshaw already fixed the ARM Option
list in one of his -mcpu patches. I checked in a fix for the AArch64
Option list under the obvious rule. Tested with a make doc, and using
info to look at the docs to make sure that they are right.
I will fix the gcc-7 backport before I check it in.
Jim
[-- Attachment #2: aarch64-option.patch --]
[-- Type: text/x-patch, Size: 898 bytes --]
gcc/
* doc/invoke.texi (AArch64 Options, -mtune): Re-add falkor and
qdf24xx.
Index: doc/invoke.texi
===================================================================
--- doc/invoke.texi (revision 249611)
+++ doc/invoke.texi (working copy)
@@ -14079,7 +14079,8 @@ Specify the name of the target processor for which
performance of the code. Permissible values for this option are:
@samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55},
@samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75},
-@samp{exynos-m1}, @samp{xgene1}, @samp{vulcan}, @samp{thunderx},
+@samp{exynos-m1}, @samp{falkor}, @samp{qdf24xx},
+@samp{xgene1}, @samp{vulcan}, @samp{thunderx},
@samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81},
@samp{thunderxt83}, @samp{thunderx2t99}, @samp{cortex-a57.cortex-a53},
@samp{cortex-a72.cortex-a53}, @samp{cortex-a73.cortex-a35},
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2017-06-23 21:46 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-05-12 3:52 [PATCH, ARM/AArch64] drop aarch32 support for falkor/qdf24xx Jim Wilson
2017-05-24 14:12 ` Richard Earnshaw (lists)
2017-05-24 14:20 ` Jim Wilson
2017-05-24 15:20 ` Richard Earnshaw (lists)
2017-05-24 16:05 ` Jim Wilson
2017-05-24 16:30 ` Richard Earnshaw (lists)
2017-05-25 9:29 ` Richard Earnshaw (lists)
2017-06-09 20:03 ` Jim Wilson
2017-06-10 9:44 ` Richard Earnshaw (lists)
2017-06-12 10:40 ` James Greenhalgh
2017-06-23 21:46 ` Jim Wilson
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