From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 12678 invoked by alias); 7 Sep 2011 08:28:57 -0000 Received: (qmail 12494 invoked by uid 22791); 7 Sep 2011 08:28:55 -0000 X-SWARE-Spam-Status: No, hits=-2.6 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from mail-yx0-f175.google.com (HELO mail-yx0-f175.google.com) (209.85.213.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 07 Sep 2011 08:28:41 +0000 Received: by yxl11 with SMTP id 11so3660767yxl.20 for ; Wed, 07 Sep 2011 01:28:41 -0700 (PDT) MIME-Version: 1.0 Received: by 10.42.154.136 with SMTP id q8mr5712250icw.109.1315384121020; Wed, 07 Sep 2011 01:28:41 -0700 (PDT) Received: by 10.231.31.4 with HTTP; Wed, 7 Sep 2011 01:28:40 -0700 (PDT) In-Reply-To: <4E60C110.4030407@codesourcery.com> References: <4E5F71A1.4050207@codesourcery.com> <4E60C110.4030407@codesourcery.com> Date: Wed, 07 Sep 2011 09:12:00 -0000 Message-ID: Subject: Re: ARM: Emit conditions in push_multi From: Ramana Radhakrishnan To: Bernd Schmidt Cc: GCC Patches Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2011-09/txt/msg00464.txt.bz2 On 2 September 2011 12:42, Bernd Schmidt wrote: > On 09/02/11 12:35, Ramana Radhakrishnan wrote: >> On 1 September 2011 12:50, Bernd Schmidt wrote: >>> Shrink-wrapping tests on ARM had one additional failure, which I could >>> track down to a stmfd instruction being emitted where an stmhifd was >>> intended. The following patch fixes the testcase; full tests running >>> now. Ok? >> >> IIUC this should have been a result of conditionalizing the prologue >> saves by the CCFSM state machine in ARM state > > Correct. > >> given that the push >> instruction below doesn't have the conditional markers. > > Although I'm not sure how you arrived at this? Thumb insns can't be > conditional anyway? IT blocks in Thumb2 and the predicable attribute means we can generate some amount of conditional instruction in T2 state. I just looked at that patch as it was and didn't remember whether the pattern had a predicable attribute set on it ( in which case you would have seen the failure in Thumb2). Thus if the failure came in ARM state alone it had to be from the CCFSM state machine. It's probably worth-while just putting out the %? marker in that case anyway for the push instruction given that the only way this is likely to be seen is if someday we mark this as predicable :) > >> =A0In which case >> the routines to emit the asm for the VFP registers( vfp_output_fstmfd? >> ) should also be checked for this issue. > > Hmm, ok. I found two more places which looked suspicious. New version, > untested so far. What's "sfmfd"? That doesn't occur in my manual. sfmfd an FPA instruction should be conditionalizable given it's in the co-processor space. cheers Ramana