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Date: Mon, 01 Aug 2011 15:43:00 -0000
Message-ID: <CACUk7=XUhSw3qfURveJuz8+szhtOnojtMS=ka5YsCKZQPtejMg@mail.gmail.com>
Subject: Re: [Patch 4/4] ARM 64 bit sync atomic operations [V2]
From: Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
To: "Dr. David Alan Gilbert" <david.gilbert@linaro.org>
Cc: gcc-patches@gcc.gnu.org, rth@redhat.com, joseph@codesourcery.com, 	patches@linaro.org
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On 26 July 2011 10:02, Dr. David Alan Gilbert <david.gilbert@linaro.org> wr=
ote:
>
> =A0 =A0 =A0 =A0gcc/
> =A0 =A0 =A0 =A0* config/arm/arm.c (TARGET_HAVE_DMB_MCR) MCR Not available=
 in Thumb1
> =A0 =A0 =A0 =A0 =A0but is available on armv6

`:' after (TARGET_HAVE_DMB_MCR) and something like

`Disable for Thumb1.'

instead of what's on there.

>
> =A0/* Nonzero if this chip implements a memory barrier via CP15. =A0*/
> -#define TARGET_HAVE_DMB_MCR =A0 =A0(arm_arch6k && ! TARGET_HAVE_DMB)
> +#define TARGET_HAVE_DMB_MCR =A0 =A0(arm_arch6 && ! TARGET_HAVE_DMB \
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0&& ! TAR=
GET_THUMB1)

Otherwise OK for trunk and afflicted release branches since this
really is a bug fix.

cheers
Ramana