* Re: [PATCH, ARM] ICE when building kernel raid6 neon code
[not found] <xilhiby0142cs0le48qgs52q.1389786995121@email.android.com>
@ 2014-01-16 5:44 ` Zhenqiang Chen
2014-01-27 17:07 ` Ramana Radhakrishnan
0 siblings, 1 reply; 6+ messages in thread
From: Zhenqiang Chen @ 2014-01-16 5:44 UTC (permalink / raw)
To: Ramana Radhakrishnan; +Cc: gcc-patches, Richard Earnshaw
[-- Attachment #1: Type: text/plain, Size: 3504 bytes --]
Thanks for comments.
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59837
The patch with a test case is attached.
ChangeLog:
2014-01-16 Zhenqiang Chen <zhenqiang.chen@linaro.org>
PR target/59837
* config/arm/arm.c (arm_emit_vfp_multi_reg_pop): Do not add
REG_CFA_ADJUST_CFA NOTE if shrink-wrap is not enabled.
testsuite/ChangeLog:
2014-01-16 Zhenqiang Chen <zhenqiang.chen@linaro.org>
* gcc.target/arm/pr59837.c: New testcase.
On 15 January 2014 19:56, Ramana Radhakrishnan
<Ramana.Radhakrishnan@arm.com> wrote:
> Please also create a bugzilla entry for this and use the pr number here.
>
> Ramana
>
>
> Sent from Samsung Mobile
>
>
>
> -------- Original message --------
> From: Zhenqiang Chen <zhenqiang.chen@linaro.org>
> Date:
> To: gcc-patches@gcc.gnu.org
> Cc: Richard Earnshaw <Richard.Earnshaw@arm.com>,Ramana Radhakrishnan
> <Ramana.Radhakrishnan@arm.com>
> Subject: [PATCH, ARM] ICE when building kernel raid6 neon code
>
>
> Hi,
>
> The patch fixes ICE when building kernel raid6 neon code.
>
> lib/raid6/neon4.c: In function 'raid6_
>
> neon4_gen_syndrome_real':
> lib/raid6/neon4.c:113:1: internal compiler error: in
> dwarf2out_frame_debug_adjust_cfa, at dwarf2cfi.c:1090
> }
>
> https://bugs.launchpad.net/gcc-linaro/+bug/1268893
>
> Root cause:
> When expanding epilogue, REG_CFA_ADJUST_CFA NOTE is added to handle
> dwarf info issue for shrink-wrap. But for TARGET_APCS_FRAME,
> shrink-wrap is disabled. And not all dwarf info in
> arm_expand_epilogue_apcs_frame are correctly updated.
> arm_emit_vfp_multi_reg_pop is called by both
> arm_expand_epilogue_apcs_frame and arm_expand_epilogue. So we should
> not add the NOTE in arm_emit_vfp_multi_reg_pop if shrink-wrap is not
> enabled.
>
> Boot strap and no make check regression on ARM Chromebook.
>
> OK for trunk?
>
> Thanks!
> -Zhenqiang
>
> ChangeLog:
> 2014-01-15 Zhenqiang Chen <zhenqiang.chen@linaro.org>
>
> * config/arm/arm.c (arm_emit_vfp_multi_reg_pop): Do not add
> REG_CFA_ADJUST_CFA NOTE if shrink-wrap is not enabled.
>
> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
> index 18196b3..1ccb796 100644
> --- a/gcc/config/arm/arm.c
> +++ b/gcc/config/arm/arm.c
> @@ -19890,8 +19890,12 @@ arm_emit_vfp_multi_reg_pop (int first_reg,
> int num_regs, rtx base_reg)
> par = emit_insn (par);
> REG_NOTES (par) = dwarf;
>
> - arm_add_cfa_adjust_cfa_note (par, 2 * UNITS_PER_WORD * num_regs,
> - base_reg, base_reg);
> + /* REG_CFA_ADJUST_CFA NOTE is added to handle dwarf info issue when
> + shrink-wrap is enabled. So when shrink-wrap is not enabled, we should
> + not add the note. */
> + if (flag_shrink_wrap)
> + arm_add_cfa_adjust_cfa_note (par, 2 * UNITS_PER_WORD * num_regs,
> + base_reg, base_reg);
> }
>
> /* Generate and emit a pattern that will be recognized as LDRD
> pattern. If even
>
>
> -- IMPORTANT NOTICE: The contents of this email and any attachments are
> confidential and may also be privileged. If you are not the intended
> recipient, please notify the sender immediately and do not disclose the
> contents to any other person, use it for any purpose, or store or copy the
> information in any medium. Thank you.
>
> ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
> Registered in England & Wales, Company No: 2557590
> ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
> Registered in England & Wales, Company No: 2548782
[-- Attachment #2: pr59837.patch --]
[-- Type: text/x-patch, Size: 3571 bytes --]
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 18196b3..1ccb796 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -19890,8 +19890,12 @@ arm_emit_vfp_multi_reg_pop (int first_reg, int num_regs, rtx base_reg)
par = emit_insn (par);
REG_NOTES (par) = dwarf;
- arm_add_cfa_adjust_cfa_note (par, 2 * UNITS_PER_WORD * num_regs,
- base_reg, base_reg);
+ /* REG_CFA_ADJUST_CFA NOTE is added to handle dwarf info issue when
+ shrink-wrap is enabled. So when shrink-wrap is not enabled, we should
+ not add the note. */
+ if (flag_shrink_wrap)
+ arm_add_cfa_adjust_cfa_note (par, 2 * UNITS_PER_WORD * num_regs,
+ base_reg, base_reg);
}
/* Generate and emit a pattern that will be recognized as LDRD pattern. If even
diff --git a/gcc/testsuite/gcc.target/arm/pr59837.c b/gcc/testsuite/gcc.target/arm/pr59837.c
new file mode 100644
index 0000000..9057f64
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr59837.c
@@ -0,0 +1,79 @@
+/* { dg-do compile { target arm_neon } } */
+/* { dg-options " -Os -fno-omit-frame-pointer -mapcs -mabi=aapcs-linux -marm -mfloat-abi=softfp -g " } */
+
+#include <arm_neon.h>
+
+typedef uint8x16_t unative_t;
+static inline unative_t SHLBYTE(unative_t v)
+{
+ return vshlq_n_u8(v, 1);
+}
+
+static inline unative_t MASK(unative_t v)
+{
+ const uint8x16_t temp = ((unative_t){0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0});
+ return (unative_t)vcltq_s8((int8x16_t)v, (int8x16_t)temp);
+}
+
+void raid6_neon4_gen_syndrome_real(int disks, unsigned long bytes, void **ptrs)
+{
+ uint8_t **dptr = (uint8_t **)ptrs;
+ uint8_t *p, *q;
+ int d, z, z0;
+
+ register unative_t wd0, wq0, wp0, w10, w20;
+ register unative_t wd1, wq1, wp1, w11, w21;
+ register unative_t wd2, wq2, wp2, w12, w22;
+ register unative_t wd3, wq3, wp3, w13, w23;
+ const unative_t x1d = ((unative_t){0x1d,0x1d,0x1d,0x1d, 0x1d,0x1d,0x1d,0x1d, 0x1d,0x1d,0x1d,0x1d, 0x1d,0x1d,0x1d,0x1d});
+
+ z0 = disks - 3;
+ p = dptr[z0+1];
+ q = dptr[z0+2];
+
+ for ( d = 0 ; d < bytes ; d += sizeof(unative_t)*4 ) {
+ wq0 = wp0 = vld1q_u8(&dptr[z0][d+0*sizeof(unative_t)]);
+ wq1 = wp1 = vld1q_u8(&dptr[z0][d+1*sizeof(unative_t)]);
+ wq2 = wp2 = vld1q_u8(&dptr[z0][d+2*sizeof(unative_t)]);
+ wq3 = wp3 = vld1q_u8(&dptr[z0][d+3*sizeof(unative_t)]);
+ for ( z = z0-1 ; z >= 0 ; z-- ) {
+ wd0 = vld1q_u8(&dptr[z][d+0*sizeof(unative_t)]);
+ wd1 = vld1q_u8(&dptr[z][d+1*sizeof(unative_t)]);
+ wd2 = vld1q_u8(&dptr[z][d+2*sizeof(unative_t)]);
+ wd3 = vld1q_u8(&dptr[z][d+3*sizeof(unative_t)]);
+ wp0 = veorq_u8(wp0, wd0);
+ wp1 = veorq_u8(wp1, wd1);
+ wp2 = veorq_u8(wp2, wd2);
+ wp3 = veorq_u8(wp3, wd3);
+ w20 = MASK(wq0);
+ w21 = MASK(wq1);
+ w22 = MASK(wq2);
+ w23 = MASK(wq3);
+ w10 = SHLBYTE(wq0);
+ w11 = SHLBYTE(wq1);
+ w12 = SHLBYTE(wq2);
+ w13 = SHLBYTE(wq3);
+
+ w20 = vandq_u8(w20, x1d);
+ w21 = vandq_u8(w21, x1d);
+ w22 = vandq_u8(w22, x1d);
+ w23 = vandq_u8(w23, x1d);
+ w10 = veorq_u8(w10, w20);
+ w11 = veorq_u8(w11, w21);
+ w12 = veorq_u8(w12, w22);
+ w13 = veorq_u8(w13, w23);
+ wq0 = veorq_u8(w10, wd0);
+ wq1 = veorq_u8(w11, wd1);
+ wq2 = veorq_u8(w12, wd2);
+ wq3 = veorq_u8(w13, wd3);
+ }
+ vst1q_u8(&p[d+sizeof(unative_t)*0], wp0);
+ vst1q_u8(&p[d+sizeof(unative_t)*1], wp1);
+ vst1q_u8(&p[d+sizeof(unative_t)*2], wp2);
+ vst1q_u8(&p[d+sizeof(unative_t)*3], wp3);
+ vst1q_u8(&q[d+sizeof(unative_t)*0], wq0);
+ vst1q_u8(&q[d+sizeof(unative_t)*1], wq1);
+ vst1q_u8(&q[d+sizeof(unative_t)*2], wq2);
+ vst1q_u8(&q[d+sizeof(unative_t)*3], wq3);
+ }
+}
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH, ARM] ICE when building kernel raid6 neon code
2014-01-16 5:44 ` [PATCH, ARM] ICE when building kernel raid6 neon code Zhenqiang Chen
@ 2014-01-27 17:07 ` Ramana Radhakrishnan
2014-01-28 3:37 ` Zhenqiang Chen
0 siblings, 1 reply; 6+ messages in thread
From: Ramana Radhakrishnan @ 2014-01-27 17:07 UTC (permalink / raw)
To: Zhenqiang Chen; +Cc: Ramana Radhakrishnan, gcc-patches, Richard Earnshaw
On Thu, Jan 16, 2014 at 5:44 AM, Zhenqiang Chen
<zhenqiang.chen@linaro.org> wrote:
> Thanks for comments.
>
> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59837
>
> The patch with a test case is attached.
> +/* { dg-options " -Os -fno-omit-frame-pointer -mapcs -mabi=aapcs-linux -marm -mfloat-abi=softfp -g " } */
Can you instead do ?
{ dg-options "-Os -fno-omit-frame-pointer -mapcs" }
{ dg-add-options arm_neon }
I don't like this as it as it stands because the test relies on the
compiler being configured for neon by default.
regards
Ramana
>
> ChangeLog:
> 2014-01-16 Zhenqiang Chen <zhenqiang.chen@linaro.org>
>
> PR target/59837
> * config/arm/arm.c (arm_emit_vfp_multi_reg_pop): Do not add
> REG_CFA_ADJUST_CFA NOTE if shrink-wrap is not enabled.
>
> testsuite/ChangeLog:
> 2014-01-16 Zhenqiang Chen <zhenqiang.chen@linaro.org>
>
> * gcc.target/arm/pr59837.c: New testcase.
>
> On 15 January 2014 19:56, Ramana Radhakrishnan
> <Ramana.Radhakrishnan@arm.com> wrote:
>> Please also create a bugzilla entry for this and use the pr number here.
>>
>> Ramana
>>
>>
>> Sent from Samsung Mobile
>>
>>
>>
>> -------- Original message --------
>> From: Zhenqiang Chen <zhenqiang.chen@linaro.org>
>> Date:
>> To: gcc-patches@gcc.gnu.org
>> Cc: Richard Earnshaw <Richard.Earnshaw@arm.com>,Ramana Radhakrishnan
>> <Ramana.Radhakrishnan@arm.com>
>> Subject: [PATCH, ARM] ICE when building kernel raid6 neon code
>>
>>
>> Hi,
>>
>> The patch fixes ICE when building kernel raid6 neon code.
>>
>> lib/raid6/neon4.c: In function 'raid6_
>>
>> neon4_gen_syndrome_real':
>> lib/raid6/neon4.c:113:1: internal compiler error: in
>> dwarf2out_frame_debug_adjust_cfa, at dwarf2cfi.c:1090
>> }
>>
>> https://bugs.launchpad.net/gcc-linaro/+bug/1268893
>>
>> Root cause:
>> When expanding epilogue, REG_CFA_ADJUST_CFA NOTE is added to handle
>> dwarf info issue for shrink-wrap. But for TARGET_APCS_FRAME,
>> shrink-wrap is disabled. And not all dwarf info in
>> arm_expand_epilogue_apcs_frame are correctly updated.
>> arm_emit_vfp_multi_reg_pop is called by both
>> arm_expand_epilogue_apcs_frame and arm_expand_epilogue. So we should
>> not add the NOTE in arm_emit_vfp_multi_reg_pop if shrink-wrap is not
>> enabled.
>>
>> Boot strap and no make check regression on ARM Chromebook.
>>
>> OK for trunk?
>>
>> Thanks!
>> -Zhenqiang
>>
>> ChangeLog:
>> 2014-01-15 Zhenqiang Chen <zhenqiang.chen@linaro.org>
>>
>> * config/arm/arm.c (arm_emit_vfp_multi_reg_pop): Do not add
>> REG_CFA_ADJUST_CFA NOTE if shrink-wrap is not enabled.
>>
>> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
>> index 18196b3..1ccb796 100644
>> --- a/gcc/config/arm/arm.c
>> +++ b/gcc/config/arm/arm.c
>> @@ -19890,8 +19890,12 @@ arm_emit_vfp_multi_reg_pop (int first_reg,
>> int num_regs, rtx base_reg)
>> par = emit_insn (par);
>> REG_NOTES (par) = dwarf;
>>
>> - arm_add_cfa_adjust_cfa_note (par, 2 * UNITS_PER_WORD * num_regs,
>> - base_reg, base_reg);
>> + /* REG_CFA_ADJUST_CFA NOTE is added to handle dwarf info issue when
>> + shrink-wrap is enabled. So when shrink-wrap is not enabled, we should
>> + not add the note. */
>> + if (flag_shrink_wrap)
>> + arm_add_cfa_adjust_cfa_note (par, 2 * UNITS_PER_WORD * num_regs,
>> + base_reg, base_reg);
>> }
>>
>> /* Generate and emit a pattern that will be recognized as LDRD
>> pattern. If even
>>
>>
>> -- IMPORTANT NOTICE: The contents of this email and any attachments are
>> confidential and may also be privileged. If you are not the intended
>> recipient, please notify the sender immediately and do not disclose the
>> contents to any other person, use it for any purpose, or store or copy the
>> information in any medium. Thank you.
>>
>> ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
>> Registered in England & Wales, Company No: 2557590
>> ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
>> Registered in England & Wales, Company No: 2548782
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH, ARM] ICE when building kernel raid6 neon code
2014-01-27 17:07 ` Ramana Radhakrishnan
@ 2014-01-28 3:37 ` Zhenqiang Chen
2014-03-06 8:09 ` Ramana Radhakrishnan
0 siblings, 1 reply; 6+ messages in thread
From: Zhenqiang Chen @ 2014-01-28 3:37 UTC (permalink / raw)
To: Ramana Radhakrishnan; +Cc: Ramana Radhakrishnan, gcc-patches, Richard Earnshaw
[-- Attachment #1: Type: text/plain, Size: 4609 bytes --]
On 28 January 2014 01:07, Ramana Radhakrishnan
<ramana.gcc@googlemail.com> wrote:
> On Thu, Jan 16, 2014 at 5:44 AM, Zhenqiang Chen
> <zhenqiang.chen@linaro.org> wrote:
>> Thanks for comments.
>>
>> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59837
>>
>> The patch with a test case is attached.
>
>
>> +/* { dg-options " -Os -fno-omit-frame-pointer -mapcs -mabi=aapcs-linux -marm -mfloat-abi=softfp -g " } */
>
> Can you instead do ?
>
> { dg-options "-Os -fno-omit-frame-pointer -mapcs" }
> { dg-add-options arm_neon }
>
> I don't like this as it as it stands because the test relies on the
> compiler being configured for neon by default.
Thanks. The test case is updated according to your comments.
The patch is also updated to skip dwarf info in function
arm_emit_multi_reg_pop when shrink-wrap is not enabled. A new test
case (pr59837-1.c) is added to reproduce the issue. And I double check
the arm_expand_epilogue_apcs_frame. There is no more function which
adds REG_CFA_ADJUST_CFA NOTE.
Thanks!
-Zhenqiang
>> 2014-01-16 Zhenqiang Chen <zhenqiang.chen@linaro.org>
>>
>> PR target/59837
>> * config/arm/arm.c (arm_emit_vfp_multi_reg_pop): Do not add
>> REG_CFA_ADJUST_CFA NOTE if shrink-wrap is not enabled.
>>
>> testsuite/ChangeLog:
>> 2014-01-16 Zhenqiang Chen <zhenqiang.chen@linaro.org>
>>
>> * gcc.target/arm/pr59837.c: New testcase.
>>
>> On 15 January 2014 19:56, Ramana Radhakrishnan
>> <Ramana.Radhakrishnan@arm.com> wrote:
>>> Please also create a bugzilla entry for this and use the pr number here.
>>>
>>> Ramana
>>>
>>>
>>> Sent from Samsung Mobile
>>>
>>>
>>>
>>> -------- Original message --------
>>> From: Zhenqiang Chen <zhenqiang.chen@linaro.org>
>>> Date:
>>> To: gcc-patches@gcc.gnu.org
>>> Cc: Richard Earnshaw <Richard.Earnshaw@arm.com>,Ramana Radhakrishnan
>>> <Ramana.Radhakrishnan@arm.com>
>>> Subject: [PATCH, ARM] ICE when building kernel raid6 neon code
>>>
>>>
>>> Hi,
>>>
>>> The patch fixes ICE when building kernel raid6 neon code.
>>>
>>> lib/raid6/neon4.c: In function 'raid6_
>>>
>>> neon4_gen_syndrome_real':
>>> lib/raid6/neon4.c:113:1: internal compiler error: in
>>> dwarf2out_frame_debug_adjust_cfa, at dwarf2cfi.c:1090
>>> }
>>>
>>> https://bugs.launchpad.net/gcc-linaro/+bug/1268893
>>>
>>> Root cause:
>>> When expanding epilogue, REG_CFA_ADJUST_CFA NOTE is added to handle
>>> dwarf info issue for shrink-wrap. But for TARGET_APCS_FRAME,
>>> shrink-wrap is disabled. And not all dwarf info in
>>> arm_expand_epilogue_apcs_frame are correctly updated.
>>> arm_emit_vfp_multi_reg_pop is called by both
>>> arm_expand_epilogue_apcs_frame and arm_expand_epilogue. So we should
>>> not add the NOTE in arm_emit_vfp_multi_reg_pop if shrink-wrap is not
>>> enabled.
>>>
>>> Boot strap and no make check regression on ARM Chromebook.
>>>
>>> OK for trunk?
>>>
>>> Thanks!
>>> -Zhenqiang
>>>
>>> ChangeLog:
>>> 2014-01-15 Zhenqiang Chen <zhenqiang.chen@linaro.org>
>>>
>>> * config/arm/arm.c (arm_emit_vfp_multi_reg_pop): Do not add
>>> REG_CFA_ADJUST_CFA NOTE if shrink-wrap is not enabled.
>>>
>>> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
>>> index 18196b3..1ccb796 100644
>>> --- a/gcc/config/arm/arm.c
>>> +++ b/gcc/config/arm/arm.c
>>> @@ -19890,8 +19890,12 @@ arm_emit_vfp_multi_reg_pop (int first_reg,
>>> int num_regs, rtx base_reg)
>>> par = emit_insn (par);
>>> REG_NOTES (par) = dwarf;
>>>
>>> - arm_add_cfa_adjust_cfa_note (par, 2 * UNITS_PER_WORD * num_regs,
>>> - base_reg, base_reg);
>>> + /* REG_CFA_ADJUST_CFA NOTE is added to handle dwarf info issue when
>>> + shrink-wrap is enabled. So when shrink-wrap is not enabled, we should
>>> + not add the note. */
>>> + if (flag_shrink_wrap)
>>> + arm_add_cfa_adjust_cfa_note (par, 2 * UNITS_PER_WORD * num_regs,
>>> + base_reg, base_reg);
>>> }
>>>
>>> /* Generate and emit a pattern that will be recognized as LDRD
>>> pattern. If even
>>>
>>>
>>> -- IMPORTANT NOTICE: The contents of this email and any attachments are
>>> confidential and may also be privileged. If you are not the intended
>>> recipient, please notify the sender immediately and do not disclose the
>>> contents to any other person, use it for any purpose, or store or copy the
>>> information in any medium. Thank you.
>>>
>>> ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
>>> Registered in England & Wales, Company No: 2557590
>>> ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
>>> Registered in England & Wales, Company No: 2548782
[-- Attachment #2: pr59837.patch --]
[-- Type: text/x-patch, Size: 4335 bytes --]
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index fc81bf6..4758c3b 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -19816,7 +19816,7 @@ arm_emit_multi_reg_pop (unsigned long saved_regs_mask)
par = emit_insn (par);
REG_NOTES (par) = dwarf;
- if (!return_in_pc)
+ if (!return_in_pc && flag_shrink_wrap)
arm_add_cfa_adjust_cfa_note (par, UNITS_PER_WORD * num_regs,
stack_pointer_rtx, stack_pointer_rtx);
}
@@ -19890,8 +19890,12 @@ arm_emit_vfp_multi_reg_pop (int first_reg, int num_regs, rtx base_reg)
par = emit_insn (par);
REG_NOTES (par) = dwarf;
- arm_add_cfa_adjust_cfa_note (par, 2 * UNITS_PER_WORD * num_regs,
- base_reg, base_reg);
+ /* REG_CFA_ADJUST_CFA NOTE is added to handle dwarf info issue when
+ shrink-wrap is enabled. So when shrink-wrap is not enabled, we should
+ not add the note. */
+ if (flag_shrink_wrap)
+ arm_add_cfa_adjust_cfa_note (par, 2 * UNITS_PER_WORD * num_regs,
+ base_reg, base_reg);
}
/* Generate and emit a pattern that will be recognized as LDRD pattern. If even
diff --git a/gcc/testsuite/gcc.target/arm/pr59837-1.c b/gcc/testsuite/gcc.target/arm/pr59837-1.c
new file mode 100644
index 0000000..95c2b2f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr59837-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-Os -fno-omit-frame-pointer -mapcs -g " } */
+
+extern void baz (int);
+
+static int i;
+
+void bar ()
+{
+ baz (i);
+}
diff --git a/gcc/testsuite/gcc.target/arm/pr59837.c b/gcc/testsuite/gcc.target/arm/pr59837.c
new file mode 100644
index 0000000..05e22f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr59837.c
@@ -0,0 +1,80 @@
+/* { dg-do compile } */
+/* { dg-options "-Os -fno-omit-frame-pointer -mapcs -g " } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+typedef uint8x16_t unative_t;
+static inline unative_t SHLBYTE (unative_t v)
+{
+ return vshlq_n_u8 (v, 1);
+}
+
+static inline unative_t MASK (unative_t v)
+{
+ const uint8x16_t temp = ((unative_t){0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0});
+ return (unative_t)vcltq_s8 ((int8x16_t)v, (int8x16_t)temp);
+}
+
+void raid6_neon4_gen_syndrome_real (int disks, unsigned long bytes, void **ptrs)
+{
+ uint8_t **dptr = (uint8_t **)ptrs;
+ uint8_t *p, *q;
+ int d, z, z0;
+
+ register unative_t wd0, wq0, wp0, w10, w20;
+ register unative_t wd1, wq1, wp1, w11, w21;
+ register unative_t wd2, wq2, wp2, w12, w22;
+ register unative_t wd3, wq3, wp3, w13, w23;
+ const unative_t x1d = ((unative_t){0x1d,0x1d,0x1d,0x1d, 0x1d,0x1d,0x1d,0x1d, 0x1d,0x1d,0x1d,0x1d, 0x1d,0x1d,0x1d,0x1d});
+
+ z0 = disks - 3;
+ p = dptr[z0 + 1];
+ q = dptr[z0 + 2];
+
+ for (d = 0 ; d < bytes; d += sizeof (unative_t) * 4) {
+ wq0 = wp0 = vld1q_u8 (&dptr[z0][d + 0*sizeof (unative_t)]);
+ wq1 = wp1 = vld1q_u8 (&dptr[z0][d + 1*sizeof (unative_t)]);
+ wq2 = wp2 = vld1q_u8 (&dptr[z0][d + 2*sizeof (unative_t)]);
+ wq3 = wp3 = vld1q_u8 (&dptr[z0][d + 3*sizeof (unative_t)]);
+ for (z = z0 - 1; z >= 0; z--) {
+ wd0 = vld1q_u8 (&dptr[z][d + 0*sizeof (unative_t)]);
+ wd1 = vld1q_u8 (&dptr[z][d + 1*sizeof (unative_t)]);
+ wd2 = vld1q_u8 (&dptr[z][d + 2*sizeof (unative_t)]);
+ wd3 = vld1q_u8 (&dptr[z][d + 3*sizeof (unative_t)]);
+ wp0 = veorq_u8 (wp0, wd0);
+ wp1 = veorq_u8 (wp1, wd1);
+ wp2 = veorq_u8 (wp2, wd2);
+ wp3 = veorq_u8 (wp3, wd3);
+ w20 = MASK (wq0);
+ w21 = MASK (wq1);
+ w22 = MASK (wq2);
+ w23 = MASK (wq3);
+ w10 = SHLBYTE (wq0);
+ w11 = SHLBYTE (wq1);
+ w12 = SHLBYTE (wq2);
+ w13 = SHLBYTE (wq3);
+
+ w20 = vandq_u8 (w20, x1d);
+ w21 = vandq_u8 (w21, x1d);
+ w22 = vandq_u8 (w22, x1d);
+ w23 = vandq_u8 (w23, x1d);
+ w10 = veorq_u8 (w10, w20);
+ w11 = veorq_u8 (w11, w21);
+ w12 = veorq_u8 (w12, w22);
+ w13 = veorq_u8 (w13, w23);
+ wq0 = veorq_u8 (w10, wd0);
+ wq1 = veorq_u8 (w11, wd1);
+ wq2 = veorq_u8 (w12, wd2);
+ wq3 = veorq_u8 (w13, wd3);
+ }
+ vst1q_u8 (&p[d + sizeof (unative_t)*0], wp0);
+ vst1q_u8 (&p[d + sizeof (unative_t)*1], wp1);
+ vst1q_u8 (&p[d + sizeof (unative_t)*2], wp2);
+ vst1q_u8 (&p[d + sizeof (unative_t)*3], wp3);
+ vst1q_u8 (&q[d + sizeof (unative_t)*0], wq0);
+ vst1q_u8 (&q[d + sizeof (unative_t)*1], wq1);
+ vst1q_u8 (&q[d + sizeof (unative_t)*2], wq2);
+ vst1q_u8 (&q[d + sizeof (unative_t)*3], wq3);
+ }
+}
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH, ARM] ICE when building kernel raid6 neon code
2014-01-28 3:37 ` Zhenqiang Chen
@ 2014-03-06 8:09 ` Ramana Radhakrishnan
0 siblings, 0 replies; 6+ messages in thread
From: Ramana Radhakrishnan @ 2014-03-06 8:09 UTC (permalink / raw)
To: Zhenqiang Chen; +Cc: Ramana Radhakrishnan, gcc-patches, Richard Earnshaw
On Tue, Jan 28, 2014 at 3:37 AM, Zhenqiang Chen
<zhenqiang.chen@linaro.org> wrote:
> On 28 January 2014 01:07, Ramana Radhakrishnan
> <ramana.gcc@googlemail.com> wrote:
>> On Thu, Jan 16, 2014 at 5:44 AM, Zhenqiang Chen
>> <zhenqiang.chen@linaro.org> wrote:
>>> Thanks for comments.
>>>
>>> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59837
>>>
>>> The patch with a test case is attached.
>>
>>
>>> +/* { dg-options " -Os -fno-omit-frame-pointer -mapcs -mabi=aapcs-linux -marm -mfloat-abi=softfp -g " } */
>>
>> Can you instead do ?
>>
>> { dg-options "-Os -fno-omit-frame-pointer -mapcs" }
>> { dg-add-options arm_neon }
>>
>> I don't like this as it as it stands because the test relies on the
>> compiler being configured for neon by default.
>
> Thanks. The test case is updated according to your comments.
>
> The patch is also updated to skip dwarf info in function
> arm_emit_multi_reg_pop when shrink-wrap is not enabled. A new test
> case (pr59837-1.c) is added to reproduce the issue. And I double check
> the arm_expand_epilogue_apcs_frame. There is no more function which
> adds REG_CFA_ADJUST_CFA NOTE.
This is OK if no regressions and an RM doesn't object in 24 hours.
maps-frame is used in the kernel so fixing this up for 4.9 would be
good.
Cheers,
Ramana
>
> Thanks!
> -Zhenqiang
>
>
>>> 2014-01-16 Zhenqiang Chen <zhenqiang.chen@linaro.org>
>>>
>>> PR target/59837
>>> * config/arm/arm.c (arm_emit_vfp_multi_reg_pop): Do not add
>>> REG_CFA_ADJUST_CFA NOTE if shrink-wrap is not enabled.
>>>
>>> testsuite/ChangeLog:
>>> 2014-01-16 Zhenqiang Chen <zhenqiang.chen@linaro.org>
>>>
>>> * gcc.target/arm/pr59837.c: New testcase.
>>>
>>> On 15 January 2014 19:56, Ramana Radhakrishnan
>>> <Ramana.Radhakrishnan@arm.com> wrote:
>>>> Please also create a bugzilla entry for this and use the pr number here.
>>>>
>>>> Ramana
>>>>
>>>>
>>>> Sent from Samsung Mobile
>>>>
>>>>
>>>>
>>>> -------- Original message --------
>>>> From: Zhenqiang Chen <zhenqiang.chen@linaro.org>
>>>> Date:
>>>> To: gcc-patches@gcc.gnu.org
>>>> Cc: Richard Earnshaw <Richard.Earnshaw@arm.com>,Ramana Radhakrishnan
>>>> <Ramana.Radhakrishnan@arm.com>
>>>> Subject: [PATCH, ARM] ICE when building kernel raid6 neon code
>>>>
>>>>
>>>> Hi,
>>>>
>>>> The patch fixes ICE when building kernel raid6 neon code.
>>>>
>>>> lib/raid6/neon4.c: In function 'raid6_
>>>>
>>>> neon4_gen_syndrome_real':
>>>> lib/raid6/neon4.c:113:1: internal compiler error: in
>>>> dwarf2out_frame_debug_adjust_cfa, at dwarf2cfi.c:1090
>>>> }
>>>>
>>>> https://bugs.launchpad.net/gcc-linaro/+bug/1268893
>>>>
>>>> Root cause:
>>>> When expanding epilogue, REG_CFA_ADJUST_CFA NOTE is added to handle
>>>> dwarf info issue for shrink-wrap. But for TARGET_APCS_FRAME,
>>>> shrink-wrap is disabled. And not all dwarf info in
>>>> arm_expand_epilogue_apcs_frame are correctly updated.
>>>> arm_emit_vfp_multi_reg_pop is called by both
>>>> arm_expand_epilogue_apcs_frame and arm_expand_epilogue. So we should
>>>> not add the NOTE in arm_emit_vfp_multi_reg_pop if shrink-wrap is not
>>>> enabled.
>>>>
>>>> Boot strap and no make check regression on ARM Chromebook.
>>>>
>>>> OK for trunk?
>>>>
>>>> Thanks!
>>>> -Zhenqiang
>>>>
>>>> ChangeLog:
>>>> 2014-01-15 Zhenqiang Chen <zhenqiang.chen@linaro.org>
>>>>
>>>> * config/arm/arm.c (arm_emit_vfp_multi_reg_pop): Do not add
>>>> REG_CFA_ADJUST_CFA NOTE if shrink-wrap is not enabled.
>>>>
>>>> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
>>>> index 18196b3..1ccb796 100644
>>>> --- a/gcc/config/arm/arm.c
>>>> +++ b/gcc/config/arm/arm.c
>>>> @@ -19890,8 +19890,12 @@ arm_emit_vfp_multi_reg_pop (int first_reg,
>>>> int num_regs, rtx base_reg)
>>>> par = emit_insn (par);
>>>> REG_NOTES (par) = dwarf;
>>>>
>>>> - arm_add_cfa_adjust_cfa_note (par, 2 * UNITS_PER_WORD * num_regs,
>>>> - base_reg, base_reg);
>>>> + /* REG_CFA_ADJUST_CFA NOTE is added to handle dwarf info issue when
>>>> + shrink-wrap is enabled. So when shrink-wrap is not enabled, we should
>>>> + not add the note. */
>>>> + if (flag_shrink_wrap)
>>>> + arm_add_cfa_adjust_cfa_note (par, 2 * UNITS_PER_WORD * num_regs,
>>>> + base_reg, base_reg);
>>>> }
>>>>
>>>> /* Generate and emit a pattern that will be recognized as LDRD
>>>> pattern. If even
>>>>
>>>>
>>>> -- IMPORTANT NOTICE: The contents of this email and any attachments are
>>>> confidential and may also be privileged. If you are not the intended
>>>> recipient, please notify the sender immediately and do not disclose the
>>>> contents to any other person, use it for any purpose, or store or copy the
>>>> information in any medium. Thank you.
>>>>
>>>> ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
>>>> Registered in England & Wales, Company No: 2557590
>>>> ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ,
>>>> Registered in England & Wales, Company No: 2548782
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH, ARM] ICE when building kernel raid6 neon code
2014-01-15 10:04 Zhenqiang Chen
@ 2014-01-15 11:37 ` Richard Earnshaw
0 siblings, 0 replies; 6+ messages in thread
From: Richard Earnshaw @ 2014-01-15 11:37 UTC (permalink / raw)
To: Zhenqiang Chen; +Cc: gcc-patches, Ramana Radhakrishnan
On 15/01/14 10:04, Zhenqiang Chen wrote:
> Hi,
>
> The patch fixes ICE when building kernel raid6 neon code.
>
> lib/raid6/neon4.c: In function 'raid6_
>
> neon4_gen_syndrome_real':
> lib/raid6/neon4.c:113:1: internal compiler error: in
> dwarf2out_frame_debug_adjust_cfa, at dwarf2cfi.c:1090
> }
>
> https://bugs.launchpad.net/gcc-linaro/+bug/1268893
>
> Root cause:
> When expanding epilogue, REG_CFA_ADJUST_CFA NOTE is added to handle
> dwarf info issue for shrink-wrap. But for TARGET_APCS_FRAME,
> shrink-wrap is disabled. And not all dwarf info in
> arm_expand_epilogue_apcs_frame are correctly updated.
> arm_emit_vfp_multi_reg_pop is called by both
> arm_expand_epilogue_apcs_frame and arm_expand_epilogue. So we should
> not add the NOTE in arm_emit_vfp_multi_reg_pop if shrink-wrap is not
> enabled.
>
> Boot strap and no make check regression on ARM Chromebook.
>
> OK for trunk?
>
> Thanks!
> -Zhenqiang
>
> ChangeLog:
> 2014-01-15 Zhenqiang Chen <zhenqiang.chen@linaro.org>
>
> * config/arm/arm.c (arm_emit_vfp_multi_reg_pop): Do not add
> REG_CFA_ADJUST_CFA NOTE if shrink-wrap is not enabled.
>
> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
> index 18196b3..1ccb796 100644
> --- a/gcc/config/arm/arm.c
> +++ b/gcc/config/arm/arm.c
> @@ -19890,8 +19890,12 @@ arm_emit_vfp_multi_reg_pop (int first_reg,
> int num_regs, rtx base_reg)
> par = emit_insn (par);
> REG_NOTES (par) = dwarf;
>
> - arm_add_cfa_adjust_cfa_note (par, 2 * UNITS_PER_WORD * num_regs,
> - base_reg, base_reg);
> + /* REG_CFA_ADJUST_CFA NOTE is added to handle dwarf info issue when
> + shrink-wrap is enabled. So when shrink-wrap is not enabled, we should
> + not add the note. */
> + if (flag_shrink_wrap)
> + arm_add_cfa_adjust_cfa_note (par, 2 * UNITS_PER_WORD * num_regs,
> + base_reg, base_reg);
> }
>
> /* Generate and emit a pattern that will be recognized as LDRD
> pattern. If even
>
Testcase?
R.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH, ARM] ICE when building kernel raid6 neon code
@ 2014-01-15 10:04 Zhenqiang Chen
2014-01-15 11:37 ` Richard Earnshaw
0 siblings, 1 reply; 6+ messages in thread
From: Zhenqiang Chen @ 2014-01-15 10:04 UTC (permalink / raw)
To: gcc-patches; +Cc: Richard Earnshaw, Ramana Radhakrishnan
Hi,
The patch fixes ICE when building kernel raid6 neon code.
lib/raid6/neon4.c: In function 'raid6_
neon4_gen_syndrome_real':
lib/raid6/neon4.c:113:1: internal compiler error: in
dwarf2out_frame_debug_adjust_cfa, at dwarf2cfi.c:1090
}
https://bugs.launchpad.net/gcc-linaro/+bug/1268893
Root cause:
When expanding epilogue, REG_CFA_ADJUST_CFA NOTE is added to handle
dwarf info issue for shrink-wrap. But for TARGET_APCS_FRAME,
shrink-wrap is disabled. And not all dwarf info in
arm_expand_epilogue_apcs_frame are correctly updated.
arm_emit_vfp_multi_reg_pop is called by both
arm_expand_epilogue_apcs_frame and arm_expand_epilogue. So we should
not add the NOTE in arm_emit_vfp_multi_reg_pop if shrink-wrap is not
enabled.
Boot strap and no make check regression on ARM Chromebook.
OK for trunk?
Thanks!
-Zhenqiang
ChangeLog:
2014-01-15 Zhenqiang Chen <zhenqiang.chen@linaro.org>
* config/arm/arm.c (arm_emit_vfp_multi_reg_pop): Do not add
REG_CFA_ADJUST_CFA NOTE if shrink-wrap is not enabled.
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 18196b3..1ccb796 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -19890,8 +19890,12 @@ arm_emit_vfp_multi_reg_pop (int first_reg,
int num_regs, rtx base_reg)
par = emit_insn (par);
REG_NOTES (par) = dwarf;
- arm_add_cfa_adjust_cfa_note (par, 2 * UNITS_PER_WORD * num_regs,
- base_reg, base_reg);
+ /* REG_CFA_ADJUST_CFA NOTE is added to handle dwarf info issue when
+ shrink-wrap is enabled. So when shrink-wrap is not enabled, we should
+ not add the note. */
+ if (flag_shrink_wrap)
+ arm_add_cfa_adjust_cfa_note (par, 2 * UNITS_PER_WORD * num_regs,
+ base_reg, base_reg);
}
/* Generate and emit a pattern that will be recognized as LDRD
pattern. If even
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2014-03-06 8:09 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2014-01-16 5:44 ` [PATCH, ARM] ICE when building kernel raid6 neon code Zhenqiang Chen
2014-01-27 17:07 ` Ramana Radhakrishnan
2014-01-28 3:37 ` Zhenqiang Chen
2014-03-06 8:09 ` Ramana Radhakrishnan
2014-01-15 10:04 Zhenqiang Chen
2014-01-15 11:37 ` Richard Earnshaw
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