diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index bd8ea8f..c8b3001 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -1162,9 +1162,16 @@
     {
       if (TARGET_32BIT)
         {
-          arm_split_constant (MINUS, SImode, NULL_RTX,
-	                      INTVAL (operands[1]), operands[0],
-	  		      operands[2], optimize && can_create_pseudo_p ());
+	  if (!const_ok_for_arm (INTVAL (operands[1]))
+	      && can_create_pseudo_p ())
+	    {
+	      operands[1] = force_reg (SImode, operands[1]);
+	      emit_insn (gen_subsi3 (operands[0], operands[1], operands[2]));
+	    }
+	  else
+	    arm_split_constant (MINUS, SImode, NULL_RTX,
+				INTVAL (operands[1]), operands[0], operands[2],
+				optimize && can_create_pseudo_p ());
           DONE;
 	}
       else /* TARGET_THUMB1 */
@@ -2077,6 +2084,17 @@
 	      emit_insn (gen_thumb2_zero_extendqisi2_v6 (operands[0],
 							 operands[1]));
 	    }
+	  else if (!(const_ok_for_arm (INTVAL (operands[2]))
+		     || const_ok_for_arm (~INTVAL (operands[2]))
+			/* zero_extendhi instruction is efficient enough.  */
+		     || INTVAL (operands[2]) == 0xffff
+		     || (INTVAL (operands[2]) < 0
+			 && const_ok_for_arm (-INTVAL (operands[2]))))
+		   && can_create_pseudo_p ())
+	    {
+	      operands[2] = force_reg (SImode, operands[2]);
+	      emit_insn (gen_andsi3 (operands[0], operands[1], operands[2]));
+	    }
 	  else
 	    arm_split_constant (AND, SImode, NULL_RTX,
 				INTVAL (operands[2]), operands[0],
@@ -2882,9 +2900,20 @@
     {
       if (TARGET_32BIT)
         {
-          arm_split_constant (IOR, SImode, NULL_RTX,
-	                      INTVAL (operands[2]), operands[0], operands[1],
-			      optimize && can_create_pseudo_p ());
+	  if (!(const_ok_for_arm (INTVAL (operands[2]))
+		|| (TARGET_THUMB2
+		    && const_ok_for_arm (~INTVAL (operands[2])))
+		|| (INTVAL (operands[2]) < 0
+		    && const_ok_for_arm (-INTVAL (operands[2]))))
+	      && can_create_pseudo_p ())
+	    {
+	      operands[2] = force_reg (SImode, operands[2]);
+	      emit_insn (gen_iorsi3 (operands[0], operands[1], operands[2]));
+	    }
+	  else
+	    arm_split_constant (IOR, SImode, NULL_RTX,
+				INTVAL (operands[2]), operands[0], operands[1],
+				optimize && can_create_pseudo_p ());
           DONE;
 	}
       else /* TARGET_THUMB1 */
@@ -3052,9 +3081,18 @@
     {
       if (TARGET_32BIT)
         {
-          arm_split_constant (XOR, SImode, NULL_RTX,
-	                      INTVAL (operands[2]), operands[0], operands[1],
-			      optimize && can_create_pseudo_p ());
+	  if (!(const_ok_for_arm (INTVAL (operands[2]))
+		|| (INTVAL (operands[2]) < 0
+		     && const_ok_for_arm (-INTVAL (operands[2]))))
+	      && can_create_pseudo_p ())
+	    {
+	      operands[2] = force_reg (SImode, operands[2]);
+	      emit_insn (gen_xorsi3 (operands[0], operands[1], operands[2]));
+	    }
+	  else
+	    arm_split_constant (XOR, SImode, NULL_RTX,
+				INTVAL (operands[2]), operands[0], operands[1],
+				optimize && can_create_pseudo_p ());
           DONE;
 	}
       else /* TARGET_THUMB1 */

diff --git a/gcc/testsuite/gcc.target/arm/maskdata.c b/gcc/testsuite/gcc.target/arm/maskdata.c
new file mode 100644
index 0000000..b4231a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/maskdata.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options " -O2 -fno-gcse " }  */
+/* { dg-require-effective-target arm_thumb2_ok } */
+
+#define MASK 0xfe00ff
+void maskdata (int * data, int len)
+{
+   int i = len;
+   for (; i > 0; i -= 2)
+    {
+      data[i] &= MASK;
+      data[i + 1] &= MASK;
+    }
+}
+/* { dg-final { scan-assembler "254" } } */
+/* { dg-final { scan-assembler "255" } } */