[linaro/gcc-4_9-branch] Merge from gcc-4_9-branch and backports

[linaro/gcc-4_9-branch] Merge from gcc-4_9-branch and backports

[Yvan Roux]

Hi all

we have merged the gcc-4_9-branch into linaro/gcc-4_9-branch up to
revision 221341 as r221360.  We have also backported this set of revisions:

* r212011 as r221216 : PR tree-optimization/61607
* r214942 as r221216 : Abstract away marking loops for removal
* r214957 as r221216 : Sanity check removed loops
* r215012 as r221216 : PR bootstrap/63204
* r215016 as r221216 : PR ipa/63196
* r215612 as r221194 : Tighten predicates on SIMD shift intrinsics
* r215722 as r221196 : Wire up vqdmullh_laneq_s16 and vqdmullh_laneq_s32
* r216663 as r221239 : [testsuite] revert changes on
check_effective_target_arm_*_ok
* r217706 as r221240 : [testsuite] new set of Neon intrinsics tests
* r217707 as r221241 : [testsuite] fix vbic/vorn Neon tests
* r217725 as r221339 : Improve modeled latency between FP operations
and FP->GP register moves
* r217780 as r221302 : Adjust generic move costs
* r217852 as r221300 : Add range-check for Symbol + offset addressing
* r217938 as r221301 : Add vector pattern for __builtin_ctz
* r218115 as r221216 : PR tree-optimization/64083
* r218463 as r221242 : [testsuite] Fix vaddl and vaddw tests
* r218486 as r221344 : Bics instruction generation for aarch64
* r218503 as r221344 : additional bics patterns
* r218733 as r221216 : PR tree-optimization/64284
* r218746 as r221216 : PR middle-end/64246
* r219764 as r221242 : [testsuite] Add explicit dependency on Neon
Cumulative Saturation flag
* r219765 as r221242 : [testsuite] Be more verbose, and actually
confirm that a test was checked.
* r219767 as r221242 : [testsuite] Add vld1_lane tests
* r219914 as r221242 : [testsuite] Add vldX_dup test.
* r219917 as r221242 : [testsuite] Add vmla and vmls tests.
* r219918 as r221242 : [testsuite] Add vmla_lane and vmls_lane tests.
* r219919 as r221242 : [testsuite] Add vtrn tests. Refactor vzup and vzip tests.
* r219920 as r221242 : [testsuite] Add vmlal and vmlsl tests.
* r219921 as r221242 : [testsuite] Add vmlal_lane and vmlsl_lane tests.
* r219922 as r221242 : [testsuite] Add vmlal_n and vmlsl_n tests.
* r219930 as r221242 : [testsuite] Add vqdmlal and vqdmlsl tests.
* r219931 as r221242 : [testsuite] Add vqdmlal_lane and vqdmlsl_lane tests
* r219932 as r221242 : [testsuite] Add vqdmlal_n and vqdmlsl_n tests.
* r219934 as r221242 : [testsuite] Add vsli_n and vsri_n tests.
* r219937 as r221242 : [testsuite] Add vsubl tests, put most of the
code in common with vaddl in vXXXl.inc.
* r219938 as r221242 : [testsuite] Add vsubw tests, putting most of
the code in common with vaddw
* r219939 as r221242 : [testsuite] Add vmovn tests.
* r219940 as r221242 : [testsuite] Add vmul_lane tests.
* r219941 as r221242 : [testsuite] Add vmul_n tests.
* r219942 as r221242 : [testsuite] Add vmull tests.
* r219943 as r221242 : [testsuite] Add vmull_lane tests.
* r219944 as r221242 : [testsuite] Add vmull_n tests.
* r219945 as r221242 : [testsuite] Add vqdmulh tests.
* r219946 as r221242 : [testsuite] Add vqdmulh_lane tests.
* r219947 as r221242 : [testsuite] Add vqdmulh_n tests.
* r219948 as r221242 : [testsuite] Add vqdmull tests.
* r219949 as r221242 : [testsuite] Add vqdmull_lane tests.
* r219950 as r221242 : [testsuite] Add vqdmull_n tests.
* r220117 as r221242 : [testsuite] Add vsubhn, vraddhn and vrsubhn tests.
* r220118 as r221242 : [testsuite] Add vmla_n and vmls_n tests.
* r220119 as r221242 : [testsuite] Add vpadd, vpmax and vpmin tests.
* r220121 as r221242 : [testsuite] Add vmovl tests.
* r220122 as r221242 : [testsuite] Add vmnv tests.
* r220123 as r221242 : [testsuite] Add vpadal tests.
* r220124 as r221242 : [testsuite] Add vpaddl tests.
* r220126 as r221242 : Fix incorrect ChangeLog formatting.
* r220353 as r221242 : [testsuite] Add vmax, vmin, vhadd, vhsub and
vrhadd tests.
* r220491 as r221216 : PR tree-optimization/64878
* r220751 as r221343 : [Haifa Scheduler] Fix latent bug in
macro-fusion/instruction grouping
* r220860 as r221215 : [AArch64] Fix wrong-code bug in right-shift SISD patterns

This will be part of our 2015.03 4.9 release.

Thanks
Yvan

[linaro/gcc-4_9-branch] Merge from gcc-4_9-branch and backports

[Yvan Roux]

Hi all

we have merged the gcc-4_9-branch into linaro/gcc-4_9-branch up to
revision 219502 as r219549.  We have also backported this set of revisions:

* r209620 as r219434 : [AArch64] Support SISD variants of SCVTF,UCVTF
* r209800 as r219597 : Add clobber_reg
* r211075 as r219465 : Add execution tests of ARM REV intrinsics.
* r211132 as r219435 : [AArch64] Fix ICE in aarch64_float_const_representable_p
* r211783 as r219596 : [AArch32] Post-indexed addressing for NEON memory access
* r211789 as r219517 : [AArch32] Improve 64 bit division performance (serie)
* r211790 as r219517 : [AArch32] Improve 64 bit division performance (serie)
* r211791 as r219517 : [AArch32] Improve 64 bit division performance (serie)
* r211792 as r219517 : [AArch32] Improve 64 bit division performance (serie)
* r211793 as r219517 : [AArch32] Improve 64 bit division performance (serie)
* r211794 as r219517 : [AArch32] Improve 64 bit division performance (serie)
* r211795 as r219517 : [AArch32] Improve 64 bit division performance (serie)
* r211796 as r219517 : [AArch32] Improve 64 bit division performance (serie)
* r211797 as r219517 : [AArch32] Improve 64 bit division performance (serie)
* r215503 as r219436 : [AArch64] Switch to sched-pressure by default.
* r216267 as r219518 : Add ACLE 2.0 predefined macros
* r216547 as r219518 : Add ACLE 2.0 predefined macro __ARM_FEATURE_IDIV
* r216548 as r219518 : fixes 216547
* r217072 as r219518 : Fix typo in definition of __ARM_FEATURE_IDIV
* r217073 as r219518 : Fix typo in definition of __ARM_FEATURE_IDIV
* r217192 as r219518 : Add ACLE arch-related predefined macros
* r217362 as r219433 : Fix up BSL expander for floating point types
* r217394 as r219522 : PR target/61997 - cc1plus ICE with aarch64
target using PCH and builtin functions
* r217405 as r219518 : Add reference to ACLE and consolidate documentation
* r217406 as r219518 : Remove unnecessary files
* r217546 as r219433 : PR target/63724
* r217593 as r219516 : Add scheduler for ThunderX
* r217661 as r219463 : Remove crypto extension from default for
cortex-a53, cortex-a57
* r217691 as r219437 : [LRA] Relax one gcc_assert in lra-eliminate for
fixed register
* r217717 as r219464 : doloop pattern for -fmodulo-sched
* r217768 as r219518 : more conditional macros defined in ACLE 2.0
* r218319 as r219438 : Revert 215321
* r218451 as r219584 : extend jump thread for finite state automata

This will be part of our 2015.01 4.9 release.

Thanks
Yvan

[linaro/gcc-4_9-branch] Merge from gcc-4_9-branch and backports

[Yvan Roux]

Hi all

we have merged the gcc-4_9-branch into linaro/gcc-4_9-branch up to
revision 218412 as r218423.  We have also backported this set of revisions:

* r213382 as r218352 : [AArch64] arm_neon.h - add vpaddd_f64,
vpaddd_s64, vpaddd_u64 intrinsics
* r214008 as r218354 : [AArch64] Move some code around in
aarch64_expand_mov_immediate
* r214948 as r218355 : [PATCH AArch64 1/2] Improve codegen of vector
compares inc. tst instruction
* r214949 as r218355 : [PATCH AArch64 2/2] Remove vector compare/tst __builtins
* r214950 as r218356 : [PATCH AArch64 1/2] Add execution tests of
vget_low and vget_high
* r214952 as r218356 : [PATCH AArch64 2/2] Replace temporary inline
assembler for vget_high
* r215013 as r218357 : Remove no-longer-needed fp-bit target macros.
* r215046 as r218358 : [AArch64] PR 61749: Do not ICE in lane
intrinsics when passed non-constant lane number
* r215047 as r218359 : [AArch32] Disable xordi3-opt.c/iordi3-opt.c on
thumb1 target
* r215071 as r218377 : [AArch64 Testsuite]Fix scan-assembler test
false alarm on aarch64-linux-gnu
* r215072 as r218360 : [AArch64 Testsuite] Add test of vld[234]q? intrinsic
* r215077 as r218361 : [AArch64 Testsuite] Extend test of vld1+vst1
intrinsics to cover more variants
* r215078 as r218362 : [AArch64 Testsuite] Add a test of vldN_dup intrinsics
* r215126 as r218363 : [AArch64 Testsuite] Add a test of the vldN_lane intrinsic
* r215129 as r218364 : [AArch64 Testsuite] Add a test of the
vst[234](q?) intrinics
* r215177 as r218365 : [AArch64 Testsuite] Add execution test of
vset(q?)_lane intrinsics.
* r215206 as r218351 : [AArch64] Add cost handling of CALLER_SAVE_REGS
and POINTER_REGS
* r215207 as r218351 : [AArch64] Fix cost for Q register moves
* r215208 as r218351 : [AArch64] Add regmove_costs for Cortex-A57 and A53
* r215473 as r218366 : [testsuite] whole_vector_shift
* r215475 as r218367 : [testsuite] vect-reduc-or
* r215540 as r218368 : PR rtl-optimization/63210 IRA
* r215707 as r218370 : Fix IRA ICE tmpdir-gcc-.dg-struct-layout-1/t028
* r215711 as r218371 : Accept cortex-m7/fpv5-sp-16/fpv5-d16
* r215842 as r218370 : Fix IRA ICE tmpdir-gcc-.dg-struct-layout-1/t028 -addon
* r215865 as r218373 : Add aarch64 to list of targets that support gold
* r216253 as r218374 : Remove unused variable and marco
* r216336 as r218375 : Target Legitimze Address
* r216444 as r218350 : [testsuite] Fix race in libstdc++ testsuite
* r216517 as r218378 : [testsuite] update testcases for GNU11
* r216524 as r218379 : Add -mthunderx option
* r216543 as r218380 : [testsuite] fix gcc-dg-prune glitch when
filtering "relocation truncation" error
* r216544 as r218384 : [testsuite] Update testcases for GNU11
* r216630 as r218385 : PR 63173 fix vldX_dup
* r216638 as r218386 : [testsuite] fix wrap_compile_flags
* r216765 as r218387 : PR63442 libgcc_cmp_return_mode not always
return word_mode
* r216996 as r218390 : [Patch 1/7] Hookize *_BY_PIECES_P
* r216998 as r218390 : [Patch 2/7 s390] Deprecate *_BY_PIECES_P, move
to hookized version
* r216999 as r218390 : [Patch 3/7 arc] Deprecate *_BY_PIECES_P, move
to hookized version
* r217001 as r218390 : [Patch 4/7 sh] Deprecate *_BY_PIECES_P, move to
hookized version
* r217002 as r218390 : [Patch 5/7 mips] Deprecate *_BY_PIECES_P, move
to hookized version
* r217003 as r218390 : [Patch 6/7 AArch64] Deprecate *_BY_PIECES_P,
move to hookized version
* r217004 as r218390 : [Patch 7/7] Remove *_BY_PIECES_P
* r217014 as r218391 : Fix CLZ_DEFINED_VALUE_AT_ZERO for vector modes
* r217026 as r218393 : ifcvt: Allow CC mode if HAVE_cbranchcc4
* r217076 as r218394 : Fix predicate and constraint mismatch in
logical atomic operations
* r217079 as r218398 : Migrate to new reduc_plus_scal_optab
* r217080 as r218398 : Migrate to new reduc_[us](min|max)_scal_optab
* r217742 as r218390 : PR target/63937 fix 216996
* r217971 as r218383 : [PATCH x86] Increase
PARAM_MAX_COMPLETELY_PEELED_INSNS when branch is costly
* r210735 as r218351 : Change CORE_REGS in GENERAL_REGS

This will be part of our 2014.12 4.9 release.

Thanks
Yvan

[linaro/gcc-4_9-branch] Merge from gcc-4_9-branch and backports

[Yvan Roux]

Hi all

we have merged the gcc-4_9-branch into linaro/gcc-4_9-branch up to
revision 216130 as r216256.  We have also backported this set of revisions:

r209643 as 215975 : [AArch64] Define TARGET_FLAGS_REGNUM
r211881 as 215975 : PR target/61565
r213035 as 215846 : [AArch64] libitm: Improve _ITM_beginTransaction
r213090 as 215847 : [AArch64] Fix *extr_insv_lower_reg<mode> pattern
r214824 as 215977 : [AArch64] Use CC_Z and CC_NZ with csinc and
similar instructions
r214825 as 216007 : [AArch32][1/2] Implement lceil, lfloor, lround
optabs with new ARMv8-A instructions
r214826 as 216007 : [AArch32][2/2] Vectorise lroundf, lfloorf, lceilf
using the new ARMv8-A vcvt* instructions
r214886 as 215944 : [AArch64] Improve epilogue unwind info rth
r214940 as 215853 : [AArch64] Add a mode to operand 1 of sibcall_value_insn
r214943 as 215946 : [AArch64] Add a builtin for rbit(q?)_p8; add
intrinsics and tests.
r214944 as 215948 : [AArch32/AArch64] Schedule alu_ext for Cortex-A53
r214945 as 215949 : [AArch64] Remove varargs from aarch64_simd_expand_args
r214947 as 215854 : [AArch64] Tidy: remove unused qualifier_const_pointer
r214959 as 215857 : [AArch32/AArch64] Add scheduling info for ARMv8-A
FPU new instructions in Cortex-A53
r215050 as 215858 : [AArch32[1/7] Convert FP mnemonics to UAL | mov patterns.
r215051 as 215858 : [AArch32][2/7] Convert FP mnemonics to UAL |
add/sub/div/abs patterns
r215052 as 215858 : [AARch32][3/7] Convert FP mnemonics to UAL |
mul+add patterns
r215053 as 215858 : [AArch32][4/7] Convert FP mnemonics to UAL | vcvt patterns
r215054 as 215858 : [AArch32][5/7] Convert FP mnemonics to UAL | sqrt
and FP compare patterns
r215055 as 215858 : [AArch32][6/7] Convert FP mnemonics to UAL |
movcc_vfp (fmstat)
r215056 as 215858 : [AArch32][7/7] Convert FP mnemonics to UAL |
f{ld,st}m -> v{ld,st}m
r215067 as 215923 : [AArch32] Enable auto-vectorization for copysignf
r215085 as 216007 : [AArch32][tests] Make input and output arrays
128-bit aligned in vectorisation tests
r215086 as 215928 : [AARch64] Add crtfastmath for AArch64
r215101 as 215929 : PR target/56846 libstdc++
r215136 as 215932 : PR target/63209
r215205 as 215935 : [Ree] Ensure inserted copy don't change the number
of hard registers
r215260 as 215937 : [AArch64] Fix force_simd macro in vdup_lane_2
r215321 as 215938 : Disallow -mfpu=neon for unsuitable architectures
r215346 as 215940 : movmisalign<mode>_neon_load
r215385 as 215941 : [AArch64] Add constraint letter for
stack_protect_test pattern
r215471 as 216004 : [AArch64] Auto-generate the "BUILTIN_" macros

This will be part of our 2014.10 4.9 release.

Thanks,
Yvan

[linaro/gcc-4_9-branch] Merge from gcc-4_9-branch and backports

[Yvan Roux]

Hi all

we have merged the gcc-4_9-branch into linaro/gcc-4_9-branch up to
revision 214896 as r215060.  We have also backported this set of revisions:

r211717 as r214313 : [AArch32] TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook
r212927 as r214314 : [AArch32] Enable arm target in
ira-shrinkwrap-prep* testcases
r212978 as r214739 : Testsuite: fix check_effective_target_arm_nothumb
r212989 as r214312 : PR 61876: Do not convert cast + __builtin_round
into __builtin_lround unless -fno-math-errno is used
r213304 as r214314 : [AArch64] Fix Thumb2 testsuite fallout
r213378 as r214502 : [AArch64_be] Fix vec_select hi/lo mask confusions.
r213379 as r214504 : [AArch64_be] Don't fold reduction intrinsics
r213485 as r214505 : [AArch64][1/2] Fix offset glitch in load reg pair pattern
r213486 as r214505 : fix ChangeLog for 213485
r213487 as r214505 : [AArch64][2/2] Add constrain to address offset in
storewb_pair/loadwb_pair insns
r213488 as r214506 : [AArch64] Improve TARGET_LEGITIMIZE_ADDRESS_P hook
r213489 as r214506 : add missing testcase for 213488
r213490 as r214507 : [AArch64] Removed unused get_lane and dup_lane builtins.
r213551 as r214509 : [sched-deps] Generalise usage of macro fusion to
work on any two insns
r213556 as r214509 : Fix wrong ChangeLog date from 213551
r213557 as r214511 : [doc] Document clrsb optab and fix some inconsistencies
r213627 as r214516 : [AArch64] Some aarch64-builtins.c cleanup.
r213628 as r214312 : [convert.c] PR 61876: Guard transformation to
lrint by -fno-math-errno
r213630 as r214512 : [AArch32] Adjust clz, rbit and rev patterns for
-mrestrict-it
r213632 as r214513 : [AArch32/AArch64] Add CRC32 scheduling
information to Cortex-A53 and Cortex-A57
r213651 as r214809 : [AArch64] Use REG_P and CONST_INT_P instead of
GET_CODE + comparison
r213659 as r214844 : [AArch64] Prefer dup to zip for vec_perm_const;
enable dup for bigendian; add testcase.
r213692 as r214313 : [AArch32] TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook
r213701 as r214517 : Testsuiteisms.
r213711 as r214514 : [AArch64] Use MOVN to generate 64-bit negative
immediates where sensible
r213713 as r214515 : [AArch64] Delete f_sels, f_seld types, use fcsel instead
r214503 as r214845 : [AArch64] Fix typo
r214526 as r214847 : PR target/60606 target/61330 fix ICE
r215004 as r215069 : [AArch64] PR target/63190

This will be part of our 2014.09 4.9 release.

Thanks,
Yvan

[linaro/gcc-4_9-branch] Merge from gcc-4_9-branch and backports

[Yvan Roux]

Hi all

we have merged the gcc-4_9-branch into linaro/gcc-4_9-branch up to
revision 213803 as r213943.  We have also backported this set of revisions:

r211140 as r213455      [AArch64] Drop ISB after FPCR write.
r211270 as r213790      [AArch64] Remove from arm_neon.h functions not
in the spec
r211271 as r213791      Fix check for __FAST_MATH in arm_neon.h
r211273 as r213792      [Patch,testsuite] Fix bind_pic_locally
r211275 as r213792      [Patch,testsuite] Fix tests that fail due to
symbol visibility when -fPIC
r211503 as r213793      [AArch64] fix and enable non-const shuffle for
bigendian using TBL instruction
r211779 as r213793      [AArch64][committed] Delete unused variable i
r212023 as r213794      [AArch64] Fix constraint vec_unpack_trunk
r212024 as r213795      [AArch32] Cortex-A5 rtx costs table
r212142 as r213796      [AArch32] Handle clz, rbit types in arm
pipeline descriptions
r212225 as r213797      [AArch64] Fix argument types for some
high_lane* intrinsics implemented in assembly
r212296 as r213798      [AArch64] Handle fcvta[su] and frint in RTX
cost function
r212358 as r213799      [AArch64] Relocate saved_varargs_size.
r212512 as r213799      [AArch64] Restructure callee save slot allocation logic.
r212752 as r213799      Unify slots x29/x30
r212753 as r213799      [AArch64] Add frame_size and hard_fp_offset to
machine.frame
r212912 as r213799      [AArch64] GNU-Stylize some un-formatted code.
r212913 as r213799      [AArch64] Consistent parameter types in
prologue/epilogue generation.
r212943 as r213799      [AArch64] Remove useless local variable.
r212945 as r213799      [AArch64] Remove useless parameter base_rtx.
r212946 as r213799      [AArch64] Use register offset in
cfun->machine->frame.reg_offset
r212947 as r213799      [AArch64] Remove useless variable 'increment'
r212949 as r213799      [AArch64] Hoist calculation of register rtx.
r212950 as r213799      [AArch64] Refactor code out into
aarch64_next_callee_save
r212951 as r213799      [AArch64] Use helper functions to handle multiple modes.
r212952 as r213799      [AArch64] Unify vector and core register
save/restore code.
r212954 as r213799      [AArch64] Split save restore path.
r212955 as r213799      [AArch64] Simplify prologue expand using new
helper functions.
r212956 as r213799      [AArch64] Simplify epilogue expansion using
new helper functions.
r212957 as r213799      [AArch64] Prologue and epilogue test cases.
r212958 as r213799      [AArch64] Optimize epilogue in the presence of
an outgoing args area.
r212959 as r213799      [AArch64] Extend frame state to track WB candidates.
r212976 as r213799      [AArch64] Infrastructure for optional use of writeback
r212996 as r213799      [AArch64] Optimize prologue when there is no
frame pointer.
r212997 as r213799      [AArch64] Optimize epilogue when there is no frame
r212999 as 213800       [PATCH, ARM] Fix PR61948 (ICE with DImode
shift by 1 bit)
r213000 as r213801      PR 61713: ICE when expanding single-threaded
version of atomic_test_and_set
r213376 as r213817      [AArch64][1/2] Remove UNSPEC_CLS and use clrsb
RTL code in its' place
r213555 as r213817      [AArch64][2/2] Add rtx cost function handling
of clz, clrsb, rbit

This will be part of our 2014.08 4.9 release.

Thanks,
Yvan

[linaro/gcc-4_9-branch] Merge from gcc-4_9-branch and backports

[Yvan Roux]

Hi all,

we have merged the gcc-4_9-branch into linaro/gcc-4_9-branch up to
revision 212419 as r212661.  We have also backported this set of revisions:

r209794 as r212697 : PR c/60114
r209797 as r212675 : [ARM] Wrap long literals in HOST_WIDE_INT_C in
aarch-common.c
r209858 as r212697 : [ARM/AArch64] Use signed chars in gcc.dg/pr60114.c.
r209940 as r212665 : Add execution + assembler tests of AArch64 UZP Intrinsics.
r209943 as r212665 : Rewrite AArch64 UZP Intrinsics using __builtin_shuffle.
r209947 as r212665 : Add execution tests of ARM UZP Intrinsics.
r210148 as r212698 : Add execution + assembler tests of AArch64 TRN Intrinsics.
r210151 as r212698 : Reimplement AArch64 TRN intrinsics with __builtin_shuffle.
r210152 as r212677 : Add execution + assembler tests of AArch64 EXT intrinsics.
r210153 as r212715 : Add execution + assembler tests of AArch64 REV
Neon Intrinsics.
r210216 as r212714 : Neon intrinsics TLC - Replace intrinsics with GNU
C implementations.
r210218 as r212714 : Neon intrinsics TLC - remove dead code.
r210219 as r212714 : Neon intrinsics TLC - remove ML
r210355 as r212669 : Implement HARD_REGNO_CALLER_SAVE_MODE for AArch64
r210369 as r212678 : [ARM] Remove vzip, vuzp, vtrn builtins and cleanup
r210422 as r212698 : Add execution tests of ARM TRN Intrinsics.
r210471 as r212679 : [ARM][cleanup] Use enum name instead of integer
value for PARAM_SCHED_PRESSURE_ALGORITHM.
r210828 as r212672 : TARGET_ATOMIC_ASSIGN_EXPAND_FENV AArch64
r210861 as r212695 : [AARCH64] Support tail indirect function call.
r210967 as r212680 : [ARM] Vectorise bswap* in aarch32.
r210996 as r212681 : [AArch64] Fix stack protector for ILP32
r211050 as r212682 : [AArch32] Fix PR/61331
r211058 as r212677 : Detect EXT patterns to vec_perm_const, use for
EXT intrinsics
r211059 as r212677 : Add execution tests of ARM EXT intrinsics
r211073 as r212683 : [ARM] Use mov_imm type for movw operations consistently
r211103 as r212672 : TARGET_ATOMIC_ASSIGN_EXPAND_FENV ARM
r211129 as r212685 : Fix PR target/61154
r211148 as r212673 : ILP32 dynamic linker
r211174 as r212715 : Recognize shuffle patterns for REV instructions
on AArch64, rewrite intrinsics.
r211177 as r212677 : Detect EXT patterns to vec_perm_const, use for
EXT intrinsics.
r211185 as r212690 : [PATCH AArch64 1/2] Correct signedness of
builtins, remove casts from arm_neon.h
r211186 as r212690 : AArch64 2/2] Correct signedness of builtins,
remove casts from arm_neon.h
r211268 as r212686 : [AArch64] clarify stack layout diagram
r211314 as r212691 : [AArch64] Implement movmem for the benefit of inline memcpy
r211371 as r212687 : Remove XFmode from ARM backend.
r211408 as r212689 : [AArch64] Fix REG_CFA_RESTORE mode.
r211416 as r212689 : [AArch64] Fix layout of frame layout code.
r211418 as r212688 : [AArch64] Fix some reg-to-reg move scheduler types.
r211440 as r212720 : [AArch64] Implement CRC32 ACLE intrinsics
r211441 as r212720 : [AArch64] Add CRC32 ACLE intrinsics testsuite.
r211771 as r212696 : [genattrtab] Fix memory corruption, allocate
enough memory for all bypassed reservations
r211887 as r212722 : [AArch64] Implement ADD in vector registers for
32-bit scalar values.
r211899 as r212722 : [AArch64] Implement ADD in vector registers for
32-bit scalar values.

This will be part of our 2014.07 release.

Thanks,
Yvan

[linaro/gcc-4_9-branch] Merge from gcc-4_9-branch and backports

[Yvan Roux]

Hi all,

we have merged the gcc-4_9-branch into linaro/gcc-4_9-branch up to
revision 211054 as r211495.  We have also backported this set of revisions:

r209419 as r211497 : PR rtl-optimization/60663
r209457 as r211496 : TRY_EMPTY_VM_SPACE Change aarch64 ilp32
r209559 as r211498 : [AArch64] vrnd<*>_f64 patch
r209561 as r211505 : Suppress Redundant Flag Setting for Cortex-A15.
r209613 as r211506 : AArch32 Support ORN for DIMode
r209614 as r211507 : Optimise NotDI AND/OR ZeroExtendSI for ARMv7A
r209615 as r211508 : [ARM] Allow any register for DImode values in Thumb2
r209617 as r211509 : [AArch64] Fix possible wrong code generation when
comparing DImode values.
r209618 as r211511 : [AArch64] Add a space to memory asm code between
base register and offset.
r209627 as r211512 : [AArch64] Fix indentation.
r209636 as r211512 : [AArch64] Fix aarch64_initial_elimination_offset
calculation.
r209640 as r211514 : [AArch64] vqneg and vqabs intrinsics implementation.
r209641 as r211515 : [AArch64] Vreinterpret re-implemention.
r209642 as r211515 : [AArch64] 64-bit float vreinterpret implemention
r209643 as r211516 : [AArch64] Define TARGET_FLAGS_REGNUM
r209645 as r211517 : [AArch64] Fix TLS for ILP32.
r209649 as r211518 : Merge longlong.h from glibc tree.
r209659 as r211519 : AArch64 add, sub, mul in TImode
r209701 as r211520 : [ARM] Handle FMA code in rtx costs.
r209702 as r211520 : [ARM] Cortex-A8 rtx cost table
r209703 as r211520 : [ARM][1/3] Add rev field to rtx cost tables
r209704 as r211520 : [AArch64][2/3] Recognise rev16 operations on
SImode and DImode data
r209705 as r211520 : [ARM][3/3] Recognise bitwise operations leading
to SImode rev16
r209706 as r211521 : [AArch64] Add handling of bswap operations in rtx costs
r209710 as r211523 : [ARM] Initialize new tune_params values
r209711 as r211524 : [AArch64] Fully support rotate on logical operations.
r209712 as r211530 : [AARCH64] Use standard patterns for stack protection.
r209713 as r211560 : [AArch64] VDUP Testcases
r209736 as r211573 : [AArch64] Vectorise bswap[16,32,64]
r209742 as r211574 : [AArch64] Reverse TBL indices for big-endian.
r209747 as r211575 : Fix warning in libgfortran configure script
r209749 as r211574 : [AArch64] Enable TBL for big-endian.
r209806 as r211576 : [ARM] Initialise T16-related fields in Cortex-A8
tuning struct.
r209808 as r211577 : [ARM] Enable tail call optimization for long call
r209878 as r211578 : [AArch64] Relax modes_tieable_p and
cannot_change_mode_class
r209880 as r211579 : [AArch64] Improve vst4_lane intrinsics
r209893 as r211580 : Add execution + assembler tests of the AArch64
ZIP Intrinsics.
r209897 as r211581 : Remove PUSH_ARGS_REVERSED from the RTL expander.
r209906 as r211582 : [AArch64/ARM 2/3] Rewrite AArch64 ZIP Intrinsics
using __builtin_shuffle
r209908 as r211582 : Add execution tests of ARM ZIP Intrinsics.
r210615 as r211583 : libitm: Enable aarch64
r211211 as r211584 : [AARCH64]Support full addressing modes for
ldr/str in vectorization scenarios

This will be part of our 2014.06 release.

Thanks,
Yvan

[linaro/gcc-4_9-branch] Merge from gcc-4_9-branch and backports

[Yvan Roux]

Hi,

we have merged the gcc-4_9-branch into linaro/gcc-4_9-branch up to
revision 210052 as r210370. We also have backported Ada AArch64
support as r210372 and 2 other upstream contributions as r210373 and
r210376.

This will be part of our 2014.05 release.

Thanks,
Yvan