From: abebeos <lazaridis.com+abebeos@gmail.com>
To: gcc-patches@gcc.gnu.org
Subject: [PATCH] avr: cc0 to mode_cc conversion
Date: Sat, 12 Dec 2020 06:49:47 +0200 [thread overview]
Message-ID: <CADWdT=yd90Ca7kdU2wT7b6wMBmLTr2vizGRMcrvP5PR4Km-MKg@mail.gmail.com> (raw)
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(I really tried to follow this https://gcc.gnu.org/contribute.html#patches,
but my stomach)
Hi there all!
The attached patch contains a new avr-backend, stripped from cc0.
The author is gcc maintainer Snethil Kumar Selvaraj (saaadhu), the source
can be found here:
https://github.com/saaadhu/gcc-avr-cc0/tree/avr-cc0-squashed
The gcc/g++ testsuites show zero regressions, tested with:
https://github.com/abebeos/avr-gnu
and confirmed with another testsetup, see:
https://gcc.gnu.org/pipermail/gcc-patches/2020-December/561489.html
Some more background information within:
https://gcc.gnu.org/pipermail/gcc-patches/2020-December/561668.html
and
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92729
(i have this dark feeling that I did the patch submission wrong... pressing
Send anyways!)
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diff --git a/gcc/config/avr/avr-dimode.md b/gcc/config/avr/avr-dimode.md
index adffd2bd055..6bb44416f10 100644
--- a/gcc/config/avr/avr-dimode.md
+++ b/gcc/config/avr/avr-dimode.md
@@ -95,39 +95,77 @@
;; "adddq3_insn" "addudq3_insn"
;; "addda3_insn" "adduda3_insn"
;; "addta3_insn" "adduta3_insn"
-(define_insn "add<mode>3_insn"
+(define_insn_and_split "add<mode>3_insn"
[(set (reg:ALL8 ACC_A)
(plus:ALL8 (reg:ALL8 ACC_A)
(reg:ALL8 ACC_B)))]
"avr_have_dimode"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:ALL8 ACC_A)
+ (plus:ALL8 (reg:ALL8 ACC_A)
+ (reg:ALL8 ACC_B)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*add<mode>3_insn"
+ [(set (reg:ALL8 ACC_A)
+ (plus:ALL8 (reg:ALL8 ACC_A)
+ (reg:ALL8 ACC_B)))
+ (clobber (reg:CC REG_CC))]
+ "avr_have_dimode && reload_completed"
"%~call __adddi3"
- [(set_attr "adjust_len" "call")
- (set_attr "cc" "clobber")])
+ [(set_attr "adjust_len" "call")])
-(define_insn "adddi3_const8_insn"
+(define_insn_and_split "adddi3_const8_insn"
[(set (reg:DI ACC_A)
(plus:DI (reg:DI ACC_A)
(sign_extend:DI (reg:QI REG_X))))]
"avr_have_dimode"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:DI ACC_A)
+ (plus:DI (reg:DI ACC_A)
+ (sign_extend:DI (reg:QI REG_X))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*adddi3_const8_insn"
+ [(set (reg:DI ACC_A)
+ (plus:DI (reg:DI ACC_A)
+ (sign_extend:DI (reg:QI REG_X))))
+ (clobber (reg:CC REG_CC))]
+ "avr_have_dimode && reload_completed"
"%~call __adddi3_s8"
- [(set_attr "adjust_len" "call")
- (set_attr "cc" "clobber")])
+ [(set_attr "adjust_len" "call")])
;; "adddi3_const_insn"
;; "adddq3_const_insn" "addudq3_const_insn"
;; "addda3_const_insn" "adduda3_const_insn"
;; "addta3_const_insn" "adduta3_const_insn"
-(define_insn "add<mode>3_const_insn"
+(define_insn_and_split "add<mode>3_const_insn"
[(set (reg:ALL8 ACC_A)
(plus:ALL8 (reg:ALL8 ACC_A)
(match_operand:ALL8 0 "const_operand" "n Ynn")))]
"avr_have_dimode
&& !s8_operand (operands[0], VOIDmode)"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:ALL8 ACC_A)
+ (plus:ALL8 (reg:ALL8 ACC_A)
+ (match_dup 0)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*add<mode>3_const_insn"
+ [(set (reg:ALL8 ACC_A)
+ (plus:ALL8 (reg:ALL8 ACC_A)
+ (match_operand:ALL8 0 "const_operand" "n Ynn")))
+ (clobber (reg:CC REG_CC))]
+ "avr_have_dimode
+ && !s8_operand (operands[0], VOIDmode)
+ && reload_completed"
{
return avr_out_plus (insn, operands);
}
- [(set_attr "adjust_len" "plus")
- (set_attr "cc" "clobber")])
+ [(set_attr "adjust_len" "plus")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -167,29 +205,53 @@
;; "subdq3_insn" "subudq3_insn"
;; "subda3_insn" "subuda3_insn"
;; "subta3_insn" "subuta3_insn"
-(define_insn "sub<mode>3_insn"
+(define_insn_and_split "sub<mode>3_insn"
[(set (reg:ALL8 ACC_A)
(minus:ALL8 (reg:ALL8 ACC_A)
(reg:ALL8 ACC_B)))]
"avr_have_dimode"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:ALL8 ACC_A)
+ (minus:ALL8 (reg:ALL8 ACC_A)
+ (reg:ALL8 ACC_B)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*sub<mode>3_insn"
+ [(set (reg:ALL8 ACC_A)
+ (minus:ALL8 (reg:ALL8 ACC_A)
+ (reg:ALL8 ACC_B)))
+ (clobber (reg:CC REG_CC))]
+ "avr_have_dimode && reload_completed"
"%~call __subdi3"
- [(set_attr "adjust_len" "call")
- (set_attr "cc" "set_czn")])
+ [(set_attr "adjust_len" "call")])
;; "subdi3_const_insn"
;; "subdq3_const_insn" "subudq3_const_insn"
;; "subda3_const_insn" "subuda3_const_insn"
;; "subta3_const_insn" "subuta3_const_insn"
-(define_insn "sub<mode>3_const_insn"
+(define_insn_and_split "sub<mode>3_const_insn"
[(set (reg:ALL8 ACC_A)
(minus:ALL8 (reg:ALL8 ACC_A)
(match_operand:ALL8 0 "const_operand" "n Ynn")))]
"avr_have_dimode"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:ALL8 ACC_A)
+ (minus:ALL8 (reg:ALL8 ACC_A)
+ (match_dup 0)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*sub<mode>3_const_insn"
+ [(set (reg:ALL8 ACC_A)
+ (minus:ALL8 (reg:ALL8 ACC_A)
+ (match_operand:ALL8 0 "const_operand" "n Ynn")))
+ (clobber (reg:CC REG_CC))]
+ "avr_have_dimode && reload_completed"
{
return avr_out_plus (insn, operands);
}
- [(set_attr "adjust_len" "plus")
- (set_attr "cc" "clobber")])
+ [(set_attr "adjust_len" "plus")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Signed Saturating Addition and Subtraction
@@ -220,25 +282,49 @@
DONE;
})
-(define_insn "<code_stdname><mode>3_insn"
+(define_insn_and_split "<code_stdname><mode>3_insn"
[(set (reg:ALL8S ACC_A)
(ss_addsub:ALL8S (reg:ALL8S ACC_A)
(reg:ALL8S ACC_B)))]
"avr_have_dimode"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:ALL8S ACC_A)
+ (ss_addsub:ALL8S (reg:ALL8S ACC_A)
+ (reg:ALL8S ACC_B)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*<code_stdname><mode>3_insn"
+ [(set (reg:ALL8S ACC_A)
+ (ss_addsub:ALL8S (reg:ALL8S ACC_A)
+ (reg:ALL8S ACC_B)))
+ (clobber (reg:CC REG_CC))]
+ "avr_have_dimode && reload_completed"
"%~call __<code_stdname><mode>3"
- [(set_attr "adjust_len" "call")
- (set_attr "cc" "clobber")])
+ [(set_attr "adjust_len" "call")])
-(define_insn "<code_stdname><mode>3_const_insn"
+(define_insn_and_split "<code_stdname><mode>3_const_insn"
[(set (reg:ALL8S ACC_A)
(ss_addsub:ALL8S (reg:ALL8S ACC_A)
(match_operand:ALL8S 0 "const_operand" "n Ynn")))]
"avr_have_dimode"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:ALL8S ACC_A)
+ (ss_addsub:ALL8S (reg:ALL8S ACC_A)
+ (match_dup 0)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*<code_stdname><mode>3_const_insn"
+ [(set (reg:ALL8S ACC_A)
+ (ss_addsub:ALL8S (reg:ALL8S ACC_A)
+ (match_operand:ALL8S 0 "const_operand" "n Ynn")))
+ (clobber (reg:CC REG_CC))]
+ "avr_have_dimode && reload_completed"
{
return avr_out_plus (insn, operands);
}
- [(set_attr "adjust_len" "plus")
- (set_attr "cc" "clobber")])
+ [(set_attr "adjust_len" "plus")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Unsigned Saturating Addition and Subtraction
@@ -269,25 +355,49 @@
DONE;
})
-(define_insn "<code_stdname><mode>3_insn"
+(define_insn_and_split "<code_stdname><mode>3_insn"
[(set (reg:ALL8U ACC_A)
(us_addsub:ALL8U (reg:ALL8U ACC_A)
(reg:ALL8U ACC_B)))]
"avr_have_dimode"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:ALL8U ACC_A)
+ (us_addsub:ALL8U (reg:ALL8U ACC_A)
+ (reg:ALL8U ACC_B)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*<code_stdname><mode>3_insn"
+ [(set (reg:ALL8U ACC_A)
+ (us_addsub:ALL8U (reg:ALL8U ACC_A)
+ (reg:ALL8U ACC_B)))
+ (clobber (reg:CC REG_CC))]
+ "avr_have_dimode && reload_completed"
"%~call __<code_stdname><mode>3"
- [(set_attr "adjust_len" "call")
- (set_attr "cc" "clobber")])
+ [(set_attr "adjust_len" "call")])
-(define_insn "<code_stdname><mode>3_const_insn"
+(define_insn_and_split "<code_stdname><mode>3_const_insn"
[(set (reg:ALL8U ACC_A)
(us_addsub:ALL8U (reg:ALL8U ACC_A)
(match_operand:ALL8U 0 "const_operand" "n Ynn")))]
"avr_have_dimode"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:ALL8U ACC_A)
+ (us_addsub:ALL8U (reg:ALL8U ACC_A)
+ (match_operand:ALL8U 0 "const_operand" "n Ynn")))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*<code_stdname><mode>3_const_insn"
+ [(set (reg:ALL8U ACC_A)
+ (us_addsub:ALL8U (reg:ALL8U ACC_A)
+ (match_operand:ALL8U 0 "const_operand" "n Ynn")))
+ (clobber (reg:CC REG_CC))]
+ "avr_have_dimode && reload_completed"
{
return avr_out_plus (insn, operands);
}
- [(set_attr "adjust_len" "plus")
- (set_attr "cc" "clobber")])
+ [(set_attr "adjust_len" "plus")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Negation
@@ -306,13 +416,23 @@
DONE;
})
-(define_insn "negdi2_insn"
+(define_insn_and_split "negdi2_insn"
[(set (reg:DI ACC_A)
(neg:DI (reg:DI ACC_A)))]
"avr_have_dimode"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:DI ACC_A)
+ (neg:DI (reg:DI ACC_A)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*negdi2_insn"
+ [(set (reg:DI ACC_A)
+ (neg:DI (reg:DI ACC_A)))
+ (clobber (reg:CC REG_CC))]
+ "avr_have_dimode && reload_completed"
"%~call __negdi2"
- [(set_attr "adjust_len" "call")
- (set_attr "cc" "clobber")])
+ [(set_attr "adjust_len" "call")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -322,7 +442,7 @@
(define_expand "conditional_jump"
[(set (pc)
(if_then_else
- (match_operator 0 "ordered_comparison_operator" [(cc0)
+ (match_operator 0 "ordered_comparison_operator" [(reg:CC REG_CC)
(const_int 0)])
(label_ref (match_operand 1 "" ""))
(pc)))]
@@ -333,13 +453,14 @@
;; "cbranchda4" "cbranchuda4"
;; "cbranchta4" "cbranchuta4"
(define_expand "cbranch<mode>4"
- [(parallel [(match_operand:ALL8 1 "register_operand" "")
- (match_operand:ALL8 2 "nonmemory_operand" "")
- (match_operator 0 "ordered_comparison_operator" [(cc0)
- (const_int 0)])
- (label_ref (match_operand 3 "" ""))])]
+ [(set (pc)
+ (if_then_else (match_operator 0 "ordered_comparison_operator"
+ [(match_operand:ALL8 1 "register_operand" "")
+ (match_operand:ALL8 2 "nonmemory_operand" "")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
"avr_have_dimode"
- {
+ {
rtx acc_a = gen_rtx_REG (<MODE>mode, ACC_A);
avr_fix_inputs (operands, 1 << 2, regmask (<MODE>mode, ACC_A));
@@ -348,19 +469,36 @@
if (s8_operand (operands[2], VOIDmode))
{
emit_move_insn (gen_rtx_REG (QImode, REG_X), operands[2]);
- emit_insn (gen_compare_const8_di2 ());
+ emit_jump_insn (gen_cbranch_const8_di2_split (operands[0], operands[3]));
}
else if (const_operand (operands[2], GET_MODE (operands[2])))
{
- emit_insn (gen_compare_const_<mode>2 (operands[2]));
+ emit_jump_insn (gen_cbranch_const_<mode>2_split (operands[0],
+ operands[2],
+ operands[3]));
}
else
{
emit_move_insn (gen_rtx_REG (<MODE>mode, ACC_B), operands[2]);
- emit_insn (gen_compare_<mode>2 ());
+ emit_jump_insn (gen_cbranch_<mode>2_split (operands[0], operands[3]));
}
+ DONE;
+ })
- emit_jump_insn (gen_conditional_jump (operands[0], operands[3]));
+(define_insn_and_split "cbranch_<mode>2_split"
+ [(set (pc)
+ (if_then_else (match_operator 0 "ordered_comparison_operator"
+ [(reg:ALL8 ACC_A)
+ (reg:ALL8 ACC_B)])
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
+ "avr_have_dimode"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+ {
+ emit_insn (gen_compare_<mode>2 ());
+ emit_jump_insn (gen_conditional_jump (operands[0], operands[1]));
DONE;
})
@@ -369,39 +507,74 @@
;; "compare_da2" "compare_uda2"
;; "compare_ta2" "compare_uta2"
(define_insn "compare_<mode>2"
- [(set (cc0)
- (compare (reg:ALL8 ACC_A)
+ [(set (reg:CC REG_CC)
+ (compare:CC (reg:ALL8 ACC_A)
(reg:ALL8 ACC_B)))]
- "avr_have_dimode"
+ "reload_completed && avr_have_dimode"
"%~call __cmpdi2"
- [(set_attr "adjust_len" "call")
- (set_attr "cc" "compare")])
+ [(set_attr "adjust_len" "call")])
+
+(define_insn_and_split "cbranch_const8_di2_split"
+ [(set (pc)
+ (if_then_else (match_operator 0 "ordered_comparison_operator"
+ [(reg:DI ACC_A)
+ (sign_extend:DI (reg:QI REG_X))])
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
+ "avr_have_dimode"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+ {
+ emit_insn (gen_compare_const8_di2 ());
+ emit_jump_insn (gen_conditional_jump (operands[0], operands[1]));
+ DONE;
+ })
(define_insn "compare_const8_di2"
- [(set (cc0)
- (compare (reg:DI ACC_A)
+ [(set (reg:CC REG_CC)
+ (compare:CC (reg:DI ACC_A)
(sign_extend:DI (reg:QI REG_X))))]
- "avr_have_dimode"
+ "reload_completed && avr_have_dimode"
"%~call __cmpdi2_s8"
- [(set_attr "adjust_len" "call")
- (set_attr "cc" "compare")])
+ [(set_attr "adjust_len" "call")])
+
+(define_insn_and_split "cbranch_const_<mode>2_split"
+ [(set (pc)
+ (if_then_else (match_operator 0 "ordered_comparison_operator"
+ [(reg:ALL8 ACC_A)
+ (match_operand:ALL8 1 "const_operand" "n Ynn")])
+ (label_ref (match_operand 2 "" ""))
+ (pc)))
+ (clobber (match_scratch:QI 3 "=&d"))]
+ "avr_have_dimode
+ && !s8_operand (operands[1], VOIDmode)"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+ {
+ emit_insn (gen_compare_const_<mode>2 (operands[1], operands[3]));
+ emit_jump_insn (gen_conditional_jump (operands[0], operands[2]));
+ DONE;
+ })
+
;; "compare_const_di2"
;; "compare_const_dq2" "compare_const_udq2"
;; "compare_const_da2" "compare_const_uda2"
;; "compare_const_ta2" "compare_const_uta2"
(define_insn "compare_const_<mode>2"
- [(set (cc0)
- (compare (reg:ALL8 ACC_A)
+ [(set (reg:CC REG_CC)
+ (compare:CC (reg:ALL8 ACC_A)
(match_operand:ALL8 0 "const_operand" "n Ynn")))
- (clobber (match_scratch:QI 1 "=&d"))]
- "avr_have_dimode
+ (clobber (match_operand:QI 1 "register_operand" "=&d"))]
+ "reload_completed
+ && avr_have_dimode
&& !s8_operand (operands[0], VOIDmode)"
{
return avr_out_compare64 (insn, operands, NULL);
}
- [(set_attr "adjust_len" "compare64")
- (set_attr "cc" "compare")])
+ [(set_attr "adjust_len" "compare64")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -444,14 +617,26 @@
;; "ashludq3_insn" "ashrudq3_insn" "lshrudq3_insn" "rotludq3_insn"
;; "ashluda3_insn" "ashruda3_insn" "lshruda3_insn" "rotluda3_insn"
;; "ashluta3_insn" "ashruta3_insn" "lshruta3_insn" "rotluta3_insn"
-(define_insn "<code_stdname><mode>3_insn"
+(define_insn_and_split "<code_stdname><mode>3_insn"
[(set (reg:ALL8 ACC_A)
(di_shifts:ALL8 (reg:ALL8 ACC_A)
(reg:QI 16)))]
"avr_have_dimode"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:ALL8 ACC_A)
+ (di_shifts:ALL8 (reg:ALL8 ACC_A)
+ (reg:QI 16)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*<code_stdname><mode>3_insn"
+ [(set (reg:ALL8 ACC_A)
+ (di_shifts:ALL8 (reg:ALL8 ACC_A)
+ (reg:QI 16)))
+ (clobber (reg:CC REG_CC))]
+ "avr_have_dimode && reload_completed"
"%~call __<code_stdname>di3"
- [(set_attr "adjust_len" "call")
- (set_attr "cc" "clobber")])
+ [(set_attr "adjust_len" "call")])
;; "umulsidi3"
;; "mulsidi3"
@@ -475,7 +660,8 @@
;; "umulsidi3_insn"
;; "mulsidi3_insn"
-(define_insn "<extend_u>mulsidi3_insn"
+
+(define_insn_and_split "<extend_u>mulsidi3_insn"
[(set (reg:DI ACC_A)
(mult:DI (any_extend:DI (reg:SI 18))
(any_extend:DI (reg:SI 22))))
@@ -483,6 +669,24 @@
(clobber (reg:HI REG_Z))]
"avr_have_dimode
&& AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:DI ACC_A)
+ (mult:DI (any_extend:DI (reg:SI 18))
+ (any_extend:DI (reg:SI 22))))
+ (clobber (reg:HI REG_X))
+ (clobber (reg:HI REG_Z))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*<extend_u>mulsidi3_insn"
+ [(set (reg:DI ACC_A)
+ (mult:DI (any_extend:DI (reg:SI 18))
+ (any_extend:DI (reg:SI 22))))
+ (clobber (reg:HI REG_X))
+ (clobber (reg:HI REG_Z))
+ (clobber (reg:CC REG_CC))]
+ "avr_have_dimode
+ && AVR_HAVE_MUL
+ && reload_completed"
"%~call __<extend_u>mulsidi3"
- [(set_attr "adjust_len" "call")
- (set_attr "cc" "clobber")])
+ [(set_attr "adjust_len" "call")])
diff --git a/gcc/config/avr/avr-fixed.md b/gcc/config/avr/avr-fixed.md
index 737fe970d3e..39cd7c4eea8 100644
--- a/gcc/config/avr/avr-fixed.md
+++ b/gcc/config/avr/avr-fixed.md
@@ -56,27 +56,53 @@
TA UTA
QI HI SI DI])
-(define_insn "fract<FIXED_B:mode><FIXED_A:mode>2"
+(define_insn_and_split "fract<FIXED_B:mode><FIXED_A:mode>2"
[(set (match_operand:FIXED_A 0 "register_operand" "=r")
(fract_convert:FIXED_A
(match_operand:FIXED_B 1 "register_operand" "r")))]
"<FIXED_B:MODE>mode != <FIXED_A:MODE>mode"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (fract_convert:FIXED_A
+ (match_dup 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*fract<FIXED_B:mode><FIXED_A:mode>2"
+ [(set (match_operand:FIXED_A 0 "register_operand" "=r")
+ (fract_convert:FIXED_A
+ (match_operand:FIXED_B 1 "register_operand" "r")))
+ (clobber (reg:CC REG_CC))]
+ "<FIXED_B:MODE>mode != <FIXED_A:MODE>mode
+ && reload_completed"
{
return avr_out_fract (insn, operands, true, NULL);
}
- [(set_attr "cc" "clobber")
- (set_attr "adjust_len" "sfract")])
+ [(set_attr "adjust_len" "sfract")])
-(define_insn "fractuns<FIXED_B:mode><FIXED_A:mode>2"
+(define_insn_and_split "fractuns<FIXED_B:mode><FIXED_A:mode>2"
[(set (match_operand:FIXED_A 0 "register_operand" "=r")
(unsigned_fract_convert:FIXED_A
(match_operand:FIXED_B 1 "register_operand" "r")))]
"<FIXED_B:MODE>mode != <FIXED_A:MODE>mode"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (unsigned_fract_convert:FIXED_A
+ (match_dup 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*fractuns<FIXED_B:mode><FIXED_A:mode>2"
+ [(set (match_operand:FIXED_A 0 "register_operand" "=r")
+ (unsigned_fract_convert:FIXED_A
+ (match_operand:FIXED_B 1 "register_operand" "r")))
+ (clobber (reg:CC REG_CC))]
+ "<FIXED_B:MODE>mode != <FIXED_A:MODE>mode
+ && reload_completed"
{
return avr_out_fract (insn, operands, false, NULL);
}
- [(set_attr "cc" "clobber")
- (set_attr "adjust_len" "ufract")])
+ [(set_attr "adjust_len" "ufract")])
;******************************************************************************
;** Saturated Addition and Subtraction
@@ -92,29 +118,53 @@
;; "ssaddqq3" "ssaddhq3" "ssaddha3" "ssaddsq3" "ssaddsa3"
;; "sssubqq3" "sssubhq3" "sssubha3" "sssubsq3" "sssubsa3"
-(define_insn "<code_stdname><mode>3"
+(define_insn_and_split "<code_stdname><mode>3"
[(set (match_operand:ALL124S 0 "register_operand" "=??d,d")
(ss_addsub:ALL124S (match_operand:ALL124S 1 "register_operand" "<abelian>0,0")
(match_operand:ALL124S 2 "nonmemory_operand" "r,Ynn")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (ss_addsub:ALL124S (match_dup 1)
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*<code_stdname><mode>3"
+ [(set (match_operand:ALL124S 0 "register_operand" "=??d,d")
+ (ss_addsub:ALL124S (match_operand:ALL124S 1 "register_operand" "<abelian>0,0")
+ (match_operand:ALL124S 2 "nonmemory_operand" "r,Ynn")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return avr_out_plus (insn, operands);
}
- [(set_attr "cc" "clobber")
- (set_attr "adjust_len" "plus")])
+ [(set_attr "adjust_len" "plus")])
;; "usadduqq3" "usadduhq3" "usadduha3" "usaddusq3" "usaddusa3"
;; "ussubuqq3" "ussubuhq3" "ussubuha3" "ussubusq3" "ussubusa3"
-(define_insn "<code_stdname><mode>3"
+(define_insn_and_split "<code_stdname><mode>3"
[(set (match_operand:ALL124U 0 "register_operand" "=??r,d")
(us_addsub:ALL124U (match_operand:ALL124U 1 "register_operand" "<abelian>0,0")
(match_operand:ALL124U 2 "nonmemory_operand" "r,Ynn")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (us_addsub:ALL124U (match_dup 1)
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*<code_stdname><mode>3"
+ [(set (match_operand:ALL124U 0 "register_operand" "=??r,d")
+ (us_addsub:ALL124U (match_operand:ALL124U 1 "register_operand" "<abelian>0,0")
+ (match_operand:ALL124U 2 "nonmemory_operand" "r,Ynn")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return avr_out_plus (insn, operands);
}
- [(set_attr "cc" "clobber")
- (set_attr "adjust_len" "plus")])
+ [(set_attr "adjust_len" "plus")])
;******************************************************************************
;** Saturated Negation and Absolute Value
@@ -134,21 +184,41 @@
DONE;
})
-(define_insn "ssnegqq2"
+(define_insn_and_split "ssnegqq2"
[(set (match_operand:QQ 0 "register_operand" "=r")
(ss_neg:QQ (match_operand:QQ 1 "register_operand" "0")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (ss_neg:QQ (match_dup 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*ssnegqq2"
+ [(set (match_operand:QQ 0 "register_operand" "=r")
+ (ss_neg:QQ (match_operand:QQ 1 "register_operand" "0")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"neg %0\;brvc 0f\;dec %0\;0:"
- [(set_attr "cc" "clobber")
- (set_attr "length" "3")])
+ [(set_attr "length" "3")])
-(define_insn "ssabsqq2"
+(define_insn_and_split "ssabsqq2"
[(set (match_operand:QQ 0 "register_operand" "=r")
(ss_abs:QQ (match_operand:QQ 1 "register_operand" "0")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (ss_abs:QQ (match_dup 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*ssabsqq2"
+ [(set (match_operand:QQ 0 "register_operand" "=r")
+ (ss_abs:QQ (match_operand:QQ 1 "register_operand" "0")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"sbrc %0,7\;neg %0\;sbrc %0,7\;dec %0"
- [(set_attr "cc" "clobber")
- (set_attr "length" "4")])
+ [(set_attr "length" "4")])
;; "ssneghq2" "ssnegha2" "ssnegsq2" "ssnegsa2"
;; "ssabshq2" "ssabsha2" "ssabssq2" "ssabssa2"
@@ -166,23 +236,43 @@
;; "*ssneghq2" "*ssnegha2"
;; "*ssabshq2" "*ssabsha2"
-(define_insn "*<code_stdname><mode>2"
+(define_insn_and_split "*<code_stdname><mode>2_split"
[(set (reg:ALL2S 24)
(ss_abs_neg:ALL2S (reg:ALL2S 24)))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:ALL2S 24)
+ (ss_abs_neg:ALL2S (reg:ALL2S 24)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*<code_stdname><mode>2"
+ [(set (reg:ALL2S 24)
+ (ss_abs_neg:ALL2S (reg:ALL2S 24)))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __<code_stdname>_2"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;; "*ssnegsq2" "*ssnegsa2"
;; "*ssabssq2" "*ssabssa2"
-(define_insn "*<code_stdname><mode>2"
+(define_insn_and_split "*<code_stdname><mode>2_split"
[(set (reg:ALL4S 22)
(ss_abs_neg:ALL4S (reg:ALL4S 22)))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:ALL4S 22)
+ (ss_abs_neg:ALL4S (reg:ALL4S 22)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*<code_stdname><mode>2"
+ [(set (reg:ALL4S 22)
+ (ss_abs_neg:ALL4S (reg:ALL4S 22)))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __<code_stdname>_4"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;******************************************************************************
; mul
@@ -200,23 +290,47 @@
DONE;
})
-(define_insn "mulqq3_enh"
+(define_insn_and_split "mulqq3_enh"
[(set (match_operand:QQ 0 "register_operand" "=r")
(mult:QQ (match_operand:QQ 1 "register_operand" "a")
(match_operand:QQ 2 "register_operand" "a")))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (mult:QQ (match_dup 1)
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*mulqq3_enh"
+ [(set (match_operand:QQ 0 "register_operand" "=r")
+ (mult:QQ (match_operand:QQ 1 "register_operand" "a")
+ (match_operand:QQ 2 "register_operand" "a")))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"fmuls %1,%2\;dec r1\;brvs 0f\;inc r1\;0:\;mov %0,r1\;clr __zero_reg__"
- [(set_attr "length" "6")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "6")])
-(define_insn "muluqq3_enh"
+(define_insn_and_split "muluqq3_enh"
[(set (match_operand:UQQ 0 "register_operand" "=r")
(mult:UQQ (match_operand:UQQ 1 "register_operand" "r")
(match_operand:UQQ 2 "register_operand" "r")))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (mult:UQQ (match_dup 1)
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*muluqq3_enh"
+ [(set (match_operand:UQQ 0 "register_operand" "=r")
+ (mult:UQQ (match_operand:UQQ 1 "register_operand" "r")
+ (match_operand:UQQ 2 "register_operand" "r")))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"mul %1,%2\;mov %0,r1\;clr __zero_reg__"
- [(set_attr "length" "3")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "3")])
(define_expand "mulqq3_nomul"
[(set (reg:QQ 24)
@@ -255,16 +369,32 @@
avr_fix_inputs (operands, 1 << 2, regmask (UQQmode, 22));
})
-(define_insn "*mulqq3.call"
+(define_insn_and_split "*mulqq3.call_split"
[(set (reg:QQ 23)
(mult:QQ (reg:QQ 24)
(reg:QQ 25)))
(clobber (reg:QI 22))
(clobber (reg:HI 24))]
"!AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:QQ 23)
+ (mult:QQ (reg:QQ 24)
+ (reg:QQ 25)))
+ (clobber (reg:QI 22))
+ (clobber (reg:HI 24))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*mulqq3.call"
+ [(set (reg:QQ 23)
+ (mult:QQ (reg:QQ 24)
+ (reg:QQ 25)))
+ (clobber (reg:QI 22))
+ (clobber (reg:HI 24))
+ (clobber (reg:CC REG_CC))]
+ "!AVR_HAVE_MUL && reload_completed"
"%~call __mulqq3"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;; "mulhq3" "muluhq3"
@@ -288,15 +418,29 @@
;; "*mulhq3.call" "*muluhq3.call"
;; "*mulha3.call" "*muluha3.call"
-(define_insn "*mul<mode>3.call"
+(define_insn_and_split "*mul<mode>3.call_split"
[(set (reg:ALL2QA 24)
(mult:ALL2QA (reg:ALL2QA 18)
(reg:ALL2QA 26)))
(clobber (reg:HI 22))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:ALL2QA 24)
+ (mult:ALL2QA (reg:ALL2QA 18)
+ (reg:ALL2QA 26)))
+ (clobber (reg:HI 22))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*mul<mode>3.call"
+ [(set (reg:ALL2QA 24)
+ (mult:ALL2QA (reg:ALL2QA 18)
+ (reg:ALL2QA 26)))
+ (clobber (reg:HI 22))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"%~call __mul<mode>3"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;; On the enhanced core, don't clobber either input and use a separate output
@@ -318,14 +462,26 @@
})
;; "*mulsa3.call" "*mulusa3.call"
-(define_insn "*mul<mode>3.call"
+(define_insn_and_split "*mul<mode>3.call_split"
[(set (reg:ALL4A 24)
(mult:ALL4A (reg:ALL4A 16)
(reg:ALL4A 20)))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:ALL4A 24)
+ (mult:ALL4A (reg:ALL4A 16)
+ (reg:ALL4A 20)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*mul<mode>3.call"
+ [(set (reg:ALL4A 24)
+ (mult:ALL4A (reg:ALL4A 16)
+ (reg:ALL4A 20)))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"%~call __mul<mode>3"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
; / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /
; div
@@ -351,15 +507,29 @@
;; "*divqq3.call" "*udivuqq3.call"
-(define_insn "*<code><mode>3.call"
+(define_insn_and_split "*<code><mode>3.call_split"
[(set (reg:ALL1Q 24)
(usdiv:ALL1Q (reg:ALL1Q 25)
(reg:ALL1Q 22)))
(clobber (reg:QI 25))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:ALL1Q 24)
+ (usdiv:ALL1Q (reg:ALL1Q 25)
+ (reg:ALL1Q 22)))
+ (clobber (reg:QI 25))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*<code><mode>3.call"
+ [(set (reg:ALL1Q 24)
+ (usdiv:ALL1Q (reg:ALL1Q 25)
+ (reg:ALL1Q 22)))
+ (clobber (reg:QI 25))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __<code><mode>3"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;; "divhq3" "udivuhq3"
;; "divha3" "udivuha3"
@@ -382,16 +552,32 @@
;; "*divhq3.call" "*udivuhq3.call"
;; "*divha3.call" "*udivuha3.call"
-(define_insn "*<code><mode>3.call"
+(define_insn_and_split "*<code><mode>3.call_split"
[(set (reg:ALL2QA 24)
(usdiv:ALL2QA (reg:ALL2QA 26)
(reg:ALL2QA 22)))
(clobber (reg:HI 26))
(clobber (reg:QI 21))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:ALL2QA 24)
+ (usdiv:ALL2QA (reg:ALL2QA 26)
+ (reg:ALL2QA 22)))
+ (clobber (reg:HI 26))
+ (clobber (reg:QI 21))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*<code><mode>3.call"
+ [(set (reg:ALL2QA 24)
+ (usdiv:ALL2QA (reg:ALL2QA 26)
+ (reg:ALL2QA 22)))
+ (clobber (reg:HI 26))
+ (clobber (reg:QI 21))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __<code><mode>3"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;; Note the first parameter gets passed in already offset by 2 bytes
@@ -414,16 +600,32 @@
})
;; "*divsa3.call" "*udivusa3.call"
-(define_insn "*<code><mode>3.call"
+(define_insn_and_split "*<code><mode>3.call_split"
[(set (reg:ALL4A 22)
(usdiv:ALL4A (reg:ALL4A 24)
(reg:ALL4A 18)))
(clobber (reg:HI 26))
(clobber (reg:HI 30))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:ALL4A 22)
+ (usdiv:ALL4A (reg:ALL4A 24)
+ (reg:ALL4A 18)))
+ (clobber (reg:HI 26))
+ (clobber (reg:HI 30))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*<code><mode>3.call"
+ [(set (reg:ALL4A 22)
+ (usdiv:ALL4A (reg:ALL4A 24)
+ (reg:ALL4A 18)))
+ (clobber (reg:HI 26))
+ (clobber (reg:HI 30))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __<code><mode>3"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;******************************************************************************
@@ -474,51 +676,109 @@
;; "roundqq3_const" "rounduqq3_const"
;; "roundhq3_const" "rounduhq3_const" "roundha3_const" "rounduha3_const"
;; "roundsq3_const" "roundusq3_const" "roundsa3_const" "roundusa3_const"
-(define_insn "round<mode>3_const"
+(define_insn_and_split "round<mode>3_const"
[(set (match_operand:ALL124QA 0 "register_operand" "=d")
(unspec:ALL124QA [(match_operand:ALL124QA 1 "register_operand" "0")
(match_operand:HI 2 "const_int_operand" "n")
(const_int 0)]
UNSPEC_ROUND))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (unspec:ALL124QA [(match_dup 1)
+ (match_dup 2)
+ (const_int 0)]
+ UNSPEC_ROUND))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*round<mode>3_const"
+ [(set (match_operand:ALL124QA 0 "register_operand" "=d")
+ (unspec:ALL124QA [(match_operand:ALL124QA 1 "register_operand" "0")
+ (match_operand:HI 2 "const_int_operand" "n")
+ (const_int 0)]
+ UNSPEC_ROUND))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return avr_out_round (insn, operands);
}
- [(set_attr "cc" "clobber")
- (set_attr "adjust_len" "round")])
+ [(set_attr "adjust_len" "round")])
;; "*roundqq3.libgcc" "*rounduqq3.libgcc"
-(define_insn "*round<mode>3.libgcc"
+(define_insn_and_split "*round<mode>3.libgcc_split"
[(set (reg:ALL1Q 24)
(unspec:ALL1Q [(reg:ALL1Q 22)
(reg:QI 24)] UNSPEC_ROUND))
(clobber (reg:ALL1Q 22))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:ALL1Q 24)
+ (unspec:ALL1Q [(reg:ALL1Q 22)
+ (reg:QI 24)] UNSPEC_ROUND))
+ (clobber (reg:ALL1Q 22))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*round<mode>3.libgcc"
+ [(set (reg:ALL1Q 24)
+ (unspec:ALL1Q [(reg:ALL1Q 22)
+ (reg:QI 24)] UNSPEC_ROUND))
+ (clobber (reg:ALL1Q 22))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __round<mode>3"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;; "*roundhq3.libgcc" "*rounduhq3.libgcc"
;; "*roundha3.libgcc" "*rounduha3.libgcc"
-(define_insn "*round<mode>3.libgcc"
+(define_insn_and_split "*round<mode>3.libgcc_split"
[(set (reg:ALL2QA 24)
(unspec:ALL2QA [(reg:ALL2QA 22)
(reg:QI 24)] UNSPEC_ROUND))
(clobber (reg:ALL2QA 22))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:ALL2QA 24)
+ (unspec:ALL2QA [(reg:ALL2QA 22)
+ (reg:QI 24)] UNSPEC_ROUND))
+ (clobber (reg:ALL2QA 22))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*round<mode>3.libgcc"
+ [(set (reg:ALL2QA 24)
+ (unspec:ALL2QA [(reg:ALL2QA 22)
+ (reg:QI 24)] UNSPEC_ROUND))
+ (clobber (reg:ALL2QA 22))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __round<mode>3"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;; "*roundsq3.libgcc" "*roundusq3.libgcc"
;; "*roundsa3.libgcc" "*roundusa3.libgcc"
-(define_insn "*round<mode>3.libgcc"
+(define_insn_and_split "*round<mode>3.libgcc_split"
[(set (reg:ALL4QA 22)
(unspec:ALL4QA [(reg:ALL4QA 18)
(reg:QI 24)] UNSPEC_ROUND))
(clobber (reg:ALL4QA 18))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:ALL4QA 22)
+ (unspec:ALL4QA [(reg:ALL4QA 18)
+ (reg:QI 24)] UNSPEC_ROUND))
+ (clobber (reg:ALL4QA 18))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*round<mode>3.libgcc"
+ [(set (reg:ALL4QA 22)
+ (unspec:ALL4QA [(reg:ALL4QA 18)
+ (reg:QI 24)] UNSPEC_ROUND))
+ (clobber (reg:ALL4QA 18))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __round<mode>3"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
diff --git a/gcc/config/avr/avr-protos.h b/gcc/config/avr/avr-protos.h
index 16c894ce3c3..1474b74227e 100644
--- a/gcc/config/avr/avr-protos.h
+++ b/gcc/config/avr/avr-protos.h
@@ -59,21 +59,21 @@ extern const char *avr_out_movpsi (rtx_insn *, rtx*, int*);
extern const char *avr_out_sign_extend (rtx_insn *, rtx*, int*);
extern const char *avr_out_insert_notbit (rtx_insn *, rtx*, rtx, int*);
-extern const char *ashlqi3_out (rtx_insn *insn, rtx operands[], int *len);
-extern const char *ashlhi3_out (rtx_insn *insn, rtx operands[], int *len);
-extern const char *ashlsi3_out (rtx_insn *insn, rtx operands[], int *len);
+extern const char *ashlqi3_out (rtx_insn *insn, rtx operands[], int numops, int *len);
+extern const char *ashlhi3_out (rtx_insn *insn, rtx operands[], int numops, int *len);
+extern const char *ashlsi3_out (rtx_insn *insn, rtx operands[], int numops, int *len);
-extern const char *ashrqi3_out (rtx_insn *insn, rtx operands[], int *len);
-extern const char *ashrhi3_out (rtx_insn *insn, rtx operands[], int *len);
-extern const char *ashrsi3_out (rtx_insn *insn, rtx operands[], int *len);
+extern const char *ashrqi3_out (rtx_insn *insn, rtx operands[], int numops, int *len);
+extern const char *ashrhi3_out (rtx_insn *insn, rtx operands[], int numops, int *len);
+extern const char *ashrsi3_out (rtx_insn *insn, rtx operands[], int numops, int *len);
-extern const char *lshrqi3_out (rtx_insn *insn, rtx operands[], int *len);
-extern const char *lshrhi3_out (rtx_insn *insn, rtx operands[], int *len);
-extern const char *lshrsi3_out (rtx_insn *insn, rtx operands[], int *len);
+extern const char *lshrqi3_out (rtx_insn *insn, rtx operands[], int numops, int *len);
+extern const char *lshrhi3_out (rtx_insn *insn, rtx operands[], int numops, int *len);
+extern const char *lshrsi3_out (rtx_insn *insn, rtx operands[], int numops, int *len);
-extern const char *avr_out_ashlpsi3 (rtx_insn *, rtx*, int*);
-extern const char *avr_out_ashrpsi3 (rtx_insn *, rtx*, int*);
-extern const char *avr_out_lshrpsi3 (rtx_insn *, rtx*, int*);
+extern const char *avr_out_ashlpsi3 (rtx_insn *, rtx*, int, int*);
+extern const char *avr_out_ashrpsi3 (rtx_insn *, rtx*, int, int*);
+extern const char *avr_out_lshrpsi3 (rtx_insn *, rtx*, int, int*);
extern bool avr_rotate_bytes (rtx operands[]);
@@ -116,7 +116,7 @@ extern int avr_simplify_comparison_p (machine_mode mode,
RTX_CODE op, rtx x);
extern RTX_CODE avr_normalize_condition (RTX_CODE condition);
extern void out_shift_with_cnt (const char *templ, rtx_insn *insn,
- rtx operands[], int *len, int t_len);
+ rtx operands[], int numops, int *len, int t_len);
extern enum reg_class avr_mode_code_base_reg_class (machine_mode, addr_space_t, RTX_CODE, RTX_CODE);
extern bool avr_regno_mode_code_ok_for_base_p (int, machine_mode, addr_space_t, RTX_CODE, RTX_CODE);
extern rtx avr_incoming_return_addr_rtx (void);
diff --git a/gcc/config/avr/avr.c b/gcc/config/avr/avr.c
index 61168edfdae..2322fbdf69b 100644
--- a/gcc/config/avr/avr.c
+++ b/gcc/config/avr/avr.c
@@ -195,6 +195,10 @@ rtx tmp_reg_rtx;
extern GTY(()) rtx zero_reg_rtx;
rtx zero_reg_rtx;
+/* Condition Codoe register RTX (reg:CC REG_CC) */
+extern GTY(()) rtx cc_reg_rtx;
+rtx cc_reg_rtx;
+
/* RTXs for all general purpose registers as QImode */
extern GTY(()) rtx all_regs_rtx[32];
rtx all_regs_rtx[32];
@@ -376,10 +380,10 @@ make_avr_pass_casesi (gcc::context *ctxt)
/* Make one parallel insn with all the patterns from insns i[0]..i[5]. */
static rtx_insn*
-avr_parallel_insn_from_insns (rtx_insn *i[6])
+avr_parallel_insn_from_insns (rtx_insn *i[5])
{
- rtvec vec = gen_rtvec (6, PATTERN (i[0]), PATTERN (i[1]), PATTERN (i[2]),
- PATTERN (i[3]), PATTERN (i[4]), PATTERN (i[5]));
+ rtvec vec = gen_rtvec (5, PATTERN (i[0]), PATTERN (i[1]), PATTERN (i[2]),
+ PATTERN (i[3]), PATTERN (i[4]));
start_sequence();
emit (gen_rtx_PARALLEL (VOIDmode, vec));
rtx_insn *insn = get_insns();
@@ -397,22 +401,21 @@ avr_parallel_insn_from_insns (rtx_insn *i[6])
pattern casesi_<mode>_sequence forged from the sequence to recog_data. */
static bool
-avr_is_casesi_sequence (basic_block bb, rtx_insn *insn, rtx_insn *insns[6])
+avr_is_casesi_sequence (basic_block bb, rtx_insn *insn, rtx_insn *insns[5])
{
- rtx set_5, set_0;
+ rtx set_4, set_0;
/* A first and quick test for a casesi sequences. As a side effect of
- the test, harvest respective insns to INSNS[0..5]. */
+ the test, harvest respective insns to INSNS[0..4]. */
- if (!(JUMP_P (insns[5] = insn)
+ if (!(JUMP_P (insns[4] = insn)
// casesi is the only insn that comes up with UNSPEC_INDEX_JMP,
// hence the following test ensures that we are actually dealing
// with code from casesi.
- && (set_5 = single_set (insns[5]))
- && UNSPEC == GET_CODE (SET_SRC (set_5))
- && UNSPEC_INDEX_JMP == XINT (SET_SRC (set_5), 1)
+ && (set_4 = single_set (insns[4]))
+ && UNSPEC == GET_CODE (SET_SRC (set_4))
+ && UNSPEC_INDEX_JMP == XINT (SET_SRC (set_4), 1)
- && (insns[4] = prev_real_insn (insns[5]))
&& (insns[3] = prev_real_insn (insns[4]))
&& (insns[2] = prev_real_insn (insns[3]))
&& (insns[1] = prev_real_insn (insns[2]))
@@ -429,7 +432,7 @@ avr_is_casesi_sequence (basic_block bb, rtx_insn *insn, rtx_insn *insns[6])
{
fprintf (dump_file, ";; Sequence from casesi in "
"[bb %d]:\n\n", bb->index);
- for (int i = 0; i < 6; i++)
+ for (int i = 0; i < 5; i++)
print_rtl_single (dump_file, insns[i]);
}
@@ -519,7 +522,7 @@ avr_casei_sequence_check_operands (rtx *xop)
}
-/* INSNS[1..5] is a sequence as generated by casesi and INSNS[0] is an
+/* INSNS[1..4] is a sequence as generated by casesi and INSNS[0] is an
extension of an 8-bit or 16-bit integer to SImode. XOP contains the
operands of INSNS as extracted by insn_extract from pattern
casesi_<mode>_sequence:
@@ -541,7 +544,7 @@ avr_casei_sequence_check_operands (rtx *xop)
switch value instead of SImode. */
static void
-avr_optimize_casesi (rtx_insn *insns[6], rtx *xop)
+avr_optimize_casesi (rtx_insn *insns[5], rtx *xop)
{
// Original mode of the switch value; this is QImode or HImode.
machine_mode mode = GET_MODE (xop[10]);
@@ -597,16 +600,22 @@ avr_optimize_casesi (rtx_insn *insns[6], rtx *xop)
rtx reg = copy_to_mode_reg (mode, xop[10]);
rtx (*gen_add)(rtx,rtx,rtx) = QImode == mode ? gen_addqi3 : gen_addhi3;
- rtx (*gen_cmp)(rtx,rtx) = QImode == mode ? gen_cmpqi3 : gen_cmphi3;
+ //rtx (*gen_cmp)(rtx,rtx) = QImode == mode ? gen_cmpqi3 : gen_cmphi3;
+ rtx (*gen_cbranch)(rtx,rtx,rtx,rtx)
+ = QImode == mode ? gen_cbranchqi4 : gen_cbranchhi4;
emit_insn (gen_add (reg, reg, gen_int_mode (-low_idx, mode)));
- emit_insn (gen_cmp (reg, gen_int_mode (num_idx, mode)));
+ rtx op0 = reg; rtx op1 = gen_int_mode (num_idx, mode);
+ rtx labelref = copy_rtx (xop[4]);
+ emit_jump_insn (gen_cbranch (gen_rtx_fmt_ee (GTU, VOIDmode, op0, op1),
+ op0, op1,
+ labelref));
seq1 = get_insns();
last1 = get_last_insn();
end_sequence();
- emit_insn_before (seq1, insns[1]);
+ emit_insn_after (seq1, insns[2]);
// After the out-of-bounds test and corresponding branch, use a
// 16-bit index. If QImode is used, extend it to HImode first.
@@ -627,7 +636,7 @@ avr_optimize_casesi (rtx_insn *insns[6], rtx *xop)
last2 = get_last_insn();
end_sequence();
- emit_insn_after (seq2, insns[4]);
+ emit_insn_after (seq2, insns[3]);
if (dump_file)
{
@@ -648,7 +657,7 @@ avr_optimize_casesi (rtx_insn *insns[6], rtx *xop)
}
fprintf (dump_file, ";; Deleting insns: %d, %d, %d.\n\n",
- INSN_UID (insns[1]), INSN_UID (insns[2]), INSN_UID (insns[4]));
+ INSN_UID (insns[1]), INSN_UID (insns[2]), INSN_UID (insns[3]));
}
// Pseudodelete the SImode and subreg of SImode insns. We don't care
@@ -657,7 +666,7 @@ avr_optimize_casesi (rtx_insn *insns[6], rtx *xop)
SET_INSN_DELETED (insns[1]);
SET_INSN_DELETED (insns[2]);
- SET_INSN_DELETED (insns[4]);
+ SET_INSN_DELETED (insns[3]);
}
@@ -668,7 +677,7 @@ avr_pass_casesi::avr_rest_of_handle_casesi (function *func)
FOR_EACH_BB_FN (bb, func)
{
- rtx_insn *insn, *insns[6];
+ rtx_insn *insn, *insns[5];
FOR_BB_INSNS (bb, insn)
{
@@ -814,6 +823,8 @@ avr_init_expanders (void)
tmp_reg_rtx = all_regs_rtx[AVR_TMP_REGNO];
zero_reg_rtx = all_regs_rtx[AVR_ZERO_REGNO];
+ cc_reg_rtx = gen_rtx_REG (CCmode, REG_CC);
+
lpm_addr_reg_rtx = gen_rtx_REG (HImode, REG_Z);
sreg_rtx = gen_rtx_MEM (QImode, GEN_INT (avr_addr.sreg));
@@ -2989,152 +3000,6 @@ avr_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size,
return size <= MOVE_MAX_PIECES;
}
-
-/* Worker function for `NOTICE_UPDATE_CC'. */
-/* Update the condition code in the INSN. */
-
-void
-avr_notice_update_cc (rtx body ATTRIBUTE_UNUSED, rtx_insn *insn)
-{
- rtx set;
- enum attr_cc cc = get_attr_cc (insn);
-
- switch (cc)
- {
- default:
- break;
-
- case CC_PLUS:
- case CC_LDI:
- {
- rtx *op = recog_data.operand;
- int len_dummy, icc;
-
- /* Extract insn's operands. */
- extract_constrain_insn_cached (insn);
-
- switch (cc)
- {
- default:
- gcc_unreachable();
-
- case CC_PLUS:
- avr_out_plus (insn, op, &len_dummy, &icc);
- cc = (enum attr_cc) icc;
- break;
-
- case CC_LDI:
-
- cc = (op[1] == CONST0_RTX (GET_MODE (op[0]))
- && reg_overlap_mentioned_p (op[0], zero_reg_rtx))
- /* Loading zero-reg with 0 uses CLR and thus clobbers cc0. */
- ? CC_CLOBBER
- /* Any other "r,rL" combination does not alter cc0. */
- : CC_NONE;
-
- break;
- } /* inner switch */
-
- break;
- }
- } /* outer swicth */
-
- switch (cc)
- {
- default:
- /* Special values like CC_OUT_PLUS from above have been
- mapped to "standard" CC_* values so we never come here. */
-
- gcc_unreachable();
- break;
-
- case CC_NONE:
- /* Insn does not affect CC at all, but it might set some registers
- that are stored in cc_status. If such a register is affected by
- the current insn, for example by means of a SET or a CLOBBER,
- then we must reset cc_status; cf. PR77326.
-
- Unfortunately, set_of cannot be used as reg_overlap_mentioned_p
- will abort on COMPARE (which might be found in cc_status.value1/2).
- Thus work out the registers set by the insn and regs mentioned
- in cc_status.value1/2. */
-
- if (cc_status.value1
- || cc_status.value2)
- {
- HARD_REG_SET regs_used;
- HARD_REG_SET regs_set;
- CLEAR_HARD_REG_SET (regs_used);
-
- if (cc_status.value1
- && !CONSTANT_P (cc_status.value1))
- {
- find_all_hard_regs (cc_status.value1, ®s_used);
- }
-
- if (cc_status.value2
- && !CONSTANT_P (cc_status.value2))
- {
- find_all_hard_regs (cc_status.value2, ®s_used);
- }
-
- find_all_hard_reg_sets (insn, ®s_set, false);
-
- if (hard_reg_set_intersect_p (regs_used, regs_set))
- {
- CC_STATUS_INIT;
- }
- }
-
- break; // CC_NONE
-
- case CC_SET_N:
- CC_STATUS_INIT;
- break;
-
- case CC_SET_ZN:
- set = single_set (insn);
- CC_STATUS_INIT;
- if (set)
- {
- cc_status.flags |= CC_NO_OVERFLOW;
- cc_status.value1 = SET_DEST (set);
- }
- break;
-
- case CC_SET_VZN:
- /* Insn like INC, DEC, NEG that set Z,N,V. We currently don't make use
- of this combination, cf. also PR61055. */
- CC_STATUS_INIT;
- break;
-
- case CC_SET_CZN:
- /* Insn sets the Z,N,C flags of CC to recog_operand[0].
- The V flag may or may not be known but that's ok because
- alter_cond will change tests to use EQ/NE. */
- set = single_set (insn);
- CC_STATUS_INIT;
- if (set)
- {
- cc_status.value1 = SET_DEST (set);
- cc_status.flags |= CC_OVERFLOW_UNUSABLE;
- }
- break;
-
- case CC_COMPARE:
- set = single_set (insn);
- CC_STATUS_INIT;
- if (set)
- cc_status.value1 = SET_SRC (set);
- break;
-
- case CC_CLOBBER:
- /* Insn doesn't leave CC in a usable state. */
- CC_STATUS_INIT;
- break;
- }
-}
-
/* Choose mode for jump insn:
1 - relative jump in range -63 <= x <= 62 ;
2 - relative jump in range -2046 <= x <= 2045 ;
@@ -5820,6 +5685,8 @@ compare_condition (rtx_insn *insn)
if (next && JUMP_P (next))
{
rtx pat = PATTERN (next);
+ if (GET_CODE(pat) == PARALLEL)
+ pat = XEXP (pat, 0);
rtx src = SET_SRC (pat);
if (IF_THEN_ELSE == GET_CODE (src))
@@ -6157,12 +6024,13 @@ avr_out_tstsi (rtx_insn *insn, rtx *op, int *plen)
OPERANDS[3] is a QImode scratch register from LD regs if
available and SCRATCH, otherwise (no scratch available)
+ NUMOPS is the number of operands
TEMPL is an assembler template that shifts by one position.
T_LEN is the length of this template. */
void
out_shift_with_cnt (const char *templ, rtx_insn *insn, rtx operands[],
- int *plen, int t_len)
+ int numops, int *plen, int t_len)
{
bool second_label = true;
bool saved_in_tmp = false;
@@ -6180,6 +6048,7 @@ out_shift_with_cnt (const char *templ, rtx_insn *insn, rtx operands[],
if (CONST_INT_P (operands[2]))
{
bool scratch = (GET_CODE (PATTERN (insn)) == PARALLEL
+ && numops == 4
&& REG_P (operands[3]));
int count = INTVAL (operands[2]);
int max_len = 10; /* If larger than this, always use a loop. */
@@ -6275,7 +6144,7 @@ out_shift_with_cnt (const char *templ, rtx_insn *insn, rtx operands[],
/* 8bit shift left ((char)x << i) */
const char *
-ashlqi3_out (rtx_insn *insn, rtx operands[], int *len)
+ashlqi3_out (rtx_insn *insn, rtx operands[], int numops, int *len)
{
if (CONST_INT_P (operands[2]))
{
@@ -6364,7 +6233,7 @@ ashlqi3_out (rtx_insn *insn, rtx operands[], int *len)
fatal_insn ("internal compiler error. Incorrect shift:", insn);
out_shift_with_cnt ("lsl %0",
- insn, operands, len, 1);
+ insn, operands, numops, len, 1);
return "";
}
@@ -6372,11 +6241,12 @@ ashlqi3_out (rtx_insn *insn, rtx operands[], int *len)
/* 16bit shift left ((short)x << i) */
const char *
-ashlhi3_out (rtx_insn *insn, rtx operands[], int *len)
+ashlhi3_out (rtx_insn *insn, rtx operands[], int numops, int *len)
{
if (CONST_INT_P (operands[2]))
{
- int scratch = (GET_CODE (PATTERN (insn)) == PARALLEL);
+ int scratch = (GET_CODE (PATTERN (insn)) == PARALLEL
+ && numops == 4);
int ldi_ok = test_hard_reg_class (LD_REGS, operands[0]);
int k;
int *t = len;
@@ -6621,7 +6491,7 @@ ashlhi3_out (rtx_insn *insn, rtx operands[], int *len)
len = t;
}
out_shift_with_cnt ("lsl %A0" CR_TAB
- "rol %B0", insn, operands, len, 2);
+ "rol %B0", insn, operands, numops, len, 2);
return "";
}
@@ -6629,7 +6499,7 @@ ashlhi3_out (rtx_insn *insn, rtx operands[], int *len)
/* 24-bit shift left */
const char*
-avr_out_ashlpsi3 (rtx_insn *insn, rtx *op, int *plen)
+avr_out_ashlpsi3 (rtx_insn *insn, rtx *op, int numops, int *plen)
{
if (plen)
*plen = 0;
@@ -6684,7 +6554,7 @@ avr_out_ashlpsi3 (rtx_insn *insn, rtx *op, int *plen)
out_shift_with_cnt ("lsl %A0" CR_TAB
"rol %B0" CR_TAB
- "rol %C0", insn, op, plen, 3);
+ "rol %C0", insn, op, numops, plen, 3);
return "";
}
@@ -6692,7 +6562,7 @@ avr_out_ashlpsi3 (rtx_insn *insn, rtx *op, int *plen)
/* 32bit shift left ((long)x << i) */
const char *
-ashlsi3_out (rtx_insn *insn, rtx operands[], int *len)
+ashlsi3_out (rtx_insn *insn, rtx operands[], int numops, int *len)
{
if (CONST_INT_P (operands[2]))
{
@@ -6774,14 +6644,14 @@ ashlsi3_out (rtx_insn *insn, rtx operands[], int *len)
out_shift_with_cnt ("lsl %A0" CR_TAB
"rol %B0" CR_TAB
"rol %C0" CR_TAB
- "rol %D0", insn, operands, len, 4);
+ "rol %D0", insn, operands, numops, len, 4);
return "";
}
/* 8bit arithmetic shift right ((signed char)x >> i) */
const char *
-ashrqi3_out (rtx_insn *insn, rtx operands[], int *len)
+ashrqi3_out (rtx_insn *insn, rtx operands[], int numops, int *len)
{
if (CONST_INT_P (operands[2]))
{
@@ -6845,7 +6715,7 @@ ashrqi3_out (rtx_insn *insn, rtx operands[], int *len)
fatal_insn ("internal compiler error. Incorrect shift:", insn);
out_shift_with_cnt ("asr %0",
- insn, operands, len, 1);
+ insn, operands, numops, len, 1);
return "";
}
@@ -6853,11 +6723,12 @@ ashrqi3_out (rtx_insn *insn, rtx operands[], int *len)
/* 16bit arithmetic shift right ((signed short)x >> i) */
const char *
-ashrhi3_out (rtx_insn *insn, rtx operands[], int *len)
+ashrhi3_out (rtx_insn *insn, rtx operands[], int numops, int *len)
{
if (CONST_INT_P (operands[2]))
{
- int scratch = (GET_CODE (PATTERN (insn)) == PARALLEL);
+ int scratch = (GET_CODE (PATTERN (insn)) == PARALLEL
+ && numops == 4);
int ldi_ok = test_hard_reg_class (LD_REGS, operands[0]);
int k;
int *t = len;
@@ -7008,7 +6879,7 @@ ashrhi3_out (rtx_insn *insn, rtx operands[], int *len)
len = t;
}
out_shift_with_cnt ("asr %B0" CR_TAB
- "ror %A0", insn, operands, len, 2);
+ "ror %A0", insn, operands, numops, len, 2);
return "";
}
@@ -7016,7 +6887,7 @@ ashrhi3_out (rtx_insn *insn, rtx operands[], int *len)
/* 24-bit arithmetic shift right */
const char*
-avr_out_ashrpsi3 (rtx_insn *insn, rtx *op, int *plen)
+avr_out_ashrpsi3 (rtx_insn *insn, rtx *op, int numops, int *plen)
{
int dest = REGNO (op[0]);
int src = REGNO (op[1]);
@@ -7067,7 +6938,7 @@ avr_out_ashrpsi3 (rtx_insn *insn, rtx *op, int *plen)
out_shift_with_cnt ("asr %C0" CR_TAB
"ror %B0" CR_TAB
- "ror %A0", insn, op, plen, 3);
+ "ror %A0", insn, op, numops, plen, 3);
return "";
}
@@ -7075,7 +6946,7 @@ avr_out_ashrpsi3 (rtx_insn *insn, rtx *op, int *plen)
/* 32-bit arithmetic shift right ((signed long)x >> i) */
const char *
-ashrsi3_out (rtx_insn *insn, rtx operands[], int *len)
+ashrsi3_out (rtx_insn *insn, rtx operands[], int numops, int *len)
{
if (CONST_INT_P (operands[2]))
{
@@ -7165,14 +7036,14 @@ ashrsi3_out (rtx_insn *insn, rtx operands[], int *len)
out_shift_with_cnt ("asr %D0" CR_TAB
"ror %C0" CR_TAB
"ror %B0" CR_TAB
- "ror %A0", insn, operands, len, 4);
+ "ror %A0", insn, operands, numops, len, 4);
return "";
}
/* 8-bit logic shift right ((unsigned char)x >> i) */
const char *
-lshrqi3_out (rtx_insn *insn, rtx operands[], int *len)
+lshrqi3_out (rtx_insn *insn, rtx operands[], int numops, int *len)
{
if (CONST_INT_P (operands[2]))
{
@@ -7260,18 +7131,19 @@ lshrqi3_out (rtx_insn *insn, rtx operands[], int *len)
fatal_insn ("internal compiler error. Incorrect shift:", insn);
out_shift_with_cnt ("lsr %0",
- insn, operands, len, 1);
+ insn, operands, numops, len, 1);
return "";
}
/* 16-bit logic shift right ((unsigned short)x >> i) */
const char *
-lshrhi3_out (rtx_insn *insn, rtx operands[], int *len)
+lshrhi3_out (rtx_insn *insn, rtx operands[], int numops, int *len)
{
if (CONST_INT_P (operands[2]))
{
- int scratch = (GET_CODE (PATTERN (insn)) == PARALLEL);
+ int scratch = (GET_CODE (PATTERN (insn)) == PARALLEL
+ && numops == 4);
int ldi_ok = test_hard_reg_class (LD_REGS, operands[0]);
int k;
int *t = len;
@@ -7516,7 +7388,7 @@ lshrhi3_out (rtx_insn *insn, rtx operands[], int *len)
len = t;
}
out_shift_with_cnt ("lsr %B0" CR_TAB
- "ror %A0", insn, operands, len, 2);
+ "ror %A0", insn, operands, numops, len, 2);
return "";
}
@@ -7524,7 +7396,7 @@ lshrhi3_out (rtx_insn *insn, rtx operands[], int *len)
/* 24-bit logic shift right */
const char*
-avr_out_lshrpsi3 (rtx_insn *insn, rtx *op, int *plen)
+avr_out_lshrpsi3 (rtx_insn *insn, rtx *op, int numops, int *plen)
{
int dest = REGNO (op[0]);
int src = REGNO (op[1]);
@@ -7570,7 +7442,7 @@ avr_out_lshrpsi3 (rtx_insn *insn, rtx *op, int *plen)
out_shift_with_cnt ("lsr %C0" CR_TAB
"ror %B0" CR_TAB
- "ror %A0", insn, op, plen, 3);
+ "ror %A0", insn, op, numops, plen, 3);
return "";
}
@@ -7578,7 +7450,7 @@ avr_out_lshrpsi3 (rtx_insn *insn, rtx *op, int *plen)
/* 32-bit logic shift right ((unsigned int)x >> i) */
const char *
-lshrsi3_out (rtx_insn *insn, rtx operands[], int *len)
+lshrsi3_out (rtx_insn *insn, rtx operands[], int numops, int *len)
{
if (CONST_INT_P (operands[2]))
{
@@ -7660,7 +7532,7 @@ lshrsi3_out (rtx_insn *insn, rtx operands[], int *len)
out_shift_with_cnt ("lsr %D0" CR_TAB
"ror %C0" CR_TAB
"ror %B0" CR_TAB
- "ror %A0", insn, operands, len, 4);
+ "ror %A0", insn, operands, numops, len, 4);
return "";
}
@@ -9346,6 +9218,7 @@ int
avr_adjust_insn_length (rtx_insn *insn, int len)
{
rtx *op = recog_data.operand;
+ int numops = recog_data.n_operands;
enum attr_adjust_len adjust_len;
/* As we pretend jump tables in .text, fix branch offsets crossing jump
@@ -9411,21 +9284,21 @@ avr_adjust_insn_length (rtx_insn *insn, int len)
case ADJUST_LEN_COMPARE: avr_out_compare (insn, op, &len); break;
case ADJUST_LEN_COMPARE64: avr_out_compare64 (insn, op, &len); break;
- case ADJUST_LEN_LSHRQI: lshrqi3_out (insn, op, &len); break;
- case ADJUST_LEN_LSHRHI: lshrhi3_out (insn, op, &len); break;
- case ADJUST_LEN_LSHRSI: lshrsi3_out (insn, op, &len); break;
+ case ADJUST_LEN_LSHRQI: lshrqi3_out (insn, op, numops, &len); break;
+ case ADJUST_LEN_LSHRHI: lshrhi3_out (insn, op, numops, &len); break;
+ case ADJUST_LEN_LSHRSI: lshrsi3_out (insn, op, numops, &len); break;
- case ADJUST_LEN_ASHRQI: ashrqi3_out (insn, op, &len); break;
- case ADJUST_LEN_ASHRHI: ashrhi3_out (insn, op, &len); break;
- case ADJUST_LEN_ASHRSI: ashrsi3_out (insn, op, &len); break;
+ case ADJUST_LEN_ASHRQI: ashrqi3_out (insn, op, numops, &len); break;
+ case ADJUST_LEN_ASHRHI: ashrhi3_out (insn, op, numops, &len); break;
+ case ADJUST_LEN_ASHRSI: ashrsi3_out (insn, op, numops, &len); break;
- case ADJUST_LEN_ASHLQI: ashlqi3_out (insn, op, &len); break;
- case ADJUST_LEN_ASHLHI: ashlhi3_out (insn, op, &len); break;
- case ADJUST_LEN_ASHLSI: ashlsi3_out (insn, op, &len); break;
+ case ADJUST_LEN_ASHLQI: ashlqi3_out (insn, op, numops, &len); break;
+ case ADJUST_LEN_ASHLHI: ashlhi3_out (insn, op, numops, &len); break;
+ case ADJUST_LEN_ASHLSI: ashlsi3_out (insn, op, numops, &len); break;
- case ADJUST_LEN_ASHLPSI: avr_out_ashlpsi3 (insn, op, &len); break;
- case ADJUST_LEN_ASHRPSI: avr_out_ashrpsi3 (insn, op, &len); break;
- case ADJUST_LEN_LSHRPSI: avr_out_lshrpsi3 (insn, op, &len); break;
+ case ADJUST_LEN_ASHLPSI: avr_out_ashlpsi3 (insn, op, numops, &len); break;
+ case ADJUST_LEN_ASHRPSI: avr_out_ashrpsi3 (insn, op, numops, &len); break;
+ case ADJUST_LEN_LSHRPSI: avr_out_lshrpsi3 (insn, op, numops, &len); break;
case ADJUST_LEN_CALL: len = AVR_HAVE_JMP_CALL ? 2 : 1; break;
@@ -9619,6 +9492,18 @@ avr_assemble_integer (rtx x, unsigned int size, int aligned_p)
return default_assemble_integer (x, size, aligned_p);
}
+/* Implement TARGET_CLASS_MAX_NREGS. Reasons described in comments for
+ avr_hard_regno_nregs. */
+
+static unsigned char
+avr_class_max_nregs (reg_class_t rclass, machine_mode mode)
+{
+ if (rclass == CC_REG && mode == CCmode)
+ return 1;
+
+ return CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD);
+}
+
/* Implement `TARGET_CLASS_LIKELY_SPILLED_P'. */
/* Return value is nonzero if pseudos that have been
@@ -11719,7 +11604,7 @@ avr_compare_pattern (rtx_insn *insn)
if (pattern
&& NONJUMP_INSN_P (insn)
- && SET_DEST (pattern) == cc0_rtx
+ && SET_DEST (pattern) == cc_reg_rtx
&& GET_CODE (SET_SRC (pattern)) == COMPARE)
{
machine_mode mode0 = GET_MODE (XEXP (SET_SRC (pattern), 0));
@@ -11822,8 +11707,8 @@ avr_reorg_remove_redundant_compare (rtx_insn *insn1)
|| LABEL_REF != GET_CODE (XEXP (ifelse1, 1))
|| LABEL_REF != GET_CODE (XEXP (ifelse2, 1))
|| !COMPARISON_P (XEXP (ifelse2, 0))
- || cc0_rtx != XEXP (XEXP (ifelse1, 0), 0)
- || cc0_rtx != XEXP (XEXP (ifelse2, 0), 0)
+ || cc_reg_rtx != XEXP (XEXP (ifelse1, 0), 0)
+ || cc_reg_rtx != XEXP (XEXP (ifelse2, 0), 0)
|| const0_rtx != XEXP (XEXP (ifelse1, 0), 1)
|| const0_rtx != XEXP (XEXP (ifelse2, 0), 1))
{
@@ -11893,7 +11778,7 @@ avr_reorg_remove_redundant_compare (rtx_insn *insn1)
JUMP_LABEL (jump) = JUMP_LABEL (branch1);
target = XEXP (XEXP (ifelse2, 1), 0);
- cond = gen_rtx_fmt_ee (code, VOIDmode, cc0_rtx, const0_rtx);
+ cond = gen_rtx_fmt_ee (code, VOIDmode, cc_reg_rtx, const0_rtx);
jump = emit_jump_insn_after (gen_branch_unspec (target, cond), insn2);
JUMP_LABEL (jump) = JUMP_LABEL (branch2);
@@ -12119,6 +12004,22 @@ jump_over_one_insn_p (rtx_insn *insn, rtx dest)
&& avr_2word_insn_p (next_active_insn (insn))));
}
+/* Implement TARGET_HARD_REGNO_NREGS. CCmode is four units for historical
+ reasons. If this hook is not defined, TARGET_HARD_REGNO_NREGS
+ reports that CCmode requires four registers.
+ Define this hook to allow CCmode to fit in a single REG_CC. For
+ other modes and regs, return the number of words in mode (i.e whatever
+ the default implementation of the hook returned). */
+
+static unsigned int
+avr_hard_regno_nregs (unsigned int regno, machine_mode mode)
+{
+ if (regno == REG_CC && mode == CCmode)
+ return 1;
+
+ return CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD);
+}
+
/* Implement TARGET_HARD_REGNO_MODE_OK. On the enhanced core, anything
larger than 1 byte must start in even numbered register for "movw" to
@@ -14669,6 +14570,9 @@ avr_float_lib_compare_returns_bool (machine_mode mode, enum rtx_code)
#undef TARGET_CONDITIONAL_REGISTER_USAGE
#define TARGET_CONDITIONAL_REGISTER_USAGE avr_conditional_register_usage
+#undef TARGET_HARD_REGNO_NREGS
+#define TARGET_HARD_REGNO_NREGS avr_hard_regno_nregs
+
#undef TARGET_HARD_REGNO_MODE_OK
#define TARGET_HARD_REGNO_MODE_OK avr_hard_regno_mode_ok
#undef TARGET_HARD_REGNO_SCRATCH_OK
@@ -14694,6 +14598,9 @@ avr_float_lib_compare_returns_bool (machine_mode mode, enum rtx_code)
#undef TARGET_CLASS_LIKELY_SPILLED_P
#define TARGET_CLASS_LIKELY_SPILLED_P avr_class_likely_spilled_p
+#undef TARGET_CLASS_MAX_NREGS
+#define TARGET_CLASS_MAX_NREGS avr_class_max_nregs
+
#undef TARGET_OPTION_OVERRIDE
#define TARGET_OPTION_OVERRIDE avr_option_override
diff --git a/gcc/config/avr/avr.h b/gcc/config/avr/avr.h
index c723b8aaeeb..c62144f1233 100644
--- a/gcc/config/avr/avr.h
+++ b/gcc/config/avr/avr.h
@@ -155,7 +155,7 @@ FIXME: DRIVER_SELF_SPECS has changed.
#define WCHAR_TYPE_SIZE 16
-#define FIRST_PSEUDO_REGISTER 36
+#define FIRST_PSEUDO_REGISTER 37
#define GENERAL_REGNO_P(N) IN_RANGE (N, 2, 31)
#define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
@@ -178,7 +178,8 @@ FIXME: DRIVER_SELF_SPECS has changed.
0,0,/* r28 r29 */\
0,0,/* r30 r31 */\
1,1,/* STACK */\
- 1,1 /* arg pointer */ }
+ 1,1, /* arg pointer */ \
+ 1 /* CC */ }
#define CALL_USED_REGISTERS { \
1,1,/* r0 r1 */ \
@@ -198,7 +199,8 @@ FIXME: DRIVER_SELF_SPECS has changed.
0,0,/* r28 r29 */ \
1,1,/* r30 r31 */ \
1,1,/* STACK */ \
- 1,1 /* arg pointer */ }
+ 1,1, /* arg pointer */ \
+ 1 /* CC */ }
#define REG_ALLOC_ORDER { \
24,25, \
@@ -210,7 +212,7 @@ FIXME: DRIVER_SELF_SPECS has changed.
28,29, \
17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2, \
0,1, \
- 32,33,34,35 \
+ 32,33,34,35,36 \
}
#define ADJUST_REG_ALLOC_ORDER avr_adjust_reg_alloc_order()
@@ -230,6 +232,7 @@ enum reg_class {
LD_REGS, /* r16 - r31 */
NO_LD_REGS, /* r0 - r15 */
GENERAL_REGS, /* r0 - r31 */
+ CC_REG, /* CC */
ALL_REGS, LIM_REG_CLASSES
};
@@ -250,6 +253,7 @@ enum reg_class {
"LD_REGS", /* r16 - r31 */ \
"NO_LD_REGS", /* r0 - r15 */ \
"GENERAL_REGS", /* r0 - r31 */ \
+ "CC_REG", /* CC */ \
"ALL_REGS" }
#define REG_CLASS_CONTENTS { \
@@ -270,7 +274,8 @@ enum reg_class {
0x00000000}, /* LD_REGS, r16 - r31 */ \
{0x0000ffff,0x00000000}, /* NO_LD_REGS r0 - r15 */ \
{0xffffffff,0x00000000}, /* GENERAL_REGS, r0 - r31 */ \
- {0xffffffff,0x00000003} /* ALL_REGS */ \
+ {0x00000000,0x00000010}, /* CC */ \
+ {0xffffffff,0x00000013} /* ALL_REGS */ \
}
#define REGNO_REG_CLASS(R) avr_regno_reg_class(R)
@@ -429,7 +434,7 @@ typedef struct avr_args
"r8","r9","r10","r11","r12","r13","r14","r15", \
"r16","r17","r18","r19","r20","r21","r22","r23", \
"r24","r25","r26","r27","r28","r29","r30","r31", \
- "__SP_L__","__SP_H__","argL","argH"}
+ "__SP_L__","__SP_H__","argL","argH", "CC"}
#define FINAL_PRESCAN_INSN(insn, operand, nop) \
avr_final_prescan_insn (insn, operand,nop)
@@ -484,13 +489,6 @@ typedef struct avr_args
#define TRAMPOLINE_SIZE 4
-/* Store in cc_status the expressions
- that the condition codes will describe
- after execution of an instruction whose pattern is EXP.
- Do not alter them if the instruction would not alter the cc's. */
-
-#define NOTICE_UPDATE_CC(EXP, INSN) avr_notice_update_cc (EXP, INSN)
-
/* The add insns don't set overflow in a usable way. */
#define CC_OVERFLOW_UNUSABLE 01000
/* The mov,and,or,xor insns don't set carry. That's ok though as the
@@ -500,7 +498,6 @@ typedef struct avr_args
understandable. */
#define CC_NO_CARRY CC_NO_OVERFLOW
-
/* Output assembler code to FILE to increment profiler label # LABELNO
for profiling a function entry. */
diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index 41eb78c9855..1a79759958f 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -58,6 +58,7 @@
(REG_Z 30)
(REG_W 24)
(REG_SP 32)
+ (REG_CC 36)
(LPM_REGNO 0) ; implicit target register of LPM
(TMP_REGNO 0) ; temporary register r0
(ZERO_REGNO 1) ; zero register r1
@@ -459,7 +460,8 @@
"reload_completed
&& frame_pointer_needed
&& !cfun->calls_alloca
- && find_reg_note (insn, REG_ARGS_SIZE, const0_rtx)"
+ && find_reg_note (insn, REG_ARGS_SIZE, const0_rtx)
+ && REGNO (operands[0]) != REG_Y"
[(set (reg:HI REG_SP)
(reg:HI REG_Y))])
@@ -491,19 +493,32 @@
;; "load_psi_libgcc"
;; "load_si_libgcc"
;; "load_sf_libgcc"
-(define_insn "load_<mode>_libgcc"
+(define_insn_and_split "load_<mode>_libgcc"
[(set (reg:MOVMODE 22)
(match_operand:MOVMODE 0 "memory_operand" "m,m"))]
"avr_load_libgcc_p (operands[0])
&& REG_P (XEXP (operands[0], 0))
&& REG_Z == REGNO (XEXP (operands[0], 0))"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:MOVMODE 22)
+ (match_dup 0))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*load_<mode>_libgcc"
+ [(set (reg:MOVMODE 22)
+ (match_operand:MOVMODE 0 "memory_operand" "m,m"))
+ (clobber (reg:CC REG_CC))]
+ "avr_load_libgcc_p (operands[0])
+ && REG_P (XEXP (operands[0], 0))
+ && REG_Z == REGNO (XEXP (operands[0], 0))
+ && reload_completed"
{
operands[0] = GEN_INT (GET_MODE_SIZE (<MODE>mode));
return "%~call __load_%0";
}
[(set_attr "length" "1,2")
- (set_attr "isa" "rjmp,jmp")
- (set_attr "cc" "clobber")])
+ (set_attr "isa" "rjmp,jmp")])
;; "xload8qi_A"
@@ -591,8 +606,7 @@
}
[(set_attr "length" "4,4")
(set_attr "adjust_len" "*,xload")
- (set_attr "isa" "lpmx,lpm")
- (set_attr "cc" "none")])
+ (set_attr "isa" "lpmx,lpm")])
;; R21:Z : 24-bit source address
;; R22 : 1-4 byte output
@@ -602,21 +616,35 @@
;; "xload_si_libgcc" "xload_sq_libgcc" "xload_usq_libgcc" "xload_sa_libgcc" "xload_usa_libgcc"
;; "xload_sf_libgcc"
;; "xload_psi_libgcc"
-(define_insn "xload_<mode>_libgcc"
+
+(define_insn_and_split "xload_<mode>_libgcc"
[(set (reg:MOVMODE 22)
(mem:MOVMODE (lo_sum:PSI (reg:QI 21)
(reg:HI REG_Z))))
(clobber (reg:QI 21))
(clobber (reg:HI REG_Z))]
"avr_xload_libgcc_p (<MODE>mode)"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:MOVMODE 22)
+ (mem:MOVMODE (lo_sum:PSI (reg:QI 21)
+ (reg:HI REG_Z))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*xload_<mode>_libgcc"
+ [(set (reg:MOVMODE 22)
+ (mem:MOVMODE (lo_sum:PSI (reg:QI 21)
+ (reg:HI REG_Z))))
+ (clobber (reg:CC REG_CC))]
+ "avr_xload_libgcc_p (<MODE>mode)
+ && reload_completed"
{
rtx x_bytes = GEN_INT (GET_MODE_SIZE (<MODE>mode));
output_asm_insn ("%~call __xload_%0", &x_bytes);
return "";
}
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;; General move expanders
@@ -696,17 +724,29 @@
;; "movqi_insn"
;; "movqq_insn" "movuqq_insn"
-(define_insn "mov<mode>_insn"
+(define_insn_and_split "mov<mode>_insn"
[(set (match_operand:ALL1 0 "nonimmediate_operand" "=r ,d ,Qm ,r ,q,r,*r")
(match_operand:ALL1 1 "nox_general_operand" "r Y00,n Ynn,r Y00,Qm,r,q,i"))]
"register_operand (operands[0], <MODE>mode)
|| reg_or_0_operand (operands[1], <MODE>mode)"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (match_dup 1))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*mov<mode>_insn"
+ [(set (match_operand:ALL1 0 "nonimmediate_operand" "=r ,d ,Qm ,r ,q,r,*r")
+ (match_operand:ALL1 1 "nox_general_operand" "r Y00,n Ynn,r Y00,Qm,r,q,i"))
+ (clobber (reg:CC REG_CC))]
+ "(register_operand (operands[0], <MODE>mode)
+ || reg_or_0_operand (operands[1], <MODE>mode))
+ && reload_completed"
{
return output_movqi (insn, operands, NULL);
}
[(set_attr "length" "1,1,5,5,1,1,4")
- (set_attr "adjust_len" "mov8")
- (set_attr "cc" "ldi,none,clobber,clobber,none,none,clobber")])
+ (set_attr "adjust_len" "mov8")])
;; This is used in peephole2 to optimize loading immediate constants
;; if a scratch register from LD_REGS happens to be available.
@@ -720,8 +760,7 @@
"reload_completed"
"ldi %2,lo8(%1)
mov %0,%2"
- [(set_attr "length" "2")
- (set_attr "cc" "none")])
+ [(set_attr "length" "2")])
(define_peephole2
[(match_scratch:QI 2 "d")
@@ -759,8 +798,7 @@
out %A0,%A1
out %A0,%A1\;out %B0,%B1"
[(set_attr "length" "2,4,5,1,2")
- (set_attr "isa" "no_xmega,no_xmega,no_xmega,*,xmega")
- (set_attr "cc" "none")])
+ (set_attr "isa" "no_xmega,no_xmega,no_xmega,*,xmega")])
(define_peephole2
[(match_scratch:QI 2 "d")
@@ -769,7 +807,8 @@
"operands[1] != CONST0_RTX (<MODE>mode)"
[(parallel [(set (match_dup 0)
(match_dup 1))
- (clobber (match_dup 2))])])
+ (clobber (match_dup 2))
+ (clobber (reg:CC REG_CC))])])
;; '*' because it is not used in rtl generation, only in above peephole
;; "*reload_inhi"
@@ -778,29 +817,41 @@
(define_insn "*reload_in<mode>"
[(set (match_operand:ALL2 0 "l_register_operand" "=l")
(match_operand:ALL2 1 "immediate_operand" "i"))
- (clobber (match_operand:QI 2 "register_operand" "=&d"))]
+ (clobber (match_operand:QI 2 "register_operand" "=&d"))
+ (clobber (reg:CC REG_CC))]
"reload_completed"
{
return output_reload_inhi (operands, operands[2], NULL);
}
[(set_attr "length" "4")
- (set_attr "adjust_len" "reload_in16")
- (set_attr "cc" "clobber")])
+ (set_attr "adjust_len" "reload_in16")])
;; "*movhi"
;; "*movhq" "*movuhq"
;; "*movha" "*movuha"
-(define_insn "*mov<mode>"
+(define_insn_and_split "*mov<mode>_split"
[(set (match_operand:ALL2 0 "nonimmediate_operand" "=r,r ,r,m ,d,*r,q,r")
(match_operand:ALL2 1 "nox_general_operand" "r,Y00,m,r Y00,i,i ,r,q"))]
"register_operand (operands[0], <MODE>mode)
|| reg_or_0_operand (operands[1], <MODE>mode)"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (match_dup 1))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*mov<mode>"
+ [(set (match_operand:ALL2 0 "nonimmediate_operand" "=r,r ,r,m ,d,*r,q,r")
+ (match_operand:ALL2 1 "nox_general_operand" "r,Y00,m,r Y00,i,i ,r,q"))
+ (clobber (reg:CC REG_CC))]
+ "(register_operand (operands[0], <MODE>mode)
+ || reg_or_0_operand (operands[1], <MODE>mode))
+ && reload_completed"
{
return output_movhi (insn, operands, NULL);
}
[(set_attr "length" "2,2,6,7,2,6,5,2")
- (set_attr "adjust_len" "mov16")
- (set_attr "cc" "none,none,clobber,clobber,none,clobber,none,none")])
+ (set_attr "adjust_len" "mov16")])
(define_peephole2 ; movw
[(set (match_operand:ALL1 0 "even_register_operand" "")
@@ -844,7 +895,10 @@
[(set (match_operand:HISI 0 "register_operand" "")
(match_operand:HISI 1 "memory_operand" ""))]
"reload_completed
- && AVR_HAVE_LPMX"
+ && AVR_HAVE_LPMX
+ && avr_mem_flash_p (operands[1])
+ && REG_P (XEXP (operands[1], 0))
+ && !reg_overlap_mentioned_p (XEXP (operands[1], 0), operands[0])"
[(set (match_dup 0)
(match_dup 2))
(set (match_dup 3)
@@ -853,13 +907,6 @@
{
rtx addr = XEXP (operands[1], 0);
- if (!avr_mem_flash_p (operands[1])
- || !REG_P (addr)
- || reg_overlap_mentioned_p (addr, operands[0]))
- {
- FAIL;
- }
-
operands[2] = replace_equiv_address (operands[1],
gen_rtx_POST_INC (Pmode, addr));
operands[3] = addr;
@@ -878,33 +925,47 @@
&& operands[1] != constm1_rtx"
[(parallel [(set (match_dup 0)
(match_dup 1))
- (clobber (match_dup 2))])])
+ (clobber (match_dup 2))
+ (clobber (reg:CC REG_CC))])])
;; '*' because it is not used in rtl generation.
(define_insn "*reload_inpsi"
[(set (match_operand:PSI 0 "register_operand" "=r")
(match_operand:PSI 1 "immediate_operand" "i"))
- (clobber (match_operand:QI 2 "register_operand" "=&d"))]
+ (clobber (match_operand:QI 2 "register_operand" "=&d"))
+ (clobber (reg:CC REG_CC))]
"reload_completed"
{
return avr_out_reload_inpsi (operands, operands[2], NULL);
}
[(set_attr "length" "6")
- (set_attr "adjust_len" "reload_in24")
- (set_attr "cc" "clobber")])
+ (set_attr "adjust_len" "reload_in24")])
-(define_insn "*movpsi"
+(define_insn_and_split "*movpsi_split"
[(set (match_operand:PSI 0 "nonimmediate_operand" "=r,r,r ,Qm,!d,r")
(match_operand:PSI 1 "nox_general_operand" "r,L,Qm,rL,i ,i"))]
"register_operand (operands[0], PSImode)
|| register_operand (operands[1], PSImode)
|| const0_rtx == operands[1]"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (match_dup 1))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*movpsi"
+ [(set (match_operand:PSI 0 "nonimmediate_operand" "=r,r,r ,Qm,!d,r")
+ (match_operand:PSI 1 "nox_general_operand" "r,L,Qm,rL,i ,i"))
+ (clobber (reg:CC REG_CC))]
+ "(register_operand (operands[0], PSImode)
+ || register_operand (operands[1], PSImode)
+ || const0_rtx == operands[1])
+ && reload_completed"
{
return avr_out_movpsi (insn, operands, NULL);
}
[(set_attr "length" "3,3,8,9,4,10")
- (set_attr "adjust_len" "mov24")
- (set_attr "cc" "none,none,clobber,clobber,none,clobber")])
+ (set_attr "adjust_len" "mov24")])
;;==========================================================================
;; move double word (32 bit)
@@ -917,7 +978,8 @@
"operands[1] != CONST0_RTX (<MODE>mode)"
[(parallel [(set (match_dup 0)
(match_dup 1))
- (clobber (match_dup 2))])])
+ (clobber (match_dup 2))
+ (clobber (reg:CC REG_CC))])])
;; '*' because it is not used in rtl generation.
;; "*reload_insi"
@@ -926,45 +988,69 @@
(define_insn "*reload_insi"
[(set (match_operand:ALL4 0 "register_operand" "=r")
(match_operand:ALL4 1 "immediate_operand" "n Ynn"))
- (clobber (match_operand:QI 2 "register_operand" "=&d"))]
+ (clobber (match_operand:QI 2 "register_operand" "=&d"))
+ (clobber (reg:CC REG_CC))]
"reload_completed"
{
return output_reload_insisf (operands, operands[2], NULL);
}
[(set_attr "length" "8")
- (set_attr "adjust_len" "reload_in32")
- (set_attr "cc" "clobber")])
+ (set_attr "adjust_len" "reload_in32")])
;; "*movsi"
;; "*movsq" "*movusq"
;; "*movsa" "*movusa"
-(define_insn "*mov<mode>"
+(define_insn_and_split "*mov<mode>_split"
[(set (match_operand:ALL4 0 "nonimmediate_operand" "=r,r ,r ,Qm ,!d,r")
(match_operand:ALL4 1 "nox_general_operand" "r,Y00,Qm,r Y00,i ,i"))]
"register_operand (operands[0], <MODE>mode)
|| reg_or_0_operand (operands[1], <MODE>mode)"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (match_dup 1))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*mov<mode>"
+ [(set (match_operand:ALL4 0 "nonimmediate_operand" "=r,r ,r ,Qm ,!d,r")
+ (match_operand:ALL4 1 "nox_general_operand" "r,Y00,Qm,r Y00,i ,i"))
+ (clobber (reg:CC REG_CC))]
+ "(register_operand (operands[0], <MODE>mode)
+ || reg_or_0_operand (operands[1], <MODE>mode))
+ && reload_completed"
{
return output_movsisf (insn, operands, NULL);
}
[(set_attr "length" "4,4,8,9,4,10")
- (set_attr "adjust_len" "mov32")
- (set_attr "cc" "none,none,clobber,clobber,none,clobber")])
+ (set_attr "adjust_len" "mov32")])
;; fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
;; move floating point numbers (32 bit)
-(define_insn "*movsf"
+(define_insn_and_split "*movsf_split"
[(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r ,Qm,!d,r")
(match_operand:SF 1 "nox_general_operand" "r,G,Qm,rG,F ,F"))]
"register_operand (operands[0], SFmode)
|| reg_or_0_operand (operands[1], SFmode)"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (match_dup 1))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*movsf"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r ,Qm,!d,r")
+ (match_operand:SF 1 "nox_general_operand" "r,G,Qm,rG,F ,F"))
+ (clobber (reg:CC REG_CC))]
+ "(register_operand (operands[0], SFmode)
+ || reg_or_0_operand (operands[1], SFmode))
+ && reload_completed"
{
return output_movsisf (insn, operands, NULL);
}
[(set_attr "length" "4,4,8,9,4,10")
- (set_attr "adjust_len" "mov32")
- (set_attr "cc" "none,none,clobber,clobber,none,clobber")])
+ (set_attr "adjust_len" "mov32")])
(define_peephole2 ; *reload_insf
[(match_scratch:QI 2 "d")
@@ -974,20 +1060,21 @@
"operands[1] != CONST0_RTX (SFmode)"
[(parallel [(set (match_dup 0)
(match_dup 1))
- (clobber (match_dup 2))])])
+ (clobber (match_dup 2))
+ (clobber (reg:CC REG_CC))])])
;; '*' because it is not used in rtl generation.
(define_insn "*reload_insf"
[(set (match_operand:SF 0 "register_operand" "=r")
(match_operand:SF 1 "const_double_operand" "F"))
- (clobber (match_operand:QI 2 "register_operand" "=&d"))]
+ (clobber (match_operand:QI 2 "register_operand" "=&d"))
+ (clobber (reg:CC REG_CC))]
"reload_completed"
{
return output_reload_insisf (operands, operands[2], NULL);
}
[(set_attr "length" "8")
- (set_attr "adjust_len" "reload_in32")
- (set_attr "cc" "clobber")])
+ (set_attr "adjust_len" "reload_in32")])
;;=========================================================================
;; move string (like memcpy)
@@ -1015,7 +1102,7 @@
;; "cpymem_qi"
;; "cpymem_hi"
-(define_insn "cpymem_<mode>"
+(define_insn_and_split "cpymem_<mode>"
[(set (mem:BLK (reg:HI REG_X))
(mem:BLK (reg:HI REG_Z)))
(unspec [(match_operand:QI 0 "const_int_operand" "n")]
@@ -1026,11 +1113,35 @@
(clobber (reg:QI LPM_REGNO))
(clobber (match_operand:QIHI 2 "register_operand" "=1"))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (mem:BLK (reg:HI REG_X))
+ (mem:BLK (reg:HI REG_Z)))
+ (unspec [(match_dup 0)]
+ UNSPEC_CPYMEM)
+ (use (match_dup 1))
+ (clobber (reg:HI REG_X))
+ (clobber (reg:HI REG_Z))
+ (clobber (reg:QI LPM_REGNO))
+ (clobber (match_dup 2))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*cpymem_<mode>"
+ [(set (mem:BLK (reg:HI REG_X))
+ (mem:BLK (reg:HI REG_Z)))
+ (unspec [(match_operand:QI 0 "const_int_operand" "n")]
+ UNSPEC_CPYMEM)
+ (use (match_operand:QIHI 1 "register_operand" "<CPYMEM_r_d>"))
+ (clobber (reg:HI REG_X))
+ (clobber (reg:HI REG_Z))
+ (clobber (reg:QI LPM_REGNO))
+ (clobber (match_operand:QIHI 2 "register_operand" "=1"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return avr_out_cpymem (insn, operands, NULL);
}
- [(set_attr "adjust_len" "cpymem")
- (set_attr "cc" "clobber")])
+ [(set_attr "adjust_len" "cpymem")])
;; $0 : Address Space
@@ -1041,7 +1152,8 @@
;; "cpymemx_qi"
;; "cpymemx_hi"
-(define_insn "cpymemx_<mode>"
+
+(define_insn_and_split "cpymemx_<mode>"
[(set (mem:BLK (reg:HI REG_X))
(mem:BLK (lo_sum:PSI (reg:QI 23)
(reg:HI REG_Z))))
@@ -1055,9 +1167,39 @@
(clobber (reg:QI 23))
(clobber (mem:QI (match_operand:QI 1 "io_address_operand" "n")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (mem:BLK (reg:HI REG_X))
+ (mem:BLK (lo_sum:PSI (reg:QI 23)
+ (reg:HI REG_Z))))
+ (unspec [(match_dup 0)]
+ UNSPEC_CPYMEM)
+ (use (reg:QIHI 24))
+ (clobber (reg:HI REG_X))
+ (clobber (reg:HI REG_Z))
+ (clobber (reg:QI LPM_REGNO))
+ (clobber (reg:HI 24))
+ (clobber (reg:QI 23))
+ (clobber (mem:QI (match_dup 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*cpymemx_<mode>"
+ [(set (mem:BLK (reg:HI REG_X))
+ (mem:BLK (lo_sum:PSI (reg:QI 23)
+ (reg:HI REG_Z))))
+ (unspec [(match_operand:QI 0 "const_int_operand" "n")]
+ UNSPEC_CPYMEM)
+ (use (reg:QIHI 24))
+ (clobber (reg:HI REG_X))
+ (clobber (reg:HI REG_Z))
+ (clobber (reg:QI LPM_REGNO))
+ (clobber (reg:HI 24))
+ (clobber (reg:QI 23))
+ (clobber (mem:QI (match_operand:QI 1 "io_address_operand" "n")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __movmemx_<mode>"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;; =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2
@@ -1091,7 +1233,7 @@
})
-(define_insn "*clrmemqi"
+(define_insn_and_split "*clrmemqi_split"
[(set (mem:BLK (match_operand:HI 0 "register_operand" "e"))
(const_int 0))
(use (match_operand:QI 1 "register_operand" "r"))
@@ -1099,12 +1241,30 @@
(clobber (match_scratch:HI 3 "=0"))
(clobber (match_scratch:QI 4 "=&1"))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (mem:BLK (match_dup 0))
+ (const_int 0))
+ (use (match_dup 1))
+ (use (match_dup 2))
+ (clobber (match_dup 3))
+ (clobber (match_dup 4))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*clrmemqi"
+ [(set (mem:BLK (match_operand:HI 0 "register_operand" "e"))
+ (const_int 0))
+ (use (match_operand:QI 1 "register_operand" "r"))
+ (use (match_operand:QI 2 "const_int_operand" "n"))
+ (clobber (match_scratch:HI 3 "=0"))
+ (clobber (match_scratch:QI 4 "=&1"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"0:\;st %a0+,__zero_reg__\;dec %1\;brne 0b"
- [(set_attr "length" "3")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "3")])
-(define_insn "*clrmemhi"
+(define_insn_and_split "*clrmemhi_split"
[(set (mem:BLK (match_operand:HI 0 "register_operand" "e,e"))
(const_int 0))
(use (match_operand:HI 1 "register_operand" "!w,d"))
@@ -1112,11 +1272,30 @@
(clobber (match_scratch:HI 3 "=0,0"))
(clobber (match_scratch:HI 4 "=&1,&1"))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (mem:BLK (match_dup 0))
+ (const_int 0))
+ (use (match_dup 1))
+ (use (match_dup 2))
+ (clobber (match_dup 3))
+ (clobber (match_dup 4))
+ (clobber (reg:CC REG_CC))])])
+
+
+(define_insn "*clrmemhi"
+ [(set (mem:BLK (match_operand:HI 0 "register_operand" "e,e"))
+ (const_int 0))
+ (use (match_operand:HI 1 "register_operand" "!w,d"))
+ (use (match_operand:HI 2 "const_int_operand" "n,n"))
+ (clobber (match_scratch:HI 3 "=0,0"))
+ (clobber (match_scratch:HI 4 "=&1,&1"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"@
0:\;st %a0+,__zero_reg__\;sbiw %A1,1\;brne 0b
0:\;st %a0+,__zero_reg__\;subi %A1,1\;sbci %B1,0\;brne 0b"
- [(set_attr "length" "3,4")
- (set_attr "cc" "clobber,clobber")])
+ [(set_attr "length" "3,4")])
(define_expand "strlenhi"
[(set (match_dup 4)
@@ -1142,27 +1321,57 @@
operands[4] = gen_reg_rtx (HImode);
})
-(define_insn "*strlenhi"
+(define_insn_and_split "*strlenhi_split"
[(set (match_operand:HI 0 "register_operand" "=e")
(unspec:HI [(mem:BLK (match_operand:HI 1 "register_operand" "0"))
(const_int 0)
(match_operand:HI 2 "immediate_operand" "i")]
UNSPEC_STRLEN))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel
+ [(set (match_dup 0)
+ (unspec:HI [(mem:BLK (match_dup 1))
+ (const_int 0)
+ (match_dup 2)]
+ UNSPEC_STRLEN))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*strlenhi"
+ [(set (match_operand:HI 0 "register_operand" "=e")
+ (unspec:HI [(mem:BLK (match_operand:HI 1 "register_operand" "0"))
+ (const_int 0)
+ (match_operand:HI 2 "immediate_operand" "i")]
+ UNSPEC_STRLEN))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"0:\;ld __tmp_reg__,%a0+\;tst __tmp_reg__\;brne 0b"
- [(set_attr "length" "3")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "3")])
;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; add bytes
;; "addqi3"
;; "addqq3" "adduqq3"
-(define_insn "add<mode>3"
+(define_insn_and_split "add<mode>3"
[(set (match_operand:ALL1 0 "register_operand" "=r,d ,r ,r ,r ,r")
(plus:ALL1 (match_operand:ALL1 1 "register_operand" "%0,0 ,0 ,0 ,0 ,0")
(match_operand:ALL1 2 "nonmemory_operand" "r,n Ynn,Y01,Ym1,Y02,Ym2")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (plus:ALL1 (match_dup 1)
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*add<mode>3"
+ [(set (match_operand:ALL1 0 "register_operand" "=r,d ,r ,r ,r ,r")
+ (plus:ALL1 (match_operand:ALL1 1 "register_operand" "%0,0 ,0 ,0 ,0 ,0")
+ (match_operand:ALL1 2 "nonmemory_operand" "r,n Ynn,Y01,Ym1,Y02,Ym2")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"@
add %0,%2
subi %0,lo8(-(%2))
@@ -1170,8 +1379,7 @@
dec %0
inc %0\;inc %0
dec %0\;dec %0"
- [(set_attr "length" "1,1,1,1,2,2")
- (set_attr "cc" "set_czn,set_czn,set_vzn,set_vzn,set_vzn,set_vzn")])
+ [(set_attr "length" "1,1,1,1,2,2")])
;; "addhi3"
;; "addhq3" "adduhq3"
@@ -1205,67 +1413,144 @@
})
-(define_insn "*addhi3_zero_extend"
+(define_insn_and_split "*addhi3_zero_extend_split"
[(set (match_operand:HI 0 "register_operand" "=r,*?r")
(plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r ,0"))
(match_operand:HI 2 "register_operand" "0 ,r")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (plus:HI (zero_extend:HI (match_dup 1))
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*addhi3_zero_extend"
+ [(set (match_operand:HI 0 "register_operand" "=r,*?r")
+ (plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r ,0"))
+ (match_operand:HI 2 "register_operand" "0 ,r")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"@
add %A0,%1\;adc %B0,__zero_reg__
add %A0,%A2\;mov %B0,%B2\;adc %B0,__zero_reg__"
- [(set_attr "length" "2,3")
- (set_attr "cc" "set_n")])
+ [(set_attr "length" "2,3")])
-(define_insn "*addhi3_zero_extend1"
+(define_insn_and_split "*addhi3_zero_extend1_split"
[(set (match_operand:HI 0 "register_operand" "=r")
(plus:HI (match_operand:HI 1 "register_operand" "0")
(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (plus:HI (match_dup 1)
+ (zero_extend:HI (match_dup 2))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*addhi3_zero_extend1"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (plus:HI (match_operand:HI 1 "register_operand" "0")
+ (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"add %A0,%2\;adc %B0,__zero_reg__"
- [(set_attr "length" "2")
- (set_attr "cc" "set_n")])
+ [(set_attr "length" "2")])
-(define_insn "*addhi3.sign_extend1"
+(define_insn_and_split "*addhi3.sign_extend1_split"
[(set (match_operand:HI 0 "register_operand" "=r")
(plus:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "r"))
(match_operand:HI 2 "register_operand" "0")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel
+ [(set (match_dup 0)
+ (plus:HI
+ (sign_extend:HI (match_dup 1))
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+
+(define_insn "*addhi3.sign_extend1"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (plus:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "r"))
+ (match_operand:HI 2 "register_operand" "0")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return reg_overlap_mentioned_p (operands[0], operands[1])
? "mov __tmp_reg__,%1\;add %A0,%1\;adc %B0,__zero_reg__\;sbrc __tmp_reg__,7\;dec %B0"
: "add %A0,%1\;adc %B0,__zero_reg__\;sbrc %1,7\;dec %B0";
}
- [(set_attr "length" "5")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "5")])
-(define_insn "*addhi3_zero_extend.const"
+(define_insn_and_split "*addhi3_zero_extend.const_split"
[(set (match_operand:HI 0 "register_operand" "=d")
(plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
(match_operand:HI 2 "const_m255_to_m1_operand" "Cn8")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (plus:HI (zero_extend:HI (match_dup 1))
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*addhi3_zero_extend.const"
+ [(set (match_operand:HI 0 "register_operand" "=d")
+ (plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
+ (match_operand:HI 2 "const_m255_to_m1_operand" "Cn8")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"subi %A0,%n2\;sbc %B0,%B0"
- [(set_attr "length" "2")
- (set_attr "cc" "set_czn")])
+ [(set_attr "length" "2")])
-(define_insn "*usum_widenqihi3"
+(define_insn_and_split "*usum_widenqihi3_split"
[(set (match_operand:HI 0 "register_operand" "=r")
(plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (plus:HI
+ (zero_extend:HI (match_dup 1))
+ (zero_extend:HI (match_dup 2))))
+ (clobber (reg:CC REG_CC))])])
+
+
+(define_insn "*usum_widenqihi3"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
+ (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"add %A0,%2\;clr %B0\;rol %B0"
- [(set_attr "length" "3")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "3")])
-(define_insn "*udiff_widenqihi3"
+(define_insn_and_split "*udiff_widenqihi3_split"
[(set (match_operand:HI 0 "register_operand" "=r")
(minus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (minus:HI (zero_extend:HI (match_dup 1))
+ (zero_extend:HI (match_dup 2))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*udiff_widenqihi3"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (minus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
+ (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"sub %A0,%2\;sbc %B0,%B0"
- [(set_attr "length" "2")
- (set_attr "cc" "set_czn")])
+ [(set_attr "length" "2")])
-(define_insn "*addhi3_sp"
+(define_insn_and_split "*addhi3_sp"
[(set (match_operand:HI 1 "stack_register_operand" "=q")
(plus:HI (match_operand:HI 2 "stack_register_operand" "q")
(match_operand:HI 0 "avr_sp_immediate_operand" "Csp")))]
@@ -1273,23 +1558,44 @@
{
return avr_out_addto_sp (operands, NULL);
}
+ ""
+ [(const_int 0)]
+ {
+ /* Do not attempt to split this pattern. This FAIL is necessary
+ to prevent the splitter from matching *add<ALL2>3_split, splitting
+ it, and then failing later because constraints don't match, as split
+ does not look at constraints. */
+ FAIL;
+ }
[(set_attr "length" "6")
(set_attr "adjust_len" "addto_sp")])
;; "*addhi3"
;; "*addhq3" "*adduhq3"
;; "*addha3" "*adduha3"
-(define_insn "*add<mode>3"
+(define_insn_and_split "*add<mode>3_split"
[(set (match_operand:ALL2 0 "register_operand" "=??r,d,!w ,d")
(plus:ALL2 (match_operand:ALL2 1 "register_operand" "%0,0,0 ,0")
(match_operand:ALL2 2 "nonmemory_or_const_operand" "r,s,IJ YIJ,n Ynn")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (plus:ALL2 (match_dup 1)
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*add<mode>3"
+ [(set (match_operand:ALL2 0 "register_operand" "=??r,d,!w ,d")
+ (plus:ALL2 (match_operand:ALL2 1 "register_operand" "%0,0,0 ,0")
+ (match_operand:ALL2 2 "nonmemory_or_const_operand" "r,s,IJ YIJ,n Ynn")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return avr_out_plus (insn, operands);
}
[(set_attr "length" "2")
- (set_attr "adjust_len" "plus")
- (set_attr "cc" "plus")])
+ (set_attr "adjust_len" "plus")])
;; Adding a constant to NO_LD_REGS might have lead to a reload of
;; that constant to LD_REGS. We don't add a scratch to *addhi3
@@ -1329,140 +1635,303 @@
;; "addhi3_clobber"
;; "addhq3_clobber" "adduhq3_clobber"
;; "addha3_clobber" "adduha3_clobber"
-(define_insn "add<mode>3_clobber"
+(define_insn_and_split "add<mode>3_clobber"
[(set (match_operand:ALL2 0 "register_operand" "=!w ,d ,r")
(plus:ALL2 (match_operand:ALL2 1 "register_operand" "%0 ,0 ,0")
(match_operand:ALL2 2 "const_operand" "IJ YIJ,n Ynn,n Ynn")))
(clobber (match_scratch:QI 3 "=X ,X ,&d"))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (plus:ALL2 (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_dup 3))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*add<mode>3_clobber"
+ [(set (match_operand:ALL2 0 "register_operand" "=!w ,d ,r")
+ (plus:ALL2 (match_operand:ALL2 1 "register_operand" "%0 ,0 ,0")
+ (match_operand:ALL2 2 "const_operand" "IJ YIJ,n Ynn,n Ynn")))
+ (clobber (match_scratch:QI 3 "=X ,X ,&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return avr_out_plus (insn, operands);
}
[(set_attr "length" "4")
- (set_attr "adjust_len" "plus")
- (set_attr "cc" "plus")])
+ (set_attr "adjust_len" "plus")])
;; "addsi3"
;; "addsq3" "addusq3"
;; "addsa3" "addusa3"
-(define_insn "add<mode>3"
+(define_insn_and_split "add<mode>3"
[(set (match_operand:ALL4 0 "register_operand" "=??r,d ,r")
(plus:ALL4 (match_operand:ALL4 1 "register_operand" "%0,0 ,0")
(match_operand:ALL4 2 "nonmemory_operand" "r,i ,n Ynn")))
(clobber (match_scratch:QI 3 "=X,X ,&d"))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (plus:ALL4 (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_dup 3))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*add<mode>3"
+ [(set (match_operand:ALL4 0 "register_operand" "=??r,d ,r")
+ (plus:ALL4 (match_operand:ALL4 1 "register_operand" "%0,0 ,0")
+ (match_operand:ALL4 2 "nonmemory_operand" "r,i ,n Ynn")))
+ (clobber (match_scratch:QI 3 "=X,X ,&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return avr_out_plus (insn, operands);
}
[(set_attr "length" "4")
- (set_attr "adjust_len" "plus")
- (set_attr "cc" "plus")])
+ (set_attr "adjust_len" "plus")])
-(define_insn "*addpsi3_zero_extend.qi"
+(define_insn_and_split "*addpsi3_zero_extend.qi_split"
[(set (match_operand:PSI 0 "register_operand" "=r")
(plus:PSI (zero_extend:PSI (match_operand:QI 1 "register_operand" "r"))
(match_operand:PSI 2 "register_operand" "0")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (plus:PSI (zero_extend:PSI (match_dup 1))
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*addpsi3_zero_extend.qi"
+ [(set (match_operand:PSI 0 "register_operand" "=r")
+ (plus:PSI (zero_extend:PSI (match_operand:QI 1 "register_operand" "r"))
+ (match_operand:PSI 2 "register_operand" "0")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"add %A0,%A1\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__"
- [(set_attr "length" "3")
- (set_attr "cc" "set_n")])
+ [(set_attr "length" "3")])
-(define_insn "*addpsi3_zero_extend.hi"
+(define_insn_and_split "*addpsi3_zero_extend.hi_split"
[(set (match_operand:PSI 0 "register_operand" "=r")
(plus:PSI (zero_extend:PSI (match_operand:HI 1 "register_operand" "r"))
(match_operand:PSI 2 "register_operand" "0")))]
""
- "add %A0,%A1\;adc %B0,%B1\;adc %C0,__zero_reg__"
- [(set_attr "length" "3")
- (set_attr "cc" "set_n")])
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (plus:PSI (zero_extend:PSI (match_dup 1))
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
-(define_insn "*addpsi3_sign_extend.hi"
+(define_insn "*addpsi3_zero_extend.hi"
+ [(set (match_operand:PSI 0 "register_operand" "=r")
+ (plus:PSI (zero_extend:PSI (match_operand:HI 1 "register_operand" "r"))
+ (match_operand:PSI 2 "register_operand" "0")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
+ "add %A0,%A1\;adc %B0,%B1\;adc %C0,__zero_reg__"
+ [(set_attr "length" "3")])
+
+(define_insn_and_split "*addpsi3_sign_extend.hi_split"
[(set (match_operand:PSI 0 "register_operand" "=r")
(plus:PSI (sign_extend:PSI (match_operand:HI 1 "register_operand" "r"))
(match_operand:PSI 2 "register_operand" "0")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (plus:PSI (sign_extend:PSI (match_dup 1))
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*addpsi3_sign_extend.hi"
+ [(set (match_operand:PSI 0 "register_operand" "=r")
+ (plus:PSI (sign_extend:PSI (match_operand:HI 1 "register_operand" "r"))
+ (match_operand:PSI 2 "register_operand" "0")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"add %A0,%1\;adc %B0,%B1\;adc %C0,__zero_reg__\;sbrc %B1,7\;dec %C0"
- [(set_attr "length" "5")
- (set_attr "cc" "set_n")])
+ [(set_attr "length" "5")])
-(define_insn "*addsi3_zero_extend"
+(define_insn_and_split "*addsi3_zero_extend_split"
[(set (match_operand:SI 0 "register_operand" "=r")
(plus:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
(match_operand:SI 2 "register_operand" "0")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (plus:SI (zero_extend:SI (match_dup 1))
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*addsi3_zero_extend"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (plus:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
+ (match_operand:SI 2 "register_operand" "0")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"add %A0,%1\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__"
- [(set_attr "length" "4")
- (set_attr "cc" "set_n")])
+ [(set_attr "length" "4")])
-(define_insn "*addsi3_zero_extend.hi"
+(define_insn_and_split "*addsi3_zero_extend.hi_split"
[(set (match_operand:SI 0 "register_operand" "=r")
(plus:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
(match_operand:SI 2 "register_operand" "0")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (plus:SI (zero_extend:SI (match_dup 1))
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*addsi3_zero_extend.hi"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (plus:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
+ (match_operand:SI 2 "register_operand" "0")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"add %A0,%1\;adc %B0,%B1\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__"
- [(set_attr "length" "4")
- (set_attr "cc" "set_n")])
+ [(set_attr "length" "4")])
-(define_insn "addpsi3"
+(define_insn_and_split "addpsi3"
[(set (match_operand:PSI 0 "register_operand" "=??r,d ,d,r")
(plus:PSI (match_operand:PSI 1 "register_operand" "%0,0 ,0,0")
(match_operand:PSI 2 "nonmemory_operand" "r,s ,n,n")))
(clobber (match_scratch:QI 3 "=X,X ,X,&d"))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (plus:PSI (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_dup 3 ))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*addpsi3"
+ [(set (match_operand:PSI 0 "register_operand" "=??r,d ,d,r")
+ (plus:PSI (match_operand:PSI 1 "register_operand" "%0,0 ,0,0")
+ (match_operand:PSI 2 "nonmemory_operand" "r,s ,n,n")))
+ (clobber (match_scratch:QI 3 "=X,X ,X,&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return avr_out_plus (insn, operands);
}
[(set_attr "length" "3")
- (set_attr "adjust_len" "plus")
- (set_attr "cc" "plus")])
+ (set_attr "adjust_len" "plus")])
-(define_insn "subpsi3"
+(define_insn_and_split "subpsi3"
[(set (match_operand:PSI 0 "register_operand" "=r")
(minus:PSI (match_operand:PSI 1 "register_operand" "0")
(match_operand:PSI 2 "register_operand" "r")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (minus:PSI (match_dup 1)
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*subpsi3"
+ [(set (match_operand:PSI 0 "register_operand" "=r")
+ (minus:PSI (match_operand:PSI 1 "register_operand" "0")
+ (match_operand:PSI 2 "register_operand" "r")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"sub %0,%2\;sbc %B0,%B2\;sbc %C0,%C2"
- [(set_attr "length" "3")
- (set_attr "cc" "set_czn")])
+ [(set_attr "length" "3")])
-(define_insn "*subpsi3_zero_extend.qi"
+(define_insn_and_split "*subpsi3_zero_extend.qi_split"
[(set (match_operand:PSI 0 "register_operand" "=r")
(minus:PSI (match_operand:SI 1 "register_operand" "0")
(zero_extend:PSI (match_operand:QI 2 "register_operand" "r"))))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (minus:PSI (match_dup 1)
+ (zero_extend:PSI (match_dup 2))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*subpsi3_zero_extend.qi"
+ [(set (match_operand:PSI 0 "register_operand" "=r")
+ (minus:PSI (match_operand:SI 1 "register_operand" "0")
+ (zero_extend:PSI (match_operand:QI 2 "register_operand" "r"))))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"sub %A0,%2\;sbc %B0,__zero_reg__\;sbc %C0,__zero_reg__"
- [(set_attr "length" "3")
- (set_attr "cc" "set_czn")])
+ [(set_attr "length" "3")])
-(define_insn "*subpsi3_zero_extend.hi"
+(define_insn_and_split "*subpsi3_zero_extend.hi_split"
[(set (match_operand:PSI 0 "register_operand" "=r")
(minus:PSI (match_operand:PSI 1 "register_operand" "0")
(zero_extend:PSI (match_operand:HI 2 "register_operand" "r"))))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (minus:PSI (match_dup 1)
+ (zero_extend:PSI (match_dup 2))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*subpsi3_zero_extend.hi"
+ [(set (match_operand:PSI 0 "register_operand" "=r")
+ (minus:PSI (match_operand:PSI 1 "register_operand" "0")
+ (zero_extend:PSI (match_operand:HI 2 "register_operand" "r"))))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"sub %A0,%2\;sbc %B0,%B2\;sbc %C0,__zero_reg__"
- [(set_attr "length" "3")
- (set_attr "cc" "set_czn")])
+ [(set_attr "length" "3")])
-(define_insn "*subpsi3_sign_extend.hi"
+(define_insn_and_split "*subpsi3_sign_extend.hi_split"
[(set (match_operand:PSI 0 "register_operand" "=r")
(minus:PSI (match_operand:PSI 1 "register_operand" "0")
(sign_extend:PSI (match_operand:HI 2 "register_operand" "r"))))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (minus:PSI (match_dup 1)
+ (sign_extend:PSI (match_dup 2))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*subpsi3_sign_extend.hi"
+ [(set (match_operand:PSI 0 "register_operand" "=r")
+ (minus:PSI (match_operand:PSI 1 "register_operand" "0")
+ (sign_extend:PSI (match_operand:HI 2 "register_operand" "r"))))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"sub %A0,%A2\;sbc %B0,%B2\;sbc %C0,__zero_reg__\;sbrc %B2,7\;inc %C0"
- [(set_attr "length" "5")
- (set_attr "cc" "set_czn")])
+ [(set_attr "length" "5")])
;-----------------------------------------------------------------------------
; sub bytes
;; "subqi3"
;; "subqq3" "subuqq3"
-(define_insn "sub<mode>3"
+(define_insn_and_split "sub<mode>3"
[(set (match_operand:ALL1 0 "register_operand" "=??r,d ,r ,r ,r ,r")
(minus:ALL1 (match_operand:ALL1 1 "register_operand" "0,0 ,0 ,0 ,0 ,0")
(match_operand:ALL1 2 "nonmemory_or_const_operand" "r,n Ynn,Y01,Ym1,Y02,Ym2")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (minus:ALL1 (match_dup 1)
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*sub<mode>3"
+ [(set (match_operand:ALL1 0 "register_operand" "=??r,d ,r ,r ,r ,r")
+ (minus:ALL1 (match_operand:ALL1 1 "register_operand" "0,0 ,0 ,0 ,0 ,0")
+ (match_operand:ALL1 2 "nonmemory_or_const_operand" "r,n Ynn,Y01,Ym1,Y02,Ym2")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"@
sub %0,%2
subi %0,lo8(%2)
@@ -1470,78 +1939,155 @@
inc %0
dec %0\;dec %0
inc %0\;inc %0"
- [(set_attr "length" "1,1,1,1,2,2")
- (set_attr "cc" "set_czn,set_czn,set_vzn,set_vzn,set_vzn,set_vzn")])
+ [(set_attr "length" "1,1,1,1,2,2")])
;; "subhi3"
;; "subhq3" "subuhq3"
;; "subha3" "subuha3"
-(define_insn "sub<mode>3"
+(define_insn_and_split "sub<mode>3"
[(set (match_operand:ALL2 0 "register_operand" "=??r,d ,*r")
(minus:ALL2 (match_operand:ALL2 1 "register_operand" "0,0 ,0")
(match_operand:ALL2 2 "nonmemory_or_const_operand" "r,i Ynn,Ynn")))
(clobber (match_scratch:QI 3 "=X,X ,&d"))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (minus:ALL2 (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_dup 3))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*sub<mode>3"
+ [(set (match_operand:ALL2 0 "register_operand" "=??r,d ,*r")
+ (minus:ALL2 (match_operand:ALL2 1 "register_operand" "0,0 ,0")
+ (match_operand:ALL2 2 "nonmemory_or_const_operand" "r,i Ynn,Ynn")))
+ (clobber (match_scratch:QI 3 "=X,X ,&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return avr_out_plus (insn, operands);
}
- [(set_attr "adjust_len" "plus")
- (set_attr "cc" "plus")])
+ [(set_attr "adjust_len" "plus")])
-(define_insn "*subhi3_zero_extend1"
+(define_insn_and_split "*subhi3_zero_extend1_split"
[(set (match_operand:HI 0 "register_operand" "=r")
(minus:HI (match_operand:HI 1 "register_operand" "0")
(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (minus:HI (match_dup 1)
+ (zero_extend:HI (match_dup 2))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*subhi3_zero_extend1"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (minus:HI (match_operand:HI 1 "register_operand" "0")
+ (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"sub %A0,%2\;sbc %B0,__zero_reg__"
- [(set_attr "length" "2")
- (set_attr "cc" "set_czn")])
+ [(set_attr "length" "2")])
-(define_insn "*subhi3.sign_extend2"
+(define_insn_and_split "*subhi3.sign_extend2_split"
[(set (match_operand:HI 0 "register_operand" "=r")
(minus:HI (match_operand:HI 1 "register_operand" "0")
(sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (minus:HI (match_dup 1)
+ (sign_extend:HI (match_dup 2))))
+ (clobber (reg:CC REG_CC))])])
+
+
+(define_insn "*subhi3.sign_extend2"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (minus:HI (match_operand:HI 1 "register_operand" "0")
+ (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return reg_overlap_mentioned_p (operands[0], operands[2])
? "mov __tmp_reg__,%2\;sub %A0,%2\;sbc %B0,__zero_reg__\;sbrc __tmp_reg__,7\;inc %B0"
: "sub %A0,%2\;sbc %B0,__zero_reg__\;sbrc %2,7\;inc %B0";
}
- [(set_attr "length" "5")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "5")])
;; "subsi3"
;; "subsq3" "subusq3"
;; "subsa3" "subusa3"
-(define_insn "sub<mode>3"
+(define_insn_and_split "sub<mode>3"
[(set (match_operand:ALL4 0 "register_operand" "=??r,d ,r")
(minus:ALL4 (match_operand:ALL4 1 "register_operand" "0,0 ,0")
(match_operand:ALL4 2 "nonmemory_or_const_operand" "r,n Ynn,Ynn")))
(clobber (match_scratch:QI 3 "=X,X ,&d"))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (minus:ALL4 (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_dup 3))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*sub<mode>3"
+ [(set (match_operand:ALL4 0 "register_operand" "=??r,d ,r")
+ (minus:ALL4 (match_operand:ALL4 1 "register_operand" "0,0 ,0")
+ (match_operand:ALL4 2 "nonmemory_or_const_operand" "r,n Ynn,Ynn")))
+ (clobber (match_scratch:QI 3 "=X,X ,&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return avr_out_plus (insn, operands);
}
- [(set_attr "adjust_len" "plus")
- (set_attr "cc" "plus")])
+ [(set_attr "adjust_len" "plus")])
-(define_insn "*subsi3_zero_extend"
+(define_insn_and_split "*subsi3_zero_extend_split"
[(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (match_operand:SI 1 "register_operand" "0")
(zero_extend:SI (match_operand:QI 2 "register_operand" "r"))))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (minus:SI (match_dup 1)
+ (zero_extend:SI (match_dup 2))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*subsi3_zero_extend"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (minus:SI (match_operand:SI 1 "register_operand" "0")
+ (zero_extend:SI (match_operand:QI 2 "register_operand" "r"))))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"sub %A0,%2\;sbc %B0,__zero_reg__\;sbc %C0,__zero_reg__\;sbc %D0,__zero_reg__"
[(set_attr "length" "4")
- (set_attr "cc" "set_czn")])
+ ])
-(define_insn "*subsi3_zero_extend.hi"
+(define_insn_and_split "*subsi3_zero_extend.hi_split"
[(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (match_operand:SI 1 "register_operand" "0")
(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (minus:SI (match_dup 1)
+ (zero_extend:SI (match_dup 2))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*subsi3_zero_extend.hi"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (minus:SI (match_operand:SI 1 "register_operand" "0")
+ (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"sub %A0,%2\;sbc %B0,%B2\;sbc %C0,__zero_reg__\;sbc %D0,__zero_reg__"
- [(set_attr "length" "4")
- (set_attr "cc" "set_czn")])
+ [(set_attr "length" "4")])
;******************************************************************************
; mul
@@ -1559,16 +2105,28 @@
}
})
-(define_insn "*mulqi3_enh"
+(define_insn_and_split "*mulqi3_enh_split"
[(set (match_operand:QI 0 "register_operand" "=r")
(mult:QI (match_operand:QI 1 "register_operand" "r")
(match_operand:QI 2 "register_operand" "r")))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (mult:QI (match_dup 1)
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*mulqi3_enh"
+ [(set (match_operand:QI 0 "register_operand" "=r")
+ (mult:QI (match_operand:QI 1 "register_operand" "r")
+ (match_operand:QI 2 "register_operand" "r")))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"mul %1,%2
mov %0,r0
clr r1"
- [(set_attr "length" "3")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "3")])
(define_expand "mulqi3_call"
[(set (reg:QI 24) (match_operand:QI 1 "register_operand" ""))
@@ -1581,189 +2139,392 @@
avr_fix_inputs (operands, 1 << 2, regmask (QImode, 24));
})
-(define_insn "*mulqi3_call"
+(define_insn_and_split "*mulqi3_call_split"
[(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
(clobber (reg:QI 22))]
"!AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
+ (clobber (reg:QI 22))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*mulqi3_call"
+ [(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
+ (clobber (reg:QI 22))
+ (clobber (reg:CC REG_CC))]
+ "!AVR_HAVE_MUL && reload_completed"
"%~call __mulqi3"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;; "umulqi3_highpart"
;; "smulqi3_highpart"
-(define_insn "<extend_su>mulqi3_highpart"
+
+(define_insn_and_split "<extend_su>mulqi3_highpart"
[(set (match_operand:QI 0 "register_operand" "=r")
(truncate:QI
(lshiftrt:HI (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
(any_extend:HI (match_operand:QI 2 "register_operand" "<mul_r_d>")))
(const_int 8))))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (truncate:QI
+ (lshiftrt:HI (mult:HI (any_extend:HI (match_dup 1))
+ (any_extend:HI (match_dup 2)))
+ (const_int 8))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*<extend_su>mulqi3_highpart"
+ [(set (match_operand:QI 0 "register_operand" "=r")
+ (truncate:QI
+ (lshiftrt:HI (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
+ (any_extend:HI (match_operand:QI 2 "register_operand" "<mul_r_d>")))
+ (const_int 8))))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"mul<extend_s> %1,%2
mov %0,r1
clr __zero_reg__"
- [(set_attr "length" "3")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "3")])
;; Used when expanding div or mod inline for some special values
-(define_insn "*subqi3.ashiftrt7"
+(define_insn_and_split "*subqi3.ashiftrt7_split"
[(set (match_operand:QI 0 "register_operand" "=r")
(minus:QI (match_operand:QI 1 "register_operand" "0")
(ashiftrt:QI (match_operand:QI 2 "register_operand" "r")
(const_int 7))))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (minus:QI (match_dup 1)
+ (ashiftrt:QI (match_dup 2)
+ (const_int 7))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*subqi3.ashiftrt7"
+ [(set (match_operand:QI 0 "register_operand" "=r")
+ (minus:QI (match_operand:QI 1 "register_operand" "0")
+ (ashiftrt:QI (match_operand:QI 2 "register_operand" "r")
+ (const_int 7))))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"sbrc %2,7\;inc %0"
- [(set_attr "length" "2")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "2")])
-(define_insn "*addqi3.lt0"
+(define_insn_and_split "*addqi3.lt0_split"
[(set (match_operand:QI 0 "register_operand" "=r")
(plus:QI (lt:QI (match_operand:QI 1 "register_operand" "r")
(const_int 0))
(match_operand:QI 2 "register_operand" "0")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (plus:QI (lt:QI (match_dup 1)
+ (const_int 0))
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*addqi3.lt0"
+ [(set (match_operand:QI 0 "register_operand" "=r")
+ (plus:QI (lt:QI (match_operand:QI 1 "register_operand" "r")
+ (const_int 0))
+ (match_operand:QI 2 "register_operand" "0")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"sbrc %1,7\;inc %0"
- [(set_attr "length" "2")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "2")])
-(define_insn "*addhi3.lt0"
+(define_insn_and_split "*addhi3.lt0_split"
[(set (match_operand:HI 0 "register_operand" "=w,r")
(plus:HI (lt:HI (match_operand:QI 1 "register_operand" "r,r")
(const_int 0))
(match_operand:HI 2 "register_operand" "0,0")))
(clobber (match_scratch:QI 3 "=X,&1"))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (plus:HI (lt:HI (match_dup 1)
+ (const_int 0))
+ (match_dup 2)))
+ (clobber (match_dup 3))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*addhi3.lt0"
+ [(set (match_operand:HI 0 "register_operand" "=w,r")
+ (plus:HI (lt:HI (match_operand:QI 1 "register_operand" "r,r")
+ (const_int 0))
+ (match_operand:HI 2 "register_operand" "0,0")))
+ (clobber (match_scratch:QI 3 "=X,&1"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"@
sbrc %1,7\;adiw %0,1
lsl %1\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__"
- [(set_attr "length" "2,3")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "2,3")])
-(define_insn "*addpsi3.lt0"
+(define_insn_and_split "*addpsi3.lt0_split"
[(set (match_operand:PSI 0 "register_operand" "=r")
(plus:PSI (lshiftrt:PSI (match_operand:PSI 1 "register_operand" "r")
(const_int 23))
(match_operand:PSI 2 "register_operand" "0")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (plus:PSI (lshiftrt:PSI (match_dup 1)
+ (const_int 23))
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*addpsi3.lt0"
+ [(set (match_operand:PSI 0 "register_operand" "=r")
+ (plus:PSI (lshiftrt:PSI (match_operand:PSI 1 "register_operand" "r")
+ (const_int 23))
+ (match_operand:PSI 2 "register_operand" "0")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"mov __tmp_reg__,%C1\;lsl __tmp_reg__
adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__"
- [(set_attr "length" "5")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "5")])
-(define_insn "*addsi3.lt0"
+(define_insn_and_split "*addsi3.lt0_split"
[(set (match_operand:SI 0 "register_operand" "=r")
(plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
(const_int 31))
(match_operand:SI 2 "register_operand" "0")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (plus:SI (lshiftrt:SI (match_dup 1)
+ (const_int 31))
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*addsi3.lt0"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (plus:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
+ (const_int 31))
+ (match_operand:SI 2 "register_operand" "0")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"mov __tmp_reg__,%D1\;lsl __tmp_reg__
adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__"
- [(set_attr "length" "6")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "6")])
-(define_insn "*umulqihi3.call"
+(define_insn_and_split "*umulqihi3.call_split"
[(set (reg:HI 24)
(mult:HI (zero_extend:HI (reg:QI 22))
(zero_extend:HI (reg:QI 24))))
(clobber (reg:QI 21))
(clobber (reg:HI 22))]
"!AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:HI 24)
+ (mult:HI (zero_extend:HI (reg:QI 22))
+ (zero_extend:HI (reg:QI 24))))
+ (clobber (reg:QI 21))
+ (clobber (reg:HI 22))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*umulqihi3.call"
+ [(set (reg:HI 24)
+ (mult:HI (zero_extend:HI (reg:QI 22))
+ (zero_extend:HI (reg:QI 24))))
+ (clobber (reg:QI 21))
+ (clobber (reg:HI 22))
+ (clobber (reg:CC REG_CC))]
+ "!AVR_HAVE_MUL && reload_completed"
"%~call __umulqihi3"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;; "umulqihi3"
;; "mulqihi3"
-(define_insn "<extend_u>mulqihi3"
+
+(define_insn_and_split "<extend_u>mulqihi3_split"
[(set (match_operand:HI 0 "register_operand" "=r")
(mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
(any_extend:HI (match_operand:QI 2 "register_operand" "<mul_r_d>"))))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (mult:HI (any_extend:HI (match_dup 1))
+ (any_extend:HI (match_dup 2))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "<extend_u>mulqihi3"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
+ (any_extend:HI (match_operand:QI 2 "register_operand" "<mul_r_d>"))))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"mul<extend_s> %1,%2
movw %0,r0
clr __zero_reg__"
- [(set_attr "length" "3")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "3")])
-(define_insn "usmulqihi3"
+(define_insn_and_split "usmulqihi3"
[(set (match_operand:HI 0 "register_operand" "=r")
(mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "a"))
(sign_extend:HI (match_operand:QI 2 "register_operand" "a"))))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (mult:HI (zero_extend:HI (match_dup 1))
+ (sign_extend:HI (match_dup 2))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*usmulqihi3"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "a"))
+ (sign_extend:HI (match_operand:QI 2 "register_operand" "a"))))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"mulsu %2,%1
movw %0,r0
clr __zero_reg__"
- [(set_attr "length" "3")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "3")])
;; Above insn is not canonicalized by insn combine, so here is a version with
;; operands swapped.
-
-(define_insn "*sumulqihi3"
+(define_insn_and_split "*sumulqihi3_split"
[(set (match_operand:HI 0 "register_operand" "=r")
(mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "a"))
(zero_extend:HI (match_operand:QI 2 "register_operand" "a"))))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (mult:HI (sign_extend:HI (match_dup 1))
+ (zero_extend:HI (match_dup 2))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*sumulqihi3"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "a"))
+ (zero_extend:HI (match_operand:QI 2 "register_operand" "a"))))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"mulsu %1,%2
movw %0,r0
clr __zero_reg__"
- [(set_attr "length" "3")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "3")])
;; One-extend operand 1
-(define_insn "*osmulqihi3"
+(define_insn_and_split "*osmulqihi3_split"
[(set (match_operand:HI 0 "register_operand" "=&r")
(mult:HI (not:HI (zero_extend:HI (not:QI (match_operand:QI 1 "register_operand" "a"))))
(sign_extend:HI (match_operand:QI 2 "register_operand" "a"))))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (mult:HI (not:HI (zero_extend:HI (not:QI (match_dup 1))))
+ (sign_extend:HI (match_dup 2))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*osmulqihi3"
+ [(set (match_operand:HI 0 "register_operand" "=&r")
+ (mult:HI (not:HI (zero_extend:HI (not:QI (match_operand:QI 1 "register_operand" "a"))))
+ (sign_extend:HI (match_operand:QI 2 "register_operand" "a"))))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"mulsu %2,%1
movw %0,r0
sub %B0,%2
clr __zero_reg__"
- [(set_attr "length" "4")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "4")])
-(define_insn "*oumulqihi3"
+(define_insn_and_split "*oumulqihi3_split"
[(set (match_operand:HI 0 "register_operand" "=&r")
(mult:HI (not:HI (zero_extend:HI (not:QI (match_operand:QI 1 "register_operand" "r"))))
(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (mult:HI (not:HI (zero_extend:HI (not:QI (match_dup 1))))
+ (zero_extend:HI (match_dup 2))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*oumulqihi3"
+ [(set (match_operand:HI 0 "register_operand" "=&r")
+ (mult:HI (not:HI (zero_extend:HI (not:QI (match_operand:QI 1 "register_operand" "r"))))
+ (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"mul %2,%1
movw %0,r0
sub %B0,%2
clr __zero_reg__"
- [(set_attr "length" "4")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "4")])
;******************************************************************************
; multiply-add/sub QI: $0 = $3 +/- $1*$2
;******************************************************************************
-(define_insn "*maddqi4"
+(define_insn_and_split "*maddqi4_split"
[(set (match_operand:QI 0 "register_operand" "=r")
(plus:QI (mult:QI (match_operand:QI 1 "register_operand" "r")
(match_operand:QI 2 "register_operand" "r"))
(match_operand:QI 3 "register_operand" "0")))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (plus:QI (mult:QI (match_dup 1)
+ (match_dup 2))
+ (match_dup 3)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*maddqi4"
+ [(set (match_operand:QI 0 "register_operand" "=r")
+ (plus:QI (mult:QI (match_operand:QI 1 "register_operand" "r")
+ (match_operand:QI 2 "register_operand" "r"))
+ (match_operand:QI 3 "register_operand" "0")))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"mul %1,%2
add %A0,r0
clr __zero_reg__"
- [(set_attr "length" "4")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "4")])
-(define_insn "*msubqi4"
+(define_insn_and_split "*msubqi4_split"
[(set (match_operand:QI 0 "register_operand" "=r")
(minus:QI (match_operand:QI 3 "register_operand" "0")
(mult:QI (match_operand:QI 1 "register_operand" "r")
(match_operand:QI 2 "register_operand" "r"))))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (minus:QI (match_dup 3)
+ (mult:QI (match_dup 1)
+ (match_dup 2))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*msubqi4"
+ [(set (match_operand:QI 0 "register_operand" "=r")
+ (minus:QI (match_operand:QI 3 "register_operand" "0")
+ (mult:QI (match_operand:QI 1 "register_operand" "r")
+ (match_operand:QI 2 "register_operand" "r"))))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"mul %1,%2
sub %A0,r0
clr __zero_reg__"
- [(set_attr "length" "4")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "4")])
(define_insn_and_split "*maddqi4.const"
[(set (match_operand:QI 0 "register_operand" "=r")
@@ -1821,38 +2582,66 @@
;; "*maddqihi4"
;; "*umaddqihi4"
-(define_insn "*<extend_u>maddqihi4"
+(define_insn_and_split "*<extend_u>maddqihi4_split"
[(set (match_operand:HI 0 "register_operand" "=r")
(plus:HI (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
(any_extend:HI (match_operand:QI 2 "register_operand" "<mul_r_d>")))
(match_operand:HI 3 "register_operand" "0")))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (plus:HI (mult:HI (any_extend:HI (match_dup 1))
+ (any_extend:HI (match_dup 2)))
+ (match_dup 3)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*<extend_u>maddqihi4"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (plus:HI (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
+ (any_extend:HI (match_operand:QI 2 "register_operand" "<mul_r_d>")))
+ (match_operand:HI 3 "register_operand" "0")))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"mul<extend_s> %1,%2
add %A0,r0
adc %B0,r1
clr __zero_reg__"
- [(set_attr "length" "4")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "4")])
;; "*msubqihi4"
;; "*umsubqihi4"
-(define_insn "*<extend_u>msubqihi4"
+(define_insn_and_split "*<extend_u>msubqihi4_split"
[(set (match_operand:HI 0 "register_operand" "=r")
(minus:HI (match_operand:HI 3 "register_operand" "0")
(mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
(any_extend:HI (match_operand:QI 2 "register_operand" "<mul_r_d>")))))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (minus:HI (match_dup 3)
+ (mult:HI (any_extend:HI (match_dup 1))
+ (any_extend:HI (match_dup 2)))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*<extend_u>msubqihi4"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (minus:HI (match_operand:HI 3 "register_operand" "0")
+ (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "<mul_r_d>"))
+ (any_extend:HI (match_operand:QI 2 "register_operand" "<mul_r_d>")))))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"mul<extend_s> %1,%2
sub %A0,r0
sbc %B0,r1
clr __zero_reg__"
- [(set_attr "length" "4")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "4")])
;; "*usmaddqihi4"
;; "*sumaddqihi4"
-(define_insn "*<any_extend:extend_su><any_extend2:extend_su>msubqihi4"
+(define_insn_and_split "*<any_extend:extend_su><any_extend2:extend_su>msubqihi4_split"
[(set (match_operand:HI 0 "register_operand" "=r")
(plus:HI (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "a"))
(any_extend2:HI (match_operand:QI 2 "register_operand" "a")))
@@ -1860,18 +2649,34 @@
"AVR_HAVE_MUL
&& reload_completed
&& <any_extend:CODE> != <any_extend2:CODE>"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (plus:HI (mult:HI (any_extend:HI (match_dup 1))
+ (any_extend2:HI (match_dup 2)))
+ (match_dup 3)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*<any_extend:extend_su><any_extend2:extend_su>msubqihi4"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (plus:HI (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "a"))
+ (any_extend2:HI (match_operand:QI 2 "register_operand" "a")))
+ (match_operand:HI 3 "register_operand" "0")))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL
+ && reload_completed
+ && <any_extend:CODE> != <any_extend2:CODE>"
{
output_asm_insn (<any_extend:CODE> == SIGN_EXTEND
? "mulsu %1,%2" : "mulsu %2,%1", operands);
return "add %A0,r0\;adc %B0,r1\;clr __zero_reg__";
}
- [(set_attr "length" "4")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "4")])
;; "*usmsubqihi4"
;; "*sumsubqihi4"
-(define_insn "*<any_extend:extend_su><any_extend2:extend_su>msubqihi4"
+(define_insn_and_split "*<any_extend:extend_su><any_extend2:extend_su>msubqihi4_split"
[(set (match_operand:HI 0 "register_operand" "=r")
(minus:HI (match_operand:HI 3 "register_operand" "0")
(mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "a"))
@@ -1879,14 +2684,30 @@
"AVR_HAVE_MUL
&& reload_completed
&& <any_extend:CODE> != <any_extend2:CODE>"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (minus:HI (match_dup 3)
+ (mult:HI (any_extend:HI (match_dup 1))
+ (any_extend2:HI (match_dup 2)))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*<any_extend:extend_su><any_extend2:extend_su>msubqihi4"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (minus:HI (match_operand:HI 3 "register_operand" "0")
+ (mult:HI (any_extend:HI (match_operand:QI 1 "register_operand" "a"))
+ (any_extend2:HI (match_operand:QI 2 "register_operand" "a")))))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL
+ && reload_completed
+ && <any_extend:CODE> != <any_extend2:CODE>"
{
output_asm_insn (<any_extend:CODE> == SIGN_EXTEND
? "mulsu %1,%2" : "mulsu %2,%1", operands);
return "sub %A0,r0\;sbc %B0,r1\;clr __zero_reg__";
}
- [(set_attr "length" "4")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "4")])
;; Handle small constants
@@ -2130,17 +2951,28 @@
;; The EXTEND of $1 only appears in combine, we don't see it in expand so that
;; expand decides to use ASHIFT instead of MUL because ASHIFT costs are cheaper
;; at that time. Fix that.
-
-(define_insn "*ashiftqihi2.signx.1"
+(define_insn_and_split "*ashiftqihi2.signx.1_split"
[(set (match_operand:HI 0 "register_operand" "=r,*r")
(ashift:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "0,r"))
(const_int 1)))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (ashift:HI (sign_extend:HI (match_dup 1))
+ (const_int 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*ashiftqihi2.signx.1"
+ [(set (match_operand:HI 0 "register_operand" "=r,*r")
+ (ashift:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "0,r"))
+ (const_int 1)))
+ (clobber (reg:CC REG_CC)) ]
+ "reload_completed"
"@
lsl %A0\;sbc %B0,%B0
mov %A0,%1\;lsl %A0\;sbc %B0,%B0"
- [(set_attr "length" "2,3")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "2,3")])
(define_insn_and_split "*ashifthi3.signx.const"
[(set (match_operand:HI 0 "register_operand" "=r")
@@ -2200,47 +3032,83 @@
; mul HI: $1 = sign-/zero-/one-extend, $2 = reg
;******************************************************************************
-(define_insn "mulsqihi3"
+(define_insn_and_split "mulsqihi3"
[(set (match_operand:HI 0 "register_operand" "=&r")
(mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "a"))
(match_operand:HI 2 "register_operand" "a")))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (mult:HI (sign_extend:HI (match_dup 1))
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*mulsqihi3"
+ [(set (match_operand:HI 0 "register_operand" "=&r")
+ (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "a"))
+ (match_operand:HI 2 "register_operand" "a")))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"mulsu %1,%A2
movw %0,r0
mul %1,%B2
add %B0,r0
clr __zero_reg__"
- [(set_attr "length" "5")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "5")])
-(define_insn "muluqihi3"
+(define_insn_and_split "muluqihi3"
[(set (match_operand:HI 0 "register_operand" "=&r")
(mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
(match_operand:HI 2 "register_operand" "r")))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (mult:HI (zero_extend:HI (match_dup 1))
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*muluqihi3"
+ [(set (match_operand:HI 0 "register_operand" "=&r")
+ (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
+ (match_operand:HI 2 "register_operand" "r")))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"mul %1,%A2
movw %0,r0
mul %1,%B2
add %B0,r0
clr __zero_reg__"
- [(set_attr "length" "5")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "5")])
;; one-extend operand 1
-(define_insn "muloqihi3"
+(define_insn_and_split "muloqihi3"
[(set (match_operand:HI 0 "register_operand" "=&r")
(mult:HI (not:HI (zero_extend:HI (not:QI (match_operand:QI 1 "register_operand" "r"))))
(match_operand:HI 2 "register_operand" "r")))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (mult:HI (not:HI (zero_extend:HI (not:QI (match_dup 1))))
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*muloqihi3"
+ [(set (match_operand:HI 0 "register_operand" "=&r")
+ (mult:HI (not:HI (zero_extend:HI (not:QI (match_operand:QI 1 "register_operand" "r"))))
+ (match_operand:HI 2 "register_operand" "r")))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"mul %1,%A2
movw %0,r0
mul %1,%B2
add %B0,r0
sub %B0,%A2
clr __zero_reg__"
- [(set_attr "length" "6")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "6")])
;******************************************************************************
@@ -2288,18 +3156,30 @@
operands[2] = force_reg (HImode, operands[2]);
})
-(define_insn "*mulhi3_enh"
+(define_insn_and_split "*mulhi3_enh_split"
[(set (match_operand:HI 0 "register_operand" "=&r")
(mult:HI (match_operand:HI 1 "register_operand" "r")
(match_operand:HI 2 "register_operand" "r")))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (mult:HI (match_dup 1)
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*mulhi3_enh"
+ [(set (match_operand:HI 0 "register_operand" "=&r")
+ (mult:HI (match_operand:HI 1 "register_operand" "r")
+ (match_operand:HI 2 "register_operand" "r")))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
{
return REGNO (operands[1]) == REGNO (operands[2])
? "mul %A1,%A1\;movw %0,r0\;mul %A1,%B1\;add %B0,r0\;add %B0,r0\;clr r1"
: "mul %A1,%A2\;movw %0,r0\;mul %A1,%B2\;add %B0,r0\;mul %B1,%A2\;add %B0,r0\;clr r1";
}
- [(set_attr "length" "7")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "7")])
(define_expand "mulhi3_call"
[(set (reg:HI 24) (match_operand:HI 1 "register_operand" ""))
@@ -2315,14 +3195,26 @@
})
-(define_insn "*mulhi3_call"
+(define_insn_and_split "*mulhi3_call_split"
[(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
(clobber (reg:HI 22))
(clobber (reg:QI 21))]
"!AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
+ (clobber (reg:HI 22))
+ (clobber (reg:QI 21))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*mulhi3_call"
+ [(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
+ (clobber (reg:HI 22))
+ (clobber (reg:QI 21))
+ (clobber (reg:CC REG_CC))]
+ "!AVR_HAVE_MUL && reload_completed"
"%~call __mulhi3"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;; To support widening multiplication with constant we postpone
;; expanding to the implicit library call until post combine and
@@ -2643,67 +3535,144 @@
avr_fix_inputs (operands, 1 << 2, regmask (HImode, 18));
})
-
-(define_insn "*mulsi3_call"
+(define_insn_and_split "*mulsi3_call_split"
[(set (reg:SI 22)
(mult:SI (reg:SI 22)
(reg:SI 18)))
(clobber (reg:HI 26))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:SI 22)
+ (mult:SI (reg:SI 22)
+ (reg:SI 18)))
+ (clobber (reg:HI 26))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*mulsi3_call"
+ [(set (reg:SI 22)
+ (mult:SI (reg:SI 22)
+ (reg:SI 18)))
+ (clobber (reg:HI 26))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"%~call __mulsi3"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;; "*mulhisi3_call"
;; "*umulhisi3_call"
-(define_insn "*<extend_u>mulhisi3_call"
+(define_insn_and_split "*<extend_u>mulhisi3_call_split"
[(set (reg:SI 22)
(mult:SI (any_extend:SI (reg:HI 18))
(any_extend:SI (reg:HI 26))))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:SI 22)
+ (mult:SI (any_extend:SI (reg:HI 18))
+ (any_extend:SI (reg:HI 26))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*<extend_u>mulhisi3_call"
+ [(set (reg:SI 22)
+ (mult:SI (any_extend:SI (reg:HI 18))
+ (any_extend:SI (reg:HI 26))))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"%~call __<extend_u>mulhisi3"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;; "*umulhi3_highpart_call"
;; "*smulhi3_highpart_call"
-(define_insn "*<extend_su>mulhi3_highpart_call"
+(define_insn_and_split "*<extend_su>mulhi3_highpart_call_split"
[(set (reg:HI 24)
(truncate:HI (lshiftrt:SI (mult:SI (any_extend:SI (reg:HI 18))
(any_extend:SI (reg:HI 26)))
(const_int 16))))
(clobber (reg:HI 22))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:HI 24)
+ (truncate:HI (lshiftrt:SI (mult:SI (any_extend:SI (reg:HI 18))
+ (any_extend:SI (reg:HI 26)))
+ (const_int 16))))
+ (clobber (reg:HI 22))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*<extend_su>mulhi3_highpart_call"
+ [(set (reg:HI 24)
+ (truncate:HI (lshiftrt:SI (mult:SI (any_extend:SI (reg:HI 18))
+ (any_extend:SI (reg:HI 26)))
+ (const_int 16))))
+ (clobber (reg:HI 22))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"%~call __<extend_u>mulhisi3"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
-(define_insn "*usmulhisi3_call"
+(define_insn_and_split "*usmulhisi3_call_split"
[(set (reg:SI 22)
(mult:SI (zero_extend:SI (reg:HI 18))
(sign_extend:SI (reg:HI 26))))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:SI 22)
+ (mult:SI (zero_extend:SI (reg:HI 18))
+ (sign_extend:SI (reg:HI 26))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*usmulhisi3_call"
+ [(set (reg:SI 22)
+ (mult:SI (zero_extend:SI (reg:HI 18))
+ (sign_extend:SI (reg:HI 26))))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"%~call __usmulhisi3"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
-(define_insn "*mul<extend_su>hisi3_call"
+(define_insn_and_split "*mul<extend_su>hisi3_call_split"
[(set (reg:SI 22)
(mult:SI (any_extend:SI (reg:HI 26))
(reg:SI 18)))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:SI 22)
+ (mult:SI (any_extend:SI (reg:HI 26))
+ (reg:SI 18)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*mul<extend_su>hisi3_call"
+ [(set (reg:SI 22)
+ (mult:SI (any_extend:SI (reg:HI 26))
+ (reg:SI 18)))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"%~call __mul<extend_su>hisi3"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
-(define_insn "*mulohisi3_call"
+(define_insn_and_split "*mulohisi3_call_split"
[(set (reg:SI 22)
(mult:SI (not:SI (zero_extend:SI (not:HI (reg:HI 26))))
(reg:SI 18)))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:SI 22)
+ (mult:SI (not:SI (zero_extend:SI (not:HI (reg:HI 26))))
+ (reg:SI 18)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*mulohisi3_call"
+ [(set (reg:SI 22)
+ (mult:SI (not:SI (zero_extend:SI (not:HI (reg:HI 26))))
+ (reg:SI 18)))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"%~call __mulohisi3"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
; / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / %
; divmod
@@ -2716,15 +3685,15 @@
;; CSE has problems to operate on hard regs.
;;
(define_insn_and_split "divmodqi4"
- [(parallel [(set (match_operand:QI 0 "pseudo_register_operand" "")
- (div:QI (match_operand:QI 1 "pseudo_register_operand" "")
- (match_operand:QI 2 "pseudo_register_operand" "")))
- (set (match_operand:QI 3 "pseudo_register_operand" "")
- (mod:QI (match_dup 1) (match_dup 2)))
- (clobber (reg:QI 22))
- (clobber (reg:QI 23))
- (clobber (reg:QI 24))
- (clobber (reg:QI 25))])]
+ [(set (match_operand:QI 0 "pseudo_register_operand" "")
+ (div:QI (match_operand:QI 1 "pseudo_register_operand" "")
+ (match_operand:QI 2 "pseudo_register_operand" "")))
+ (set (match_operand:QI 3 "pseudo_register_operand" "")
+ (mod:QI (match_dup 1) (match_dup 2)))
+ (clobber (reg:QI 22))
+ (clobber (reg:QI 23))
+ (clobber (reg:QI 24))
+ (clobber (reg:QI 25))]
""
"this divmodqi4 pattern should have been splitted;"
""
@@ -2737,26 +3706,40 @@
(set (match_dup 0) (reg:QI 24))
(set (match_dup 3) (reg:QI 25))])
-(define_insn "*divmodqi4_call"
+(define_insn_and_split "*divmodqi4_call_split"
[(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
(set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
(clobber (reg:QI 22))
(clobber (reg:QI 23))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
+ (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
+ (clobber (reg:QI 22))
+ (clobber (reg:QI 23))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*divmodqi4_call"
+ [(set (reg:QI 24) (div:QI (reg:QI 24) (reg:QI 22)))
+ (set (reg:QI 25) (mod:QI (reg:QI 24) (reg:QI 22)))
+ (clobber (reg:QI 22))
+ (clobber (reg:QI 23))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __divmodqi4"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
(define_insn_and_split "udivmodqi4"
- [(parallel [(set (match_operand:QI 0 "pseudo_register_operand" "")
- (udiv:QI (match_operand:QI 1 "pseudo_register_operand" "")
- (match_operand:QI 2 "pseudo_register_operand" "")))
- (set (match_operand:QI 3 "pseudo_register_operand" "")
- (umod:QI (match_dup 1) (match_dup 2)))
- (clobber (reg:QI 22))
- (clobber (reg:QI 23))
- (clobber (reg:QI 24))
- (clobber (reg:QI 25))])]
+ [(set (match_operand:QI 0 "pseudo_register_operand" "")
+ (udiv:QI (match_operand:QI 1 "pseudo_register_operand" "")
+ (match_operand:QI 2 "pseudo_register_operand" "")))
+ (set (match_operand:QI 3 "pseudo_register_operand" "")
+ (umod:QI (match_dup 1) (match_dup 2)))
+ (clobber (reg:QI 22))
+ (clobber (reg:QI 23))
+ (clobber (reg:QI 24))
+ (clobber (reg:QI 25))]
""
"this udivmodqi4 pattern should have been splitted;"
""
@@ -2768,25 +3751,37 @@
(set (match_dup 0) (reg:QI 24))
(set (match_dup 3) (reg:QI 25))])
-(define_insn "*udivmodqi4_call"
+(define_insn_and_split "*udivmodqi4_call_split"
[(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
(set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
(clobber (reg:QI 23))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
+ (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
+ (clobber (reg:QI 23))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*udivmodqi4_call"
+ [(set (reg:QI 24) (udiv:QI (reg:QI 24) (reg:QI 22)))
+ (set (reg:QI 25) (umod:QI (reg:QI 24) (reg:QI 22)))
+ (clobber (reg:QI 23))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __udivmodqi4"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
(define_insn_and_split "divmodhi4"
- [(parallel [(set (match_operand:HI 0 "pseudo_register_operand" "")
- (div:HI (match_operand:HI 1 "pseudo_register_operand" "")
- (match_operand:HI 2 "pseudo_register_operand" "")))
- (set (match_operand:HI 3 "pseudo_register_operand" "")
- (mod:HI (match_dup 1) (match_dup 2)))
- (clobber (reg:QI 21))
- (clobber (reg:HI 22))
- (clobber (reg:HI 24))
- (clobber (reg:HI 26))])]
+ [(set (match_operand:HI 0 "pseudo_register_operand" "")
+ (div:HI (match_operand:HI 1 "pseudo_register_operand" "")
+ (match_operand:HI 2 "pseudo_register_operand" "")))
+ (set (match_operand:HI 3 "pseudo_register_operand" "")
+ (mod:HI (match_dup 1) (match_dup 2)))
+ (clobber (reg:QI 21))
+ (clobber (reg:HI 22))
+ (clobber (reg:HI 24))
+ (clobber (reg:HI 26))]
""
"this should have been splitted;"
""
@@ -2799,26 +3794,40 @@
(set (match_dup 0) (reg:HI 22))
(set (match_dup 3) (reg:HI 24))])
-(define_insn "*divmodhi4_call"
+(define_insn_and_split "*divmodhi4_call_split"
[(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
(set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
(clobber (reg:HI 26))
(clobber (reg:QI 21))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
+ (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
+ (clobber (reg:HI 26))
+ (clobber (reg:QI 21))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*divmodhi4_call"
+ [(set (reg:HI 22) (div:HI (reg:HI 24) (reg:HI 22)))
+ (set (reg:HI 24) (mod:HI (reg:HI 24) (reg:HI 22)))
+ (clobber (reg:HI 26))
+ (clobber (reg:QI 21))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __divmodhi4"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
(define_insn_and_split "udivmodhi4"
- [(parallel [(set (match_operand:HI 0 "pseudo_register_operand" "")
- (udiv:HI (match_operand:HI 1 "pseudo_register_operand" "")
- (match_operand:HI 2 "pseudo_register_operand" "")))
- (set (match_operand:HI 3 "pseudo_register_operand" "")
- (umod:HI (match_dup 1) (match_dup 2)))
- (clobber (reg:QI 21))
- (clobber (reg:HI 22))
- (clobber (reg:HI 24))
- (clobber (reg:HI 26))])]
+ [(set (match_operand:HI 0 "pseudo_register_operand" "")
+ (udiv:HI (match_operand:HI 1 "pseudo_register_operand" "")
+ (match_operand:HI 2 "pseudo_register_operand" "")))
+ (set (match_operand:HI 3 "pseudo_register_operand" "")
+ (umod:HI (match_dup 1) (match_dup 2)))
+ (clobber (reg:QI 21))
+ (clobber (reg:HI 22))
+ (clobber (reg:HI 24))
+ (clobber (reg:HI 26))]
""
"this udivmodhi4 pattern should have been splitted.;"
""
@@ -2831,15 +3840,30 @@
(set (match_dup 0) (reg:HI 22))
(set (match_dup 3) (reg:HI 24))])
-(define_insn "*udivmodhi4_call"
+(define_insn_and_split "*udivmodhi4_call_split"
[(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
(set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
(clobber (reg:HI 26))
(clobber (reg:QI 21))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
+ (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
+ (clobber (reg:HI 26))
+ (clobber (reg:QI 21))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*udivmodhi4_call"
+ [(set (reg:HI 22) (udiv:HI (reg:HI 24) (reg:HI 22)))
+ (set (reg:HI 24) (umod:HI (reg:HI 24) (reg:HI 22)))
+ (clobber (reg:HI 26))
+ (clobber (reg:QI 21))
+ (clobber (reg:CC REG_CC))
+ ]
+ "reload_completed"
"%~call __udivmodhi4"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; 24-bit multiply
@@ -2870,11 +3894,24 @@
DONE;
})
-(define_insn "*umulqihipsi3"
+(define_insn_and_split "*umulqihipsi3_split"
[(set (match_operand:PSI 0 "register_operand" "=&r")
(mult:PSI (zero_extend:PSI (match_operand:QI 1 "register_operand" "r"))
(zero_extend:PSI (match_operand:HI 2 "register_operand" "r"))))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (mult:PSI (zero_extend:PSI (match_dup 1))
+ (zero_extend:PSI (match_dup 2))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*umulqihipsi3"
+ [(set (match_operand:PSI 0 "register_operand" "=&r")
+ (mult:PSI (zero_extend:PSI (match_operand:QI 1 "register_operand" "r"))
+ (zero_extend:PSI (match_operand:HI 2 "register_operand" "r"))))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"mul %1,%A2
movw %A0,r0
mul %1,%B2
@@ -2882,14 +3919,26 @@
add %B0,r0
adc %C0,r1
clr __zero_reg__"
- [(set_attr "length" "7")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "7")])
-(define_insn "*umulhiqipsi3"
+(define_insn_and_split "*umulhiqipsi3_split"
[(set (match_operand:PSI 0 "register_operand" "=&r")
(mult:PSI (zero_extend:PSI (match_operand:HI 2 "register_operand" "r"))
(zero_extend:PSI (match_operand:QI 1 "register_operand" "r"))))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (mult:PSI (zero_extend:PSI (match_dup 2))
+ (zero_extend:PSI (match_dup 1))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*umulhiqipsi3"
+ [(set (match_operand:PSI 0 "register_operand" "=&r")
+ (mult:PSI (zero_extend:PSI (match_operand:HI 2 "register_operand" "r"))
+ (zero_extend:PSI (match_operand:QI 1 "register_operand" "r"))))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"mul %1,%A2
movw %A0,r0
mul %1,%B2
@@ -2897,8 +3946,7 @@
mov %C0,r1
clr __zero_reg__
adc %C0,__zero_reg__"
- [(set_attr "length" "7")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "7")])
(define_expand "mulsqipsi3"
[(parallel [(set (match_operand:PSI 0 "pseudo_register_operand" "")
@@ -2963,16 +4011,28 @@
}
})
-(define_insn "*mulsqipsi3.libgcc"
+(define_insn_and_split "*mulsqipsi3.libgcc_split"
[(set (reg:PSI 18)
(mult:PSI (sign_extend:PSI (reg:QI 25))
(reg:PSI 22)))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:PSI 18)
+ (mult:PSI (sign_extend:PSI (reg:QI 25))
+ (reg:PSI 22)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*mulsqipsi3.libgcc"
+ [(set (reg:PSI 18)
+ (mult:PSI (sign_extend:PSI (reg:QI 25))
+ (reg:PSI 22)))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"%~call __mulsqipsi3"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
-(define_insn "*mulpsi3.libgcc"
+(define_insn_and_split "*mulpsi3.libgcc_split"
[(set (reg:PSI 22)
(mult:PSI (reg:PSI 22)
(reg:PSI 18)))
@@ -2980,9 +4040,27 @@
(clobber (reg:QI 25))
(clobber (reg:HI 26))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:PSI 22)
+ (mult:PSI (reg:PSI 22)
+ (reg:PSI 18)))
+ (clobber (reg:QI 21))
+ (clobber (reg:QI 25))
+ (clobber (reg:HI 26))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*mulpsi3.libgcc"
+ [(set (reg:PSI 22)
+ (mult:PSI (reg:PSI 22)
+ (reg:PSI 18)))
+ (clobber (reg:QI 21))
+ (clobber (reg:QI 25))
+ (clobber (reg:HI 26))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"%~call __mulpsi3"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -3013,16 +4091,32 @@
(set (match_dup 0) (reg:PSI 22))
(set (match_dup 3) (reg:PSI 18))])
-(define_insn "*divmodpsi4_call"
+(define_insn_and_split "*divmodpsi4_call_split"
[(set (reg:PSI 22) (div:PSI (reg:PSI 22) (reg:PSI 18)))
(set (reg:PSI 18) (mod:PSI (reg:PSI 22) (reg:PSI 18)))
(clobber (reg:QI 21))
(clobber (reg:QI 25))
(clobber (reg:QI 26))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:PSI 22) (div:PSI (reg:PSI 22) (reg:PSI 18)))
+ (set (reg:PSI 18) (mod:PSI (reg:PSI 22) (reg:PSI 18)))
+ (clobber (reg:QI 21))
+ (clobber (reg:QI 25))
+ (clobber (reg:QI 26))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*divmodpsi4_call"
+ [(set (reg:PSI 22) (div:PSI (reg:PSI 22) (reg:PSI 18)))
+ (set (reg:PSI 18) (mod:PSI (reg:PSI 22) (reg:PSI 18)))
+ (clobber (reg:QI 21))
+ (clobber (reg:QI 25))
+ (clobber (reg:QI 26))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __divmodpsi4"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
(define_insn_and_split "udivmodpsi4"
[(parallel [(set (match_operand:PSI 0 "pseudo_register_operand" "")
@@ -3046,16 +4140,32 @@
(set (match_dup 0) (reg:PSI 22))
(set (match_dup 3) (reg:PSI 18))])
-(define_insn "*udivmodpsi4_call"
+(define_insn_and_split "*udivmodpsi4_call_split"
[(set (reg:PSI 22) (udiv:PSI (reg:PSI 22) (reg:PSI 18)))
(set (reg:PSI 18) (umod:PSI (reg:PSI 22) (reg:PSI 18)))
(clobber (reg:QI 21))
(clobber (reg:QI 25))
(clobber (reg:QI 26))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:PSI 22) (udiv:PSI (reg:PSI 22) (reg:PSI 18)))
+ (set (reg:PSI 18) (umod:PSI (reg:PSI 22) (reg:PSI 18)))
+ (clobber (reg:QI 21))
+ (clobber (reg:QI 25))
+ (clobber (reg:QI 26))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*udivmodpsi4_call"
+ [(set (reg:PSI 22) (udiv:PSI (reg:PSI 22) (reg:PSI 18)))
+ (set (reg:PSI 18) (umod:PSI (reg:PSI 22) (reg:PSI 18)))
+ (clobber (reg:QI 21))
+ (clobber (reg:QI 25))
+ (clobber (reg:QI 26))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __udivmodpsi4"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -3081,15 +4191,29 @@
(set (match_dup 0) (reg:SI 18))
(set (match_dup 3) (reg:SI 22))])
-(define_insn "*divmodsi4_call"
+(define_insn_and_split "*divmodsi4_call_split"
[(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
(set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
(clobber (reg:HI 26))
(clobber (reg:HI 30))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
+ (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
+ (clobber (reg:HI 26))
+ (clobber (reg:HI 30))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*divmodsi4_call"
+ [(set (reg:SI 18) (div:SI (reg:SI 22) (reg:SI 18)))
+ (set (reg:SI 22) (mod:SI (reg:SI 22) (reg:SI 18)))
+ (clobber (reg:HI 26))
+ (clobber (reg:HI 30))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __divmodsi4"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
(define_insn_and_split "udivmodsi4"
[(parallel [(set (match_operand:SI 0 "pseudo_register_operand" "")
@@ -3113,37 +4237,78 @@
(set (match_dup 0) (reg:SI 18))
(set (match_dup 3) (reg:SI 22))])
-(define_insn "*udivmodsi4_call"
+(define_insn_and_split "*udivmodsi4_call_split"
[(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
(set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
(clobber (reg:HI 26))
(clobber (reg:HI 30))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
+ (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
+ (clobber (reg:HI 26))
+ (clobber (reg:HI 30))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*udivmodsi4_call"
+ [(set (reg:SI 18) (udiv:SI (reg:SI 22) (reg:SI 18)))
+ (set (reg:SI 22) (umod:SI (reg:SI 22) (reg:SI 18)))
+ (clobber (reg:HI 26))
+ (clobber (reg:HI 30))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __udivmodsi4"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
; and
-(define_insn "andqi3"
+(define_insn_and_split "andqi3"
[(set (match_operand:QI 0 "register_operand" "=??r,d,*l")
(and:QI (match_operand:QI 1 "register_operand" "%0,0,0")
(match_operand:QI 2 "nonmemory_operand" "r,i,Ca1")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (and:QI (match_dup 1)
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*andqi3"
+ [(set (match_operand:QI 0 "register_operand" "=??r,d,*l")
+ (and:QI (match_operand:QI 1 "register_operand" "%0,0,0")
+ (match_operand:QI 2 "nonmemory_operand" "r,i,Ca1")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"@
and %0,%2
andi %0,lo8(%2)
* return avr_out_bitop (insn, operands, NULL);"
- [(set_attr "length" "1,1,2")
- (set_attr "cc" "set_zn,set_zn,none")])
+ [(set_attr "length" "1,1,2")])
-(define_insn "andhi3"
+(define_insn_and_split "andhi3"
[(set (match_operand:HI 0 "register_operand" "=??r,d,d,r ,r")
(and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0 ,0")
(match_operand:HI 2 "nonmemory_operand" "r,s,n,Ca2,n")))
(clobber (match_scratch:QI 3 "=X,X,X,X ,&d"))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (and:HI (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_dup 3))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*andhi3"
+ [(set (match_operand:HI 0 "register_operand" "=??r,d,d,r ,r")
+ (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0 ,0")
+ (match_operand:HI 2 "nonmemory_operand" "r,s,n,Ca2,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X,X ,&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
if (which_alternative == 0)
return "and %A0,%A2\;and %B0,%B2";
@@ -3153,15 +4318,29 @@
return avr_out_bitop (insn, operands, NULL);
}
[(set_attr "length" "2,2,2,4,4")
- (set_attr "adjust_len" "*,*,out_bitop,out_bitop,out_bitop")
- (set_attr "cc" "set_n,set_n,clobber,clobber,clobber")])
+ (set_attr "adjust_len" "*,*,out_bitop,out_bitop,out_bitop")])
-(define_insn "andpsi3"
+(define_insn_and_split "andpsi3"
[(set (match_operand:PSI 0 "register_operand" "=??r,d,r ,r")
(and:PSI (match_operand:PSI 1 "register_operand" "%0,0,0 ,0")
(match_operand:PSI 2 "nonmemory_operand" "r,n,Ca3,n")))
(clobber (match_scratch:QI 3 "=X,X,X ,&d"))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (and:PSI (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_dup 3))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*andpsi3"
+ [(set (match_operand:PSI 0 "register_operand" "=??r,d,r ,r")
+ (and:PSI (match_operand:PSI 1 "register_operand" "%0,0,0 ,0")
+ (match_operand:PSI 2 "nonmemory_operand" "r,n,Ca3,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X ,&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
if (which_alternative == 0)
return "and %A0,%A2" CR_TAB
@@ -3171,15 +4350,29 @@
return avr_out_bitop (insn, operands, NULL);
}
[(set_attr "length" "3,3,6,6")
- (set_attr "adjust_len" "*,out_bitop,out_bitop,out_bitop")
- (set_attr "cc" "set_n,clobber,clobber,clobber")])
+ (set_attr "adjust_len" "*,out_bitop,out_bitop,out_bitop")])
-(define_insn "andsi3"
+(define_insn_and_split "andsi3"
[(set (match_operand:SI 0 "register_operand" "=??r,d,r ,r")
(and:SI (match_operand:SI 1 "register_operand" "%0,0,0 ,0")
(match_operand:SI 2 "nonmemory_operand" "r,n,Ca4,n")))
(clobber (match_scratch:QI 3 "=X,X,X ,&d"))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (and:SI (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_dup 3))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*andsi3"
+ [(set (match_operand:SI 0 "register_operand" "=??r,d,r ,r")
+ (and:SI (match_operand:SI 1 "register_operand" "%0,0,0 ,0")
+ (match_operand:SI 2 "nonmemory_operand" "r,n,Ca4,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X ,&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
if (which_alternative == 0)
return "and %0,%2" CR_TAB
@@ -3190,8 +4383,7 @@
return avr_out_bitop (insn, operands, NULL);
}
[(set_attr "length" "4,4,8,8")
- (set_attr "adjust_len" "*,out_bitop,out_bitop,out_bitop")
- (set_attr "cc" "set_n,clobber,clobber,clobber")])
+ (set_attr "adjust_len" "*,out_bitop,out_bitop,out_bitop")])
(define_peephole2 ; andi
[(set (match_operand:QI 0 "d_register_operand" "")
@@ -3209,24 +4401,51 @@
;;|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
;; ior
-(define_insn "iorqi3"
+(define_insn_and_split "iorqi3"
+ [(set (match_operand:QI 0 "register_operand" "=??r,d,*l")
+ (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0")
+ (match_operand:QI 2 "nonmemory_operand" "r,i,Co1")))]
+ ""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (ior:QI (match_dup 1)
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*iorqi3"
[(set (match_operand:QI 0 "register_operand" "=??r,d,*l")
(ior:QI (match_operand:QI 1 "register_operand" "%0,0,0")
- (match_operand:QI 2 "nonmemory_operand" "r,i,Co1")))]
- ""
+ (match_operand:QI 2 "nonmemory_operand" "r,i,Co1")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"@
or %0,%2
ori %0,lo8(%2)
* return avr_out_bitop (insn, operands, NULL);"
- [(set_attr "length" "1,1,2")
- (set_attr "cc" "set_zn,set_zn,none")])
+ [(set_attr "length" "1,1,2")])
-(define_insn "iorhi3"
+(define_insn_and_split "iorhi3"
[(set (match_operand:HI 0 "register_operand" "=??r,d,d,r ,r")
(ior:HI (match_operand:HI 1 "register_operand" "%0,0,0,0 ,0")
(match_operand:HI 2 "nonmemory_operand" "r,s,n,Co2,n")))
(clobber (match_scratch:QI 3 "=X,X,X,X ,&d"))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (ior:HI (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_dup 3))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*iorhi3"
+ [(set (match_operand:HI 0 "register_operand" "=??r,d,d,r ,r")
+ (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0,0 ,0")
+ (match_operand:HI 2 "nonmemory_operand" "r,s,n,Co2,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X,X ,&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
if (which_alternative == 0)
return "or %A0,%A2\;or %B0,%B2";
@@ -3236,15 +4455,29 @@
return avr_out_bitop (insn, operands, NULL);
}
[(set_attr "length" "2,2,2,4,4")
- (set_attr "adjust_len" "*,*,out_bitop,out_bitop,out_bitop")
- (set_attr "cc" "set_n,set_n,clobber,clobber,clobber")])
+ (set_attr "adjust_len" "*,*,out_bitop,out_bitop,out_bitop")])
-(define_insn "iorpsi3"
+(define_insn_and_split "iorpsi3"
[(set (match_operand:PSI 0 "register_operand" "=??r,d,r ,r")
(ior:PSI (match_operand:PSI 1 "register_operand" "%0,0,0 ,0")
(match_operand:PSI 2 "nonmemory_operand" "r,n,Co3,n")))
(clobber (match_scratch:QI 3 "=X,X,X ,&d"))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (ior:PSI (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_dup 3))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*iorpsi3"
+ [(set (match_operand:PSI 0 "register_operand" "=??r,d,r ,r")
+ (ior:PSI (match_operand:PSI 1 "register_operand" "%0,0,0 ,0")
+ (match_operand:PSI 2 "nonmemory_operand" "r,n,Co3,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X ,&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
if (which_alternative == 0)
return "or %A0,%A2" CR_TAB
@@ -3254,15 +4487,29 @@
return avr_out_bitop (insn, operands, NULL);
}
[(set_attr "length" "3,3,6,6")
- (set_attr "adjust_len" "*,out_bitop,out_bitop,out_bitop")
- (set_attr "cc" "set_n,clobber,clobber,clobber")])
+ (set_attr "adjust_len" "*,out_bitop,out_bitop,out_bitop")])
-(define_insn "iorsi3"
+(define_insn_and_split "iorsi3"
[(set (match_operand:SI 0 "register_operand" "=??r,d,r ,r")
(ior:SI (match_operand:SI 1 "register_operand" "%0,0,0 ,0")
(match_operand:SI 2 "nonmemory_operand" "r,n,Co4,n")))
(clobber (match_scratch:QI 3 "=X,X,X ,&d"))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (ior:SI (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_dup 3))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*iorsi3"
+ [(set (match_operand:SI 0 "register_operand" "=??r,d,r ,r")
+ (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0 ,0")
+ (match_operand:SI 2 "nonmemory_operand" "r,n,Co4,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X ,&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
if (which_alternative == 0)
return "or %0,%2" CR_TAB
@@ -3273,27 +4520,53 @@
return avr_out_bitop (insn, operands, NULL);
}
[(set_attr "length" "4,4,8,8")
- (set_attr "adjust_len" "*,out_bitop,out_bitop,out_bitop")
- (set_attr "cc" "set_n,clobber,clobber,clobber")])
+ (set_attr "adjust_len" "*,out_bitop,out_bitop,out_bitop")])
;;^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
;; xor
-(define_insn "xorqi3"
+(define_insn_and_split "xorqi3"
[(set (match_operand:QI 0 "register_operand" "=r")
(xor:QI (match_operand:QI 1 "register_operand" "%0")
(match_operand:QI 2 "register_operand" "r")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (xor:QI (match_dup 1)
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*xorqi3"
+ [(set (match_operand:QI 0 "register_operand" "=r")
+ (xor:QI (match_operand:QI 1 "register_operand" "%0")
+ (match_operand:QI 2 "register_operand" "r")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"eor %0,%2"
- [(set_attr "length" "1")
- (set_attr "cc" "set_zn")])
+ [(set_attr "length" "1")])
-(define_insn "xorhi3"
+(define_insn_and_split "xorhi3"
[(set (match_operand:HI 0 "register_operand" "=??r,r ,r")
(xor:HI (match_operand:HI 1 "register_operand" "%0,0 ,0")
(match_operand:HI 2 "nonmemory_operand" "r,Cx2,n")))
(clobber (match_scratch:QI 3 "=X,X ,&d"))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (xor:HI (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_dup 3))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*xorhi3"
+ [(set (match_operand:HI 0 "register_operand" "=??r,r ,r")
+ (xor:HI (match_operand:HI 1 "register_operand" "%0,0 ,0")
+ (match_operand:HI 2 "nonmemory_operand" "r,Cx2,n")))
+ (clobber (match_scratch:QI 3 "=X,X ,&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
if (which_alternative == 0)
return "eor %A0,%A2\;eor %B0,%B2";
@@ -3301,15 +4574,29 @@
return avr_out_bitop (insn, operands, NULL);
}
[(set_attr "length" "2,2,4")
- (set_attr "adjust_len" "*,out_bitop,out_bitop")
- (set_attr "cc" "set_n,clobber,clobber")])
+ (set_attr "adjust_len" "*,out_bitop,out_bitop")])
-(define_insn "xorpsi3"
+(define_insn_and_split "xorpsi3"
[(set (match_operand:PSI 0 "register_operand" "=??r,r ,r")
(xor:PSI (match_operand:PSI 1 "register_operand" "%0,0 ,0")
(match_operand:PSI 2 "nonmemory_operand" "r,Cx3,n")))
(clobber (match_scratch:QI 3 "=X,X ,&d"))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (xor:PSI (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_dup 3))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*xorpsi3"
+ [(set (match_operand:PSI 0 "register_operand" "=??r,r ,r")
+ (xor:PSI (match_operand:PSI 1 "register_operand" "%0,0 ,0")
+ (match_operand:PSI 2 "nonmemory_operand" "r,Cx3,n")))
+ (clobber (match_scratch:QI 3 "=X,X ,&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
if (which_alternative == 0)
return "eor %A0,%A2" CR_TAB
@@ -3319,15 +4606,29 @@
return avr_out_bitop (insn, operands, NULL);
}
[(set_attr "length" "3,6,6")
- (set_attr "adjust_len" "*,out_bitop,out_bitop")
- (set_attr "cc" "set_n,clobber,clobber")])
+ (set_attr "adjust_len" "*,out_bitop,out_bitop")])
-(define_insn "xorsi3"
+(define_insn_and_split "xorsi3"
[(set (match_operand:SI 0 "register_operand" "=??r,r ,r")
(xor:SI (match_operand:SI 1 "register_operand" "%0,0 ,0")
(match_operand:SI 2 "nonmemory_operand" "r,Cx4,n")))
(clobber (match_scratch:QI 3 "=X,X ,&d"))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (xor:SI (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_dup 3))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*xorsi3"
+ [(set (match_operand:SI 0 "register_operand" "=??r,r ,r")
+ (xor:SI (match_operand:SI 1 "register_operand" "%0,0 ,0")
+ (match_operand:SI 2 "nonmemory_operand" "r,Cx4,n")))
+ (clobber (match_scratch:QI 3 "=X,X ,&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
if (which_alternative == 0)
return "eor %0,%2" CR_TAB
@@ -3338,8 +4639,7 @@
return avr_out_bitop (insn, operands, NULL);
}
[(set_attr "length" "4,8,8")
- (set_attr "adjust_len" "*,out_bitop,out_bitop")
- (set_attr "cc" "set_n,clobber,clobber")])
+ (set_attr "adjust_len" "*,out_bitop,out_bitop")])
(define_split
@@ -3424,11 +4724,24 @@
(rotate:QI (match_operand:QI 1 "register_operand" "")
(const_int 4)))])
-(define_insn "*rotlqi3"
+(define_insn_and_split "*rotlqi3_split"
[(set (match_operand:QI 0 "register_operand" "=r,r,r ,r ,r ,r ,r ,r")
(rotate:QI (match_operand:QI 1 "register_operand" "0,0,0 ,0 ,0 ,0 ,0 ,0")
(match_operand:QI 2 "const_0_to_7_operand" "P,K,C03,C04,C05,C06,C07,L")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (rotate:QI (match_dup 1)
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*rotlqi3"
+ [(set (match_operand:QI 0 "register_operand" "=r,r,r ,r ,r ,r ,r ,r")
+ (rotate:QI (match_operand:QI 1 "register_operand" "0,0,0 ,0 ,0 ,0 ,0 ,0")
+ (match_operand:QI 2 "const_0_to_7_operand" "P,K,C03,C04,C05,C06,C07,L")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"@
lsl %0\;adc %0,__zero_reg__
lsl %0\;adc %0,__zero_reg__\;lsl %0\;adc %0,__zero_reg__
@@ -3438,8 +4751,7 @@
swap %0\;lsl %0\;adc %0,__zero_reg__\;lsl %0\;adc %0,__zero_reg__
bst %0,0\;ror %0\;bld %0,7
" ; empty
- [(set_attr "length" "2,4,4,1,3,5,3,0")
- (set_attr "cc" "set_n,set_n,clobber,none,set_n,set_n,clobber,none")])
+ [(set_attr "length" "2,4,4,1,3,5,3,0")])
;; Split all rotates of HI,SI and PSImode registers where rotation is by
;; a whole number of bytes. The split creates the appropriate moves and
@@ -3487,59 +4799,131 @@
FAIL;
})
-(define_insn "*rotlhi2.1"
+(define_insn_and_split "*rotlhi2.1_split"
[(set (match_operand:HI 0 "register_operand" "=r")
(rotate:HI (match_operand:HI 1 "register_operand" "0")
(const_int 1)))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (rotate:HI (match_dup 1)
+ (const_int 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*rotlhi2.1"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (rotate:HI (match_operand:HI 1 "register_operand" "0")
+ (const_int 1)))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"lsl %A0\;rol %B0\;adc %A0,__zero_reg__"
- [(set_attr "length" "3")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "3")])
-(define_insn "*rotlhi2.15"
+(define_insn_and_split "*rotlhi2.15_split"
[(set (match_operand:HI 0 "register_operand" "=r")
(rotate:HI (match_operand:HI 1 "register_operand" "0")
(const_int 15)))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (rotate:HI (match_dup 1)
+ (const_int 15)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*rotlhi2.15"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (rotate:HI (match_operand:HI 1 "register_operand" "0")
+ (const_int 15)))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"bst %A0,0\;ror %B0\;ror %A0\;bld %B0,7"
- [(set_attr "length" "4")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "4")])
-(define_insn "*rotlpsi2.1"
+(define_insn_and_split "*rotlpsi2.1_split"
[(set (match_operand:PSI 0 "register_operand" "=r")
(rotate:PSI (match_operand:PSI 1 "register_operand" "0")
(const_int 1)))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (rotate:PSI (match_dup 1)
+ (const_int 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*rotlpsi2.1"
+ [(set (match_operand:PSI 0 "register_operand" "=r")
+ (rotate:PSI (match_operand:PSI 1 "register_operand" "0")
+ (const_int 1)))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"lsl %A0\;rol %B0\;rol %C0\;adc %A0,__zero_reg__"
- [(set_attr "length" "4")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "4")])
-(define_insn "*rotlpsi2.23"
+(define_insn_and_split "*rotlpsi2.23_split"
[(set (match_operand:PSI 0 "register_operand" "=r")
(rotate:PSI (match_operand:PSI 1 "register_operand" "0")
(const_int 23)))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (rotate:PSI (match_dup 1)
+ (const_int 23)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*rotlpsi2.23"
+ [(set (match_operand:PSI 0 "register_operand" "=r")
+ (rotate:PSI (match_operand:PSI 1 "register_operand" "0")
+ (const_int 23)))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"bst %A0,0\;ror %C0\;ror %B0\;ror %A0\;bld %C0,7"
- [(set_attr "length" "5")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "5")])
-(define_insn "*rotlsi2.1"
+(define_insn_and_split "*rotlsi2.1_split"
[(set (match_operand:SI 0 "register_operand" "=r")
(rotate:SI (match_operand:SI 1 "register_operand" "0")
(const_int 1)))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (rotate:SI (match_dup 1)
+ (const_int 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*rotlsi2.1"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (rotate:SI (match_operand:SI 1 "register_operand" "0")
+ (const_int 1)))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"lsl %A0\;rol %B0\;rol %C0\;rol %D0\;adc %A0,__zero_reg__"
- [(set_attr "length" "5")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "5")])
-(define_insn "*rotlsi2.31"
+(define_insn_and_split "*rotlsi2.31_split"
[(set (match_operand:SI 0 "register_operand" "=r")
(rotate:SI (match_operand:SI 1 "register_operand" "0")
(const_int 31)))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (rotate:SI (match_dup 1)
+ (const_int 31)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*rotlsi2.31"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (rotate:SI (match_operand:SI 1 "register_operand" "0")
+ (const_int 31)))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"bst %A0,0\;ror %D0\;ror %C0\;ror %B0\;ror %A0\;bld %D0,7"
- [(set_attr "length" "6")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "6")])
;; Overlapping non-HImode registers often (but not always) need a scratch.
;; The best we can do is use early clobber alternative "#&r" so that
@@ -3644,29 +5028,53 @@
;; "*ashlqi3"
;; "*ashlqq3" "*ashluqq3"
-(define_insn "*ashl<mode>3"
+(define_insn_and_split "*ashl<mode>3_split"
[(set (match_operand:ALL1 0 "register_operand" "=r,r,r,r,!d,r,r")
(ashift:ALL1 (match_operand:ALL1 1 "register_operand" "0,0,0,0,0 ,0,0")
(match_operand:QI 2 "nop_general_operand" "r,L,P,K,n ,n,Qm")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (ashift:ALL1 (match_dup 1)
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*ashl<mode>3"
+ [(set (match_operand:ALL1 0 "register_operand" "=r,r,r,r,!d,r,r")
+ (ashift:ALL1 (match_operand:ALL1 1 "register_operand" "0,0,0,0,0 ,0,0")
+ (match_operand:QI 2 "nop_general_operand" "r,L,P,K,n ,n,Qm")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
- return ashlqi3_out (insn, operands, NULL);
+ return ashlqi3_out (insn, operands, 3, NULL);
}
[(set_attr "length" "5,0,1,2,4,6,9")
- (set_attr "adjust_len" "ashlqi")
- (set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")])
+ (set_attr "adjust_len" "ashlqi")])
-(define_insn "ashl<mode>3"
+(define_insn_and_split "ashl<mode>3"
[(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r,r,r")
(ashift:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,0,r,0,0,0")
(match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (ashift:ALL2 (match_dup 1)
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*ashl<mode>3"
+ [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r,r,r")
+ (ashift:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,0,r,0,0,0")
+ (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
- return ashlhi3_out (insn, operands, NULL);
+ return ashlhi3_out (insn, operands, 3, NULL);
}
[(set_attr "length" "6,0,2,2,4,10,10")
- (set_attr "adjust_len" "ashlhi")
- (set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")])
+ (set_attr "adjust_len" "ashlhi")])
;; Insns like the following are generated when (implicitly) extending 8-bit shifts
@@ -3752,17 +5160,29 @@
;; "ashlsi3"
;; "ashlsq3" "ashlusq3"
;; "ashlsa3" "ashlusa3"
-(define_insn "ashl<mode>3"
+(define_insn_and_split "ashl<mode>3"
[(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r,r,r,r")
(ashift:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,0,r,0,0,0")
(match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (ashift:ALL4 (match_dup 1)
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*ashl<mode>3"
+ [(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r,r,r,r")
+ (ashift:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,0,r,0,0,0")
+ (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
- return ashlsi3_out (insn, operands, NULL);
+ return ashlsi3_out (insn, operands, 3, NULL);
}
[(set_attr "length" "8,0,4,4,8,10,12")
- (set_attr "adjust_len" "ashlsi")
- (set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")])
+ (set_attr "adjust_len" "ashlsi")])
;; Optimize if a scratch register from LD_REGS happens to be available.
@@ -3821,18 +5241,32 @@
;; "*ashlhi3_const"
;; "*ashlhq3_const" "*ashluhq3_const"
;; "*ashlha3_const" "*ashluha3_const"
-(define_insn "*ashl<mode>3_const"
+(define_insn_and_split "*ashl<mode>3_const_split"
[(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r")
(ashift:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,r,0,0")
(match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
(clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
"reload_completed"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (ashift:ALL2 (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_dup 3))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*ashl<mode>3_const"
+ [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r")
+ (ashift:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,r,0,0")
+ (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
- return ashlhi3_out (insn, operands, NULL);
+ return ashlhi3_out (insn, operands, 4, NULL);
}
[(set_attr "length" "0,2,2,4,10")
- (set_attr "adjust_len" "ashlhi")
- (set_attr "cc" "none,set_n,clobber,set_n,clobber")])
+ (set_attr "adjust_len" "ashlhi")])
(define_peephole2
[(match_scratch:QI 3 "d")
@@ -3848,18 +5282,32 @@
;; "*ashlsi3_const"
;; "*ashlsq3_const" "*ashlusq3_const"
;; "*ashlsa3_const" "*ashlusa3_const"
-(define_insn "*ashl<mode>3_const"
+(define_insn_and_split "*ashl<mode>3_const_split"
[(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r")
(ashift:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,r,0")
(match_operand:QI 2 "const_int_operand" "L,P,O,n")))
(clobber (match_scratch:QI 3 "=X,X,X,&d"))]
"reload_completed"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (ashift:ALL4 (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_dup 3))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*ashl<mode>3_const"
+ [(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r")
+ (ashift:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,r,0")
+ (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X,&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
- return ashlsi3_out (insn, operands, NULL);
+ return ashlsi3_out (insn, operands, 4, NULL);
}
[(set_attr "length" "0,4,4,10")
- (set_attr "adjust_len" "ashlsi")
- (set_attr "cc" "none,set_n,clobber,clobber")])
+ (set_attr "adjust_len" "ashlsi")])
(define_expand "ashlpsi3"
[(parallel [(set (match_operand:PSI 0 "register_operand" "")
@@ -3888,76 +5336,140 @@
}
})
-(define_insn "*ashlpsi3"
+(define_insn_and_split "*ashlpsi3_split"
[(set (match_operand:PSI 0 "register_operand" "=r,r,r,r")
(ashift:PSI (match_operand:PSI 1 "register_operand" "0,0,r,0")
(match_operand:QI 2 "nonmemory_operand" "r,P,O,n")))
(clobber (match_scratch:QI 3 "=X,X,X,&d"))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (ashift:PSI (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_dup 3))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*ashlpsi3"
+ [(set (match_operand:PSI 0 "register_operand" "=r,r,r,r")
+ (ashift:PSI (match_operand:PSI 1 "register_operand" "0,0,r,0")
+ (match_operand:QI 2 "nonmemory_operand" "r,P,O,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X,&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
- return avr_out_ashlpsi3 (insn, operands, NULL);
+ return avr_out_ashlpsi3 (insn, operands, 4, NULL);
}
- [(set_attr "adjust_len" "ashlpsi")
- (set_attr "cc" "clobber")])
+ [(set_attr "adjust_len" "ashlpsi")])
;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
;; arithmetic shift right
;; "ashrqi3"
;; "ashrqq3" "ashruqq3"
-(define_insn "ashr<mode>3"
+(define_insn_and_split "ashr<mode>3"
[(set (match_operand:ALL1 0 "register_operand" "=r,r,r,r,r ,r ,r")
(ashiftrt:ALL1 (match_operand:ALL1 1 "register_operand" "0,0,0,0,0 ,0 ,0")
(match_operand:QI 2 "nop_general_operand" "r,L,P,K,C03 C04 C05,C06 C07,Qm")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (ashiftrt:ALL1 (match_dup 1)
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*ashr<mode>3"
+ [(set (match_operand:ALL1 0 "register_operand" "=r,r,r,r,r ,r ,r")
+ (ashiftrt:ALL1 (match_operand:ALL1 1 "register_operand" "0,0,0,0,0 ,0 ,0")
+ (match_operand:QI 2 "nop_general_operand" "r,L,P,K,C03 C04 C05,C06 C07,Qm")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
- return ashrqi3_out (insn, operands, NULL);
+ return ashrqi3_out (insn, operands, 3, NULL);
}
[(set_attr "length" "5,0,1,2,5,4,9")
- (set_attr "adjust_len" "ashrqi")
- (set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,clobber,clobber")])
+ (set_attr "adjust_len" "ashrqi")])
;; "ashrhi3"
;; "ashrhq3" "ashruhq3"
;; "ashrha3" "ashruha3"
-(define_insn "ashr<mode>3"
+(define_insn_and_split "ashr<mode>3"
[(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r,r,r")
(ashiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,0,r,0,0,0")
(match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r,r,r")
+ (ashiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,0,r,0,0,0")
+ (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*ashr<mode>3"
+ [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r,r,r")
+ (ashiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,0,r,0,0,0")
+ (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
- return ashrhi3_out (insn, operands, NULL);
+ return ashrhi3_out (insn, operands, 2, NULL);
}
[(set_attr "length" "6,0,2,4,4,10,10")
- (set_attr "adjust_len" "ashrhi")
- (set_attr "cc" "clobber,none,clobber,set_n,clobber,clobber,clobber")])
+ (set_attr "adjust_len" "ashrhi")])
-(define_insn "ashrpsi3"
+(define_insn_and_split "ashrpsi3"
[(set (match_operand:PSI 0 "register_operand" "=r,r,r,r,r")
(ashiftrt:PSI (match_operand:PSI 1 "register_operand" "0,0,0,r,0")
(match_operand:QI 2 "nonmemory_operand" "r,P,K,O,n")))
(clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (ashiftrt:PSI (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_dup 3))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*ashrpsi3"
+ [(set (match_operand:PSI 0 "register_operand" "=r,r,r,r,r")
+ (ashiftrt:PSI (match_operand:PSI 1 "register_operand" "0,0,0,r,0")
+ (match_operand:QI 2 "nonmemory_operand" "r,P,K,O,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
- return avr_out_ashrpsi3 (insn, operands, NULL);
+ return avr_out_ashrpsi3 (insn, operands, 4, NULL);
}
- [(set_attr "adjust_len" "ashrpsi")
- (set_attr "cc" "clobber")])
+ [(set_attr "adjust_len" "ashrpsi")])
;; "ashrsi3"
;; "ashrsq3" "ashrusq3"
;; "ashrsa3" "ashrusa3"
-(define_insn "ashr<mode>3"
+(define_insn_and_split "ashr<mode>3"
[(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r,r,r,r")
(ashiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,0,r,0,0,0")
(match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (ashiftrt:ALL4 (match_dup 1)
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*ashr<mode>3"
+ [(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r,r,r,r")
+ (ashiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,0,r,0,0,0")
+ (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
- return ashrsi3_out (insn, operands, NULL);
+ return ashrsi3_out (insn, operands, 3, NULL);
}
[(set_attr "length" "8,0,4,6,8,10,12")
- (set_attr "adjust_len" "ashrsi")
- (set_attr "cc" "clobber,none,clobber,set_n,clobber,clobber,clobber")])
+ (set_attr "adjust_len" "ashrsi")])
;; Optimize if a scratch register from LD_REGS happens to be available.
@@ -3975,18 +5487,32 @@
;; "*ashrhi3_const"
;; "*ashrhq3_const" "*ashruhq3_const"
;; "*ashrha3_const" "*ashruha3_const"
-(define_insn "*ashr<mode>3_const"
+(define_insn_and_split "*ashr<mode>3_const_split"
[(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r")
(ashiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,r,0,0")
(match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
(clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
"reload_completed"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (ashiftrt:ALL2 (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_dup 3))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*ashr<mode>3_const"
+ [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r")
+ (ashiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,r,0,0")
+ (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
- return ashrhi3_out (insn, operands, NULL);
+ return ashrhi3_out (insn, operands, 3, NULL);
}
[(set_attr "length" "0,2,4,4,10")
- (set_attr "adjust_len" "ashrhi")
- (set_attr "cc" "none,clobber,set_n,clobber,clobber")])
+ (set_attr "adjust_len" "ashrhi")])
(define_peephole2
[(match_scratch:QI 3 "d")
@@ -4002,18 +5528,32 @@
;; "*ashrsi3_const"
;; "*ashrsq3_const" "*ashrusq3_const"
;; "*ashrsa3_const" "*ashrusa3_const"
-(define_insn "*ashr<mode>3_const"
+(define_insn_and_split "*ashr<mode>3_const_split"
[(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r")
(ashiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,r,0")
(match_operand:QI 2 "const_int_operand" "L,P,O,n")))
(clobber (match_scratch:QI 3 "=X,X,X,&d"))]
"reload_completed"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (ashiftrt:ALL4 (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_dup 3))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*ashr<mode>3_const"
+ [(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r")
+ (ashiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,r,0")
+ (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X,&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
- return ashrsi3_out (insn, operands, NULL);
+ return ashrsi3_out (insn, operands, 4, NULL);
}
[(set_attr "length" "0,4,4,10")
- (set_attr "adjust_len" "ashrsi")
- (set_attr "cc" "none,clobber,set_n,clobber")])
+ (set_attr "adjust_len" "ashrsi")])
;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
;; logical shift right
@@ -4067,59 +5607,109 @@
;; "*lshrqi3"
;; "*lshrqq3"
;; "*lshruqq3"
-(define_insn "*lshr<mode>3"
+(define_insn_and_split "*lshr<mode>3_split"
[(set (match_operand:ALL1 0 "register_operand" "=r,r,r,r,!d,r,r")
(lshiftrt:ALL1 (match_operand:ALL1 1 "register_operand" "0,0,0,0,0 ,0,0")
(match_operand:QI 2 "nop_general_operand" "r,L,P,K,n ,n,Qm")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (lshiftrt:ALL1 (match_dup 1)
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*lshr<mode>3"
+ [(set (match_operand:ALL1 0 "register_operand" "=r,r,r,r,!d,r,r")
+ (lshiftrt:ALL1 (match_operand:ALL1 1 "register_operand" "0,0,0,0,0 ,0,0")
+ (match_operand:QI 2 "nop_general_operand" "r,L,P,K,n ,n,Qm")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
- return lshrqi3_out (insn, operands, NULL);
+ return lshrqi3_out (insn, operands, 3, NULL);
}
[(set_attr "length" "5,0,1,2,4,6,9")
- (set_attr "adjust_len" "lshrqi")
- (set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")])
+ (set_attr "adjust_len" "lshrqi")])
;; "lshrhi3"
;; "lshrhq3" "lshruhq3"
;; "lshrha3" "lshruha3"
-(define_insn "lshr<mode>3"
+(define_insn_and_split "lshr<mode>3"
[(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r,r,r")
(lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,0,r,0,0,0")
(match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (lshiftrt:ALL2 (match_dup 1)
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*lshr<mode>3"
+ [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r,r,r")
+ (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,0,r,0,0,0")
+ (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
- return lshrhi3_out (insn, operands, NULL);
+ return lshrhi3_out (insn, operands, 3, NULL);
}
[(set_attr "length" "6,0,2,2,4,10,10")
- (set_attr "adjust_len" "lshrhi")
- (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber,clobber")])
+ (set_attr "adjust_len" "lshrhi")])
-(define_insn "lshrpsi3"
+(define_insn_and_split "lshrpsi3"
[(set (match_operand:PSI 0 "register_operand" "=r,r,r,r,r")
(lshiftrt:PSI (match_operand:PSI 1 "register_operand" "0,0,r,0,0")
(match_operand:QI 2 "nonmemory_operand" "r,P,O,K,n")))
(clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (lshiftrt:PSI (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_dup 3))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*lshrpsi3"
+ [(set (match_operand:PSI 0 "register_operand" "=r,r,r,r,r")
+ (lshiftrt:PSI (match_operand:PSI 1 "register_operand" "0,0,r,0,0")
+ (match_operand:QI 2 "nonmemory_operand" "r,P,O,K,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
- return avr_out_lshrpsi3 (insn, operands, NULL);
+ return avr_out_lshrpsi3 (insn, operands, 4, NULL);
}
- [(set_attr "adjust_len" "lshrpsi")
- (set_attr "cc" "clobber")])
+ [(set_attr "adjust_len" "lshrpsi")])
;; "lshrsi3"
;; "lshrsq3" "lshrusq3"
;; "lshrsa3" "lshrusa3"
-(define_insn "lshr<mode>3"
+(define_insn_and_split "lshr<mode>3"
[(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r,r,r,r")
(lshiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,0,r,0,0,0")
(match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (lshiftrt:ALL4 (match_dup 1)
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*lshr<mode>3"
+ [(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r,r,r,r")
+ (lshiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,0,r,0,0,0")
+ (match_operand:QI 2 "nop_general_operand" "r,L,P,O,K,n,Qm")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
- return lshrsi3_out (insn, operands, NULL);
+ return lshrsi3_out (insn, operands, 3, NULL);
}
[(set_attr "length" "8,0,4,4,8,10,12")
- (set_attr "adjust_len" "lshrsi")
- (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber,clobber")])
+ (set_attr "adjust_len" "lshrsi")])
;; Optimize if a scratch register from LD_REGS happens to be available.
@@ -4178,18 +5768,32 @@
;; "*lshrhi3_const"
;; "*lshrhq3_const" "*lshruhq3_const"
;; "*lshrha3_const" "*lshruha3_const"
-(define_insn "*lshr<mode>3_const"
+(define_insn_and_split "*lshr<mode>3_const_split"
[(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r")
(lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,r,0,0")
(match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
(clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
"reload_completed"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (lshiftrt:ALL2 (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_dup 3))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*lshr<mode>3_const"
+ [(set (match_operand:ALL2 0 "register_operand" "=r,r,r,r,r")
+ (lshiftrt:ALL2 (match_operand:ALL2 1 "register_operand" "0,0,r,0,0")
+ (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
- return lshrhi3_out (insn, operands, NULL);
+ return lshrhi3_out (insn, operands, 4, NULL);
}
[(set_attr "length" "0,2,2,4,10")
- (set_attr "adjust_len" "lshrhi")
- (set_attr "cc" "none,clobber,clobber,clobber,clobber")])
+ (set_attr "adjust_len" "lshrhi")])
(define_peephole2
[(match_scratch:QI 3 "d")
@@ -4205,143 +5809,277 @@
;; "*lshrsi3_const"
;; "*lshrsq3_const" "*lshrusq3_const"
;; "*lshrsa3_const" "*lshrusa3_const"
-(define_insn "*lshr<mode>3_const"
+(define_insn_and_split "*lshr<mode>3_const_split"
[(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r")
(lshiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,r,0")
(match_operand:QI 2 "const_int_operand" "L,P,O,n")))
(clobber (match_scratch:QI 3 "=X,X,X,&d"))]
"reload_completed"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (lshiftrt:ALL4 (match_dup 1)
+ (match_dup 2)))
+ (clobber (match_dup 3))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*lshr<mode>3_const"
+ [(set (match_operand:ALL4 0 "register_operand" "=r,r,r,r")
+ (lshiftrt:ALL4 (match_operand:ALL4 1 "register_operand" "0,0,r,0")
+ (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X,&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
- return lshrsi3_out (insn, operands, NULL);
+ return lshrsi3_out (insn, operands, 4, NULL);
}
[(set_attr "length" "0,4,4,10")
- (set_attr "adjust_len" "lshrsi")
- (set_attr "cc" "none,clobber,clobber,clobber")])
+ (set_attr "adjust_len" "lshrsi")])
;; abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x)
;; abs
-(define_insn "absqi2"
+(define_insn_and_split "absqi2"
[(set (match_operand:QI 0 "register_operand" "=r")
(abs:QI (match_operand:QI 1 "register_operand" "0")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (abs:QI (match_dup 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*absqi2"
+ [(set (match_operand:QI 0 "register_operand" "=r")
+ (abs:QI (match_operand:QI 1 "register_operand" "0")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"sbrc %0,7
neg %0"
- [(set_attr "length" "2")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "2")])
-(define_insn "abssf2"
+(define_insn_and_split "abssf2"
[(set (match_operand:SF 0 "register_operand" "=d,r")
(abs:SF (match_operand:SF 1 "register_operand" "0,0")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (abs:SF (match_dup 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*abssf2"
+ [(set (match_operand:SF 0 "register_operand" "=d,r")
+ (abs:SF (match_operand:SF 1 "register_operand" "0,0")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"@
andi %D0,0x7f
clt\;bld %D0,7"
- [(set_attr "length" "1,2")
- (set_attr "cc" "set_n,clobber")])
+ [(set_attr "length" "1,2")])
;; 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x 0 - x
;; neg
-(define_insn "negqi2"
+(define_insn_and_split "negqi2"
[(set (match_operand:QI 0 "register_operand" "=r")
(neg:QI (match_operand:QI 1 "register_operand" "0")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (neg:QI (match_dup 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*negqi2"
+ [(set (match_operand:QI 0 "register_operand" "=r")
+ (neg:QI (match_operand:QI 1 "register_operand" "0")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"neg %0"
- [(set_attr "length" "1")
- (set_attr "cc" "set_vzn")])
+ [(set_attr "length" "1")])
-(define_insn "*negqihi2"
+(define_insn_and_split "*negqihi2_split"
[(set (match_operand:HI 0 "register_operand" "=r")
(neg:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "0"))))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (neg:HI (sign_extend:HI (match_dup 1))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*negqihi2"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (neg:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "0"))))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"clr %B0\;neg %A0\;brge .+2\;com %B0"
- [(set_attr "length" "4")
- (set_attr "cc" "set_n")])
+ [(set_attr "length" "4")])
-(define_insn "neghi2"
+(define_insn_and_split "neghi2"
[(set (match_operand:HI 0 "register_operand" "=r,&r")
(neg:HI (match_operand:HI 1 "register_operand" "0,r")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (neg:HI (match_dup 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*neghi2"
+ [(set (match_operand:HI 0 "register_operand" "=r,&r")
+ (neg:HI (match_operand:HI 1 "register_operand" "0,r")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"@
neg %B0\;neg %A0\;sbc %B0,__zero_reg__
clr %A0\;clr %B0\;sub %A0,%A1\;sbc %B0,%B1"
- [(set_attr "length" "3,4")
- (set_attr "cc" "set_czn")])
+ [(set_attr "length" "3,4")])
-(define_insn "negpsi2"
+(define_insn_and_split "negpsi2"
[(set (match_operand:PSI 0 "register_operand" "=!d,r,&r")
(neg:PSI (match_operand:PSI 1 "register_operand" "0,0,r")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (neg:PSI (match_dup 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*negpsi2"
+ [(set (match_operand:PSI 0 "register_operand" "=!d,r,&r")
+ (neg:PSI (match_operand:PSI 1 "register_operand" "0,0,r")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"@
com %C0\;com %B0\;neg %A0\;sbci %B0,-1\;sbci %C0,-1
com %C0\;com %B0\;com %A0\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__
clr %A0\;clr %B0\;clr %C0\;sub %A0,%A1\;sbc %B0,%B1\;sbc %C0,%C1"
- [(set_attr "length" "5,6,6")
- (set_attr "cc" "set_czn,set_n,set_czn")])
+ [(set_attr "length" "5,6,6")])
-(define_insn "negsi2"
+(define_insn_and_split "negsi2"
[(set (match_operand:SI 0 "register_operand" "=!d,r,&r,&r")
(neg:SI (match_operand:SI 1 "register_operand" "0,0,r ,r")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (neg:SI (match_dup 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*negsi2"
+ [(set (match_operand:SI 0 "register_operand" "=!d,r,&r,&r")
+ (neg:SI (match_operand:SI 1 "register_operand" "0,0,r ,r")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"@
com %D0\;com %C0\;com %B0\;neg %A0\;sbci %B0,lo8(-1)\;sbci %C0,lo8(-1)\;sbci %D0,lo8(-1)
com %D0\;com %C0\;com %B0\;com %A0\;adc %A0,__zero_reg__\;adc %B0,__zero_reg__\;adc %C0,__zero_reg__\;adc %D0,__zero_reg__
clr %A0\;clr %B0\;clr %C0\;clr %D0\;sub %A0,%A1\;sbc %B0,%B1\;sbc %C0,%C1\;sbc %D0,%D1
clr %A0\;clr %B0\;movw %C0,%A0\;sub %A0,%A1\;sbc %B0,%B1\;sbc %C0,%C1\;sbc %D0,%D1"
[(set_attr "length" "7,8,8,7")
- (set_attr "isa" "*,*,mov,movw")
- (set_attr "cc" "set_czn,set_n,set_czn,set_czn")])
+ (set_attr "isa" "*,*,mov,movw")])
-(define_insn "negsf2"
+(define_insn_and_split "negsf2"
[(set (match_operand:SF 0 "register_operand" "=d,r")
(neg:SF (match_operand:SF 1 "register_operand" "0,0")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (neg:SF (match_dup 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*negsf2"
+ [(set (match_operand:SF 0 "register_operand" "=d,r")
+ (neg:SF (match_operand:SF 1 "register_operand" "0,0")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"@
subi %D0,0x80
bst %D0,7\;com %D0\;bld %D0,7\;com %D0"
- [(set_attr "length" "1,4")
- (set_attr "cc" "set_n,set_n")])
+ [(set_attr "length" "1,4")])
;; !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
;; not
-(define_insn "one_cmplqi2"
+(define_insn_and_split "one_cmplqi2"
[(set (match_operand:QI 0 "register_operand" "=r")
(not:QI (match_operand:QI 1 "register_operand" "0")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (not:QI (match_dup 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*one_cmplqi2"
+ [(set (match_operand:QI 0 "register_operand" "=r")
+ (not:QI (match_operand:QI 1 "register_operand" "0")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"com %0"
- [(set_attr "length" "1")
- (set_attr "cc" "set_czn")])
+ [(set_attr "length" "1")])
-(define_insn "one_cmplhi2"
+(define_insn_and_split "one_cmplhi2"
[(set (match_operand:HI 0 "register_operand" "=r")
(not:HI (match_operand:HI 1 "register_operand" "0")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (not:HI (match_dup 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*one_cmplhi2"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (not:HI (match_operand:HI 1 "register_operand" "0")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"com %0
com %B0"
- [(set_attr "length" "2")
- (set_attr "cc" "set_n")])
+ [(set_attr "length" "2")])
-(define_insn "one_cmplpsi2"
+(define_insn_and_split "one_cmplpsi2"
[(set (match_operand:PSI 0 "register_operand" "=r")
(not:PSI (match_operand:PSI 1 "register_operand" "0")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (not:PSI (match_dup 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*one_cmplpsi2"
+ [(set (match_operand:PSI 0 "register_operand" "=r")
+ (not:PSI (match_operand:PSI 1 "register_operand" "0")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"com %0\;com %B0\;com %C0"
- [(set_attr "length" "3")
- (set_attr "cc" "set_n")])
+ [(set_attr "length" "3")])
-(define_insn "one_cmplsi2"
+(define_insn_and_split "one_cmplsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(not:SI (match_operand:SI 1 "register_operand" "0")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (not:SI (match_dup 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*one_cmplsi2"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (not:SI (match_operand:SI 1 "register_operand" "0")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"com %0
com %B0
com %C0
com %D0"
- [(set_attr "length" "4")
- (set_attr "cc" "set_n")])
+ [(set_attr "length" "4")])
;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x
;; sign extend
@@ -4353,71 +6091,131 @@
;; multiplication. There is no need for combine to propagate hard registers,
;; register allocation can do it just as well.
-(define_insn "extendqihi2"
+(define_insn_and_split "extendqihi2"
[(set (match_operand:HI 0 "register_operand" "=r,r")
(sign_extend:HI (match_operand:QI 1 "combine_pseudo_register_operand" "0,*r")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (sign_extend:HI (match_dup 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*extendqihi2"
+ [(set (match_operand:HI 0 "register_operand" "=r,r")
+ (sign_extend:HI (match_operand:QI 1 "combine_pseudo_register_operand" "0,*r")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return avr_out_sign_extend (insn, operands, NULL);
}
[(set_attr "length" "3,4")
- (set_attr "adjust_len" "sext")
- (set_attr "cc" "set_n")])
+ (set_attr "adjust_len" "sext")])
-(define_insn "extendqipsi2"
+(define_insn_and_split "extendqipsi2"
[(set (match_operand:PSI 0 "register_operand" "=r,r")
(sign_extend:PSI (match_operand:QI 1 "combine_pseudo_register_operand" "0,*r")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (sign_extend:PSI (match_dup 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*extendqipsi2"
+ [(set (match_operand:PSI 0 "register_operand" "=r,r")
+ (sign_extend:PSI (match_operand:QI 1 "combine_pseudo_register_operand" "0,*r")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return avr_out_sign_extend (insn, operands, NULL);
}
[(set_attr "length" "4,5")
- (set_attr "adjust_len" "sext")
- (set_attr "cc" "set_n")])
+ (set_attr "adjust_len" "sext")])
-(define_insn "extendqisi2"
+(define_insn_and_split "extendqisi2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(sign_extend:SI (match_operand:QI 1 "combine_pseudo_register_operand" "0,*r")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (sign_extend:SI (match_dup 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*extendqisi2"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (sign_extend:SI (match_operand:QI 1 "combine_pseudo_register_operand" "0,*r")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return avr_out_sign_extend (insn, operands, NULL);
}
[(set_attr "length" "5,6")
- (set_attr "adjust_len" "sext")
- (set_attr "cc" "set_n")])
+ (set_attr "adjust_len" "sext")])
-(define_insn "extendhipsi2"
+(define_insn_and_split "extendhipsi2"
[(set (match_operand:PSI 0 "register_operand" "=r,r")
(sign_extend:PSI (match_operand:HI 1 "combine_pseudo_register_operand" "0,*r")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (sign_extend:PSI (match_dup 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*extendhipsi2"
+ [(set (match_operand:PSI 0 "register_operand" "=r,r")
+ (sign_extend:PSI (match_operand:HI 1 "combine_pseudo_register_operand" "0,*r")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return avr_out_sign_extend (insn, operands, NULL);
}
[(set_attr "length" "3,5")
- (set_attr "adjust_len" "sext")
- (set_attr "cc" "set_n")])
+ (set_attr "adjust_len" "sext")])
-(define_insn "extendhisi2"
+(define_insn_and_split "extendhisi2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(sign_extend:SI (match_operand:HI 1 "combine_pseudo_register_operand" "0,*r")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (sign_extend:SI (match_dup 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*extendhisi2"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (sign_extend:SI (match_operand:HI 1 "combine_pseudo_register_operand" "0,*r")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return avr_out_sign_extend (insn, operands, NULL);
}
[(set_attr "length" "4,6")
- (set_attr "adjust_len" "sext")
- (set_attr "cc" "set_n")])
+ (set_attr "adjust_len" "sext")])
-(define_insn "extendpsisi2"
+(define_insn_and_split "extendpsisi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(sign_extend:SI (match_operand:PSI 1 "combine_pseudo_register_operand" "0")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (sign_extend:SI (match_dup 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*extendpsisi2"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (sign_extend:SI (match_operand:PSI 1 "combine_pseudo_register_operand" "0")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return avr_out_sign_extend (insn, operands, NULL);
}
[(set_attr "length" "3")
- (set_attr "adjust_len" "sext")
- (set_attr "cc" "set_n")])
+ (set_attr "adjust_len" "sext")])
;; xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x xx<---x
;; zero extend
@@ -4585,145 +6383,133 @@
; Optimize negated tests into reverse compare if overflow is undefined.
(define_insn "*negated_tstqi"
- [(set (cc0)
- (compare (neg:QI (match_operand:QI 0 "register_operand" "r"))
+ [(set (reg:CC REG_CC)
+ (compare:CC (neg:QI (match_operand:QI 0 "register_operand" "r"))
(const_int 0)))]
- "!flag_wrapv && !flag_trapv"
+ "reload_completed && !flag_wrapv && !flag_trapv"
"cp __zero_reg__,%0"
- [(set_attr "cc" "compare")
- (set_attr "length" "1")])
+ [(set_attr "length" "1")])
(define_insn "*reversed_tstqi"
- [(set (cc0)
- (compare (const_int 0)
+ [(set (reg:CC REG_CC)
+ (compare:CC (const_int 0)
(match_operand:QI 0 "register_operand" "r")))]
- ""
+ "reload_completed"
"cp __zero_reg__,%0"
-[(set_attr "cc" "compare")
- (set_attr "length" "2")])
+[(set_attr "length" "2")])
(define_insn "*negated_tsthi"
- [(set (cc0)
- (compare (neg:HI (match_operand:HI 0 "register_operand" "r"))
+ [(set (reg:CC REG_CC)
+ (compare:CC (neg:HI (match_operand:HI 0 "register_operand" "r"))
(const_int 0)))]
- "!flag_wrapv && !flag_trapv"
+ "reload_completed && !flag_wrapv && !flag_trapv"
"cp __zero_reg__,%A0
cpc __zero_reg__,%B0"
-[(set_attr "cc" "compare")
- (set_attr "length" "2")])
+[(set_attr "length" "2")])
;; Leave here the clobber used by the cmphi pattern for simplicity, even
;; though it is unused, because this pattern is synthesized by avr_reorg.
(define_insn "*reversed_tsthi"
- [(set (cc0)
- (compare (const_int 0)
+ [(set (reg:CC REG_CC)
+ (compare:CC (const_int 0)
(match_operand:HI 0 "register_operand" "r")))
(clobber (match_scratch:QI 1 "=X"))]
- ""
+ "reload_completed"
"cp __zero_reg__,%A0
cpc __zero_reg__,%B0"
-[(set_attr "cc" "compare")
- (set_attr "length" "2")])
+[(set_attr "length" "2")])
(define_insn "*negated_tstpsi"
- [(set (cc0)
- (compare (neg:PSI (match_operand:PSI 0 "register_operand" "r"))
+ [(set (reg:CC REG_CC)
+ (compare:CC (neg:PSI (match_operand:PSI 0 "register_operand" "r"))
(const_int 0)))]
- "!flag_wrapv && !flag_trapv"
+ "reload_completed && !flag_wrapv && !flag_trapv"
"cp __zero_reg__,%A0\;cpc __zero_reg__,%B0\;cpc __zero_reg__,%C0"
- [(set_attr "cc" "compare")
- (set_attr "length" "3")])
+ [(set_attr "length" "3")])
(define_insn "*reversed_tstpsi"
- [(set (cc0)
- (compare (const_int 0)
+ [(set (reg:CC REG_CC)
+ (compare:CC (const_int 0)
(match_operand:PSI 0 "register_operand" "r")))
(clobber (match_scratch:QI 1 "=X"))]
- ""
+ "reload_completed"
"cp __zero_reg__,%A0\;cpc __zero_reg__,%B0\;cpc __zero_reg__,%C0"
- [(set_attr "cc" "compare")
- (set_attr "length" "3")])
+ [(set_attr "length" "3")])
(define_insn "*negated_tstsi"
- [(set (cc0)
- (compare (neg:SI (match_operand:SI 0 "register_operand" "r"))
+ [(set (reg:CC REG_CC)
+ (compare:CC (neg:SI (match_operand:SI 0 "register_operand" "r"))
(const_int 0)))]
- "!flag_wrapv && !flag_trapv"
+ "reload_completed && !flag_wrapv && !flag_trapv"
"cp __zero_reg__,%A0
cpc __zero_reg__,%B0
cpc __zero_reg__,%C0
cpc __zero_reg__,%D0"
- [(set_attr "cc" "compare")
- (set_attr "length" "4")])
+ [(set_attr "length" "4")])
;; "*reversed_tstsi"
;; "*reversed_tstsq" "*reversed_tstusq"
;; "*reversed_tstsa" "*reversed_tstusa"
(define_insn "*reversed_tst<mode>"
- [(set (cc0)
- (compare (match_operand:ALL4 0 "const0_operand" "Y00")
+ [(set (reg:CC REG_CC)
+ (compare:CC (match_operand:ALL4 0 "const0_operand" "Y00")
(match_operand:ALL4 1 "register_operand" "r")))
(clobber (match_scratch:QI 2 "=X"))]
- ""
+ "reload_completed"
"cp __zero_reg__,%A1
cpc __zero_reg__,%B1
cpc __zero_reg__,%C1
cpc __zero_reg__,%D1"
- [(set_attr "cc" "compare")
- (set_attr "length" "4")])
+ [(set_attr "length" "4")])
;; "cmpqi3"
;; "cmpqq3" "cmpuqq3"
(define_insn "cmp<mode>3"
- [(set (cc0)
- (compare (match_operand:ALL1 0 "register_operand" "r ,r,d")
+ [(set (reg:CC REG_CC)
+ (compare:CC (match_operand:ALL1 0 "register_operand" "r ,r,d")
(match_operand:ALL1 1 "nonmemory_operand" "Y00,r,i")))]
- ""
+ "reload_completed"
"@
tst %0
cp %0,%1
cpi %0,lo8(%1)"
- [(set_attr "cc" "compare,compare,compare")
- (set_attr "length" "1,1,1")])
+ [(set_attr "length" "1,1,1")])
(define_insn "*cmpqi_sign_extend"
- [(set (cc0)
- (compare (sign_extend:HI (match_operand:QI 0 "register_operand" "d"))
+ [(set (reg:CC REG_CC)
+ (compare:CC (sign_extend:HI (match_operand:QI 0 "register_operand" "d"))
(match_operand:HI 1 "s8_operand" "n")))]
- ""
+ "reload_completed"
"cpi %0,lo8(%1)"
- [(set_attr "cc" "compare")
- (set_attr "length" "1")])
+ [(set_attr "length" "1")])
(define_insn "*cmphi.zero-extend.0"
- [(set (cc0)
- (compare (zero_extend:HI (match_operand:QI 0 "register_operand" "r"))
+ [(set (reg:CC REG_CC)
+ (compare:CC (zero_extend:HI (match_operand:QI 0 "register_operand" "r"))
(match_operand:HI 1 "register_operand" "r")))]
- ""
+ "reload_completed"
"cp %0,%A1\;cpc __zero_reg__,%B1"
- [(set_attr "cc" "compare")
- (set_attr "length" "2")])
+ [(set_attr "length" "2")])
(define_insn "*cmphi.zero-extend.1"
- [(set (cc0)
- (compare (match_operand:HI 0 "register_operand" "r")
+ [(set (reg:CC REG_CC)
+ (compare:CC (match_operand:HI 0 "register_operand" "r")
(zero_extend:HI (match_operand:QI 1 "register_operand" "r"))))]
- ""
+ "reload_completed"
"cp %A0,%1\;cpc %B0,__zero_reg__"
- [(set_attr "cc" "compare")
- (set_attr "length" "2")])
+ [(set_attr "length" "2")])
;; "cmphi3"
;; "cmphq3" "cmpuhq3"
;; "cmpha3" "cmpuha3"
(define_insn "cmp<mode>3"
- [(set (cc0)
- (compare (match_operand:ALL2 0 "register_operand" "!w ,r ,r,d ,r ,d,r")
+ [(set (reg:CC REG_CC)
+ (compare:CC (match_operand:ALL2 0 "register_operand" "!w ,r ,r,d ,r ,d,r")
(match_operand:ALL2 1 "nonmemory_operand" "Y00,Y00,r,s ,s ,M,n Ynn")))
(clobber (match_scratch:QI 2 "=X ,X ,X,&d,&d ,X,&d"))]
- ""
+ "reload_completed"
{
switch (which_alternative)
{
@@ -4749,16 +6535,15 @@
return avr_out_compare (insn, operands, NULL);
}
- [(set_attr "cc" "compare")
- (set_attr "length" "1,2,2,3,4,2,4")
+ [(set_attr "length" "1,2,2,3,4,2,4")
(set_attr "adjust_len" "tsthi,tsthi,*,*,*,compare,compare")])
(define_insn "*cmppsi"
- [(set (cc0)
- (compare (match_operand:PSI 0 "register_operand" "r,r,d ,r ,d,r")
+ [(set (reg:CC REG_CC)
+ (compare:CC (match_operand:PSI 0 "register_operand" "r,r,d ,r ,d,r")
(match_operand:PSI 1 "nonmemory_operand" "L,r,s ,s ,M,n")))
(clobber (match_scratch:QI 2 "=X,X,&d,&d ,X,&d"))]
- ""
+ "reload_completed"
{
switch (which_alternative)
{
@@ -4779,19 +6564,18 @@
return avr_out_compare (insn, operands, NULL);
}
- [(set_attr "cc" "compare")
- (set_attr "length" "3,3,5,6,3,7")
+ [(set_attr "length" "3,3,5,6,3,7")
(set_attr "adjust_len" "tstpsi,*,*,*,compare,compare")])
;; "*cmpsi"
;; "*cmpsq" "*cmpusq"
;; "*cmpsa" "*cmpusa"
(define_insn "*cmp<mode>"
- [(set (cc0)
- (compare (match_operand:ALL4 0 "register_operand" "r ,r ,d,r ,r")
+ [(set (reg:CC REG_CC)
+ (compare:CC (match_operand:ALL4 0 "register_operand" "r ,r ,d,r ,r")
(match_operand:ALL4 1 "nonmemory_operand" "Y00,r ,M,M ,n Ynn")))
(clobber (match_scratch:QI 2 "=X ,X ,X,&d,&d"))]
- ""
+ "reload_completed"
{
if (0 == which_alternative)
return avr_out_tstsi (insn, operands, NULL);
@@ -4800,8 +6584,7 @@
return avr_out_compare (insn, operands, NULL);
}
- [(set_attr "cc" "compare")
- (set_attr "length" "4,4,4,5,8")
+ [(set_attr "length" "4,4,4,5,8")
(set_attr "adjust_len" "tstsi,*,compare,compare,compare")])
@@ -4810,40 +6593,120 @@
;; ----------------------------------------------------------------------
;; Conditional jump instructions
-;; "cbranchqi4"
-;; "cbranchqq4" "cbranchuqq4"
(define_expand "cbranch<mode>4"
- [(set (cc0)
- (compare (match_operand:ALL1 1 "register_operand" "")
- (match_operand:ALL1 2 "nonmemory_operand" "")))
- (set (pc)
- (if_then_else
- (match_operator 0 "ordered_comparison_operator" [(cc0)
- (const_int 0)])
+ [(set (pc)
+ (if_then_else (match_operator 0 "ordered_comparison_operator"
+ [(match_operand:ALL1 1 "register_operand" "")
+ (match_operand:ALL1 2 "nonmemory_operand" "")])
(label_ref (match_operand 3 "" ""))
(pc)))])
-;; "cbranchhi4" "cbranchhq4" "cbranchuhq4" "cbranchha4" "cbranchuha4"
-;; "cbranchsi4" "cbranchsq4" "cbranchusq4" "cbranchsa4" "cbranchusa4"
-;; "cbranchpsi4"
(define_expand "cbranch<mode>4"
- [(parallel [(set (cc0)
- (compare (match_operand:ORDERED234 1 "register_operand" "")
- (match_operand:ORDERED234 2 "nonmemory_operand" "")))
- (clobber (match_scratch:QI 4 ""))])
- (set (pc)
- (if_then_else
- (match_operator 0 "ordered_comparison_operator" [(cc0)
- (const_int 0)])
+ [(parallel
+ [(set (pc)
+ (if_then_else
+ (match_operator 0 "ordered_comparison_operator"
+ [(match_operand:ORDERED234 1 "register_operand" "")
+ (match_operand:ORDERED234 2 "nonmemory_operand" "")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))
+ (clobber (match_scratch:QI 4 ""))])])
+
+;; "*cbranchqi4"
+;; "*cbranchqq4" "*cbranchuqq4"
+(define_insn_and_split "*cbranch<mode>4"
+ [(set (pc)
+ (if_then_else (match_operator 0 "ordered_comparison_operator"
+ [(match_operand:ALL1 1 "register_operand" "r ,r,d")
+ (match_operand:ALL1 2 "nonmemory_operand" "Y00,r,i")])
(label_ref (match_operand 3 "" ""))
- (pc)))])
-
+ (pc)))]
+ ""
+ "#"
+ "reload_completed"
+ [(set (reg:CC REG_CC)
+ (compare:CC (match_dup 1) (match_dup 2)))
+ (set (pc)
+ (if_then_else (match_op_dup 0
+ [(reg:CC REG_CC) (const_int 0)])
+ (label_ref (match_dup 3))
+ (pc)))]
+ "")
+
+;; "*cbranchsi4" "*cbranchsq4" "*cbranchusq4" "*cbranchsa4" "*cbranchusa4"
+(define_insn_and_split "*cbranch<mode>4"
+ [(set (pc)
+ (if_then_else
+ (match_operator 0 "ordered_comparison_operator"
+ [(match_operand:ALL4 1 "register_operand" "r ,r ,d,r ,r")
+ (match_operand:ALL4 2 "nonmemory_operand" "Y00,r ,M,M ,n Ynn")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))
+ (clobber (match_scratch:QI 4 "=X ,X ,X,&d,&d"))]
+ ""
+ "#"
+ "reload_completed"
+ [(parallel [(set (reg:CC REG_CC)
+ (compare:CC (match_dup 1) (match_dup 2)))
+ (clobber (match_dup 4))])
+ (set (pc)
+ (if_then_else (match_op_dup 0
+ [(reg:CC REG_CC) (const_int 0)])
+ (label_ref (match_dup 3))
+ (pc)))]
+ "")
+
+;; "*cbranchpsi4"
+(define_insn_and_split "*cbranchpsi4"
+ [(set (pc)
+ (if_then_else
+ (match_operator 0 "ordered_comparison_operator"
+ [(match_operand:PSI 1 "register_operand" "r,r,d ,r ,d,r")
+ (match_operand:PSI 2 "nonmemory_operand" "L,r,s ,s ,M,n")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))
+ (clobber (match_scratch:QI 4 "=X,X,&d,&d ,X,&d"))]
+ ""
+ "#"
+ "reload_completed"
+ [(parallel [(set (reg:CC REG_CC)
+ (compare:CC (match_dup 1) (match_dup 2)))
+ (clobber (match_dup 4))])
+ (set (pc)
+ (if_then_else (match_op_dup 0
+ [(reg:CC REG_CC) (const_int 0)])
+ (label_ref (match_dup 3))
+ (pc)))]
+ "")
+
+;; "*cbranchhi4" "*cbranchhq4" "*cbranchuhq4" "*cbranchha4" "*cbranchuha4"
+(define_insn_and_split "*cbranch<mode>4"
+ [(set (pc)
+ (if_then_else
+ (match_operator 0 "ordered_comparison_operator"
+ [(match_operand:ALL2 1 "register_operand" "!w ,r ,r,d ,r ,d,r")
+ (match_operand:ALL2 2 "nonmemory_operand" "Y00,Y00,r,s ,s ,M,n Ynn")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))
+ (clobber (match_scratch:QI 4 "=X ,X ,X,&d,&d ,X,&d"))]
+ ""
+ "#"
+ "reload_completed"
+ [(parallel [(set (reg:CC REG_CC)
+ (compare:CC (match_dup 1) (match_dup 2)))
+ (clobber (match_dup 4))])
+ (set (pc)
+ (if_then_else (match_op_dup 0
+ [(reg:CC REG_CC) (const_int 0)])
+ (label_ref (match_dup 3))
+ (pc)))]
+ "")
;; Test a single bit in a QI/HI/SImode register.
;; Combine will create zero extract patterns for single bit tests.
;; permit any mode in source pattern by using VOIDmode.
-(define_insn "*sbrx_branch<mode>"
+(define_insn_and_split "*sbrx_branch<mode>_split"
[(set (pc)
(if_then_else
(match_operator 0 "eqne_operator"
@@ -4855,6 +6718,33 @@
(label_ref (match_operand 3 "" ""))
(pc)))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (pc)
+ (if_then_else
+ (match_op_dup 0
+ [(zero_extract:QIDI
+ (match_dup 1)
+ (const_int 1)
+ (match_dup 2))
+ (const_int 0)])
+ (label_ref (match_dup 3))
+ (pc)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*sbrx_branch<mode>"
+ [(set (pc)
+ (if_then_else
+ (match_operator 0 "eqne_operator"
+ [(zero_extract:QIDI
+ (match_operand:VOID 1 "register_operand" "r")
+ (const_int 1)
+ (match_operand 2 "const_int_operand" "n"))
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return avr_out_sbxx_branch (insn, operands);
}
@@ -4864,14 +6754,13 @@
(const_int 2)
(if_then_else (match_test "!AVR_HAVE_JMP_CALL")
(const_int 2)
- (const_int 4))))
- (set_attr "cc" "clobber")])
+ (const_int 4))))])
;; Same test based on bitwise AND. Keep this in case gcc changes patterns.
;; or for old peepholes.
;; Fixme - bitwise Mask will not work for DImode
-(define_insn "*sbrx_and_branch<mode>"
+(define_insn_and_split "*sbrx_and_branch<mode>_split"
[(set (pc)
(if_then_else
(match_operator 0 "eqne_operator"
@@ -4882,6 +6771,31 @@
(label_ref (match_operand 3 "" ""))
(pc)))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (pc)
+ (if_then_else
+ (match_op_dup 0
+ [(and:QISI
+ (match_dup 1)
+ (match_dup 2))
+ (const_int 0)])
+ (label_ref (match_dup 3))
+ (pc)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*sbrx_and_branch<mode>"
+ [(set (pc)
+ (if_then_else
+ (match_operator 0 "eqne_operator"
+ [(and:QISI
+ (match_operand:QISI 1 "register_operand" "r")
+ (match_operand:QISI 2 "single_one_operand" "n"))
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
HOST_WIDE_INT bitnumber;
bitnumber = exact_log2 (GET_MODE_MASK (<MODE>mode) & INTVAL (operands[2]));
@@ -4894,14 +6808,13 @@
(const_int 2)
(if_then_else (match_test "!AVR_HAVE_JMP_CALL")
(const_int 2)
- (const_int 4))))
- (set_attr "cc" "clobber")])
+ (const_int 4))))])
;; Convert sign tests to bit 7/15/31 tests that match the above insns.
(define_peephole2
- [(set (cc0) (compare (match_operand:QI 0 "register_operand" "")
+ [(set (reg:CC REG_CC) (compare:CC (match_operand:QI 0 "register_operand" "")
(const_int 0)))
- (set (pc) (if_then_else (ge (cc0) (const_int 0))
+ (set (pc) (if_then_else (ge (reg:CC REG_CC) (const_int 0))
(label_ref (match_operand 1 "" ""))
(pc)))]
""
@@ -4913,9 +6826,9 @@
(pc)))])
(define_peephole2
- [(set (cc0) (compare (match_operand:QI 0 "register_operand" "")
+ [(set (reg:CC REG_CC) (compare:CC (match_operand:QI 0 "register_operand" "")
(const_int 0)))
- (set (pc) (if_then_else (lt (cc0) (const_int 0))
+ (set (pc) (if_then_else (lt (reg:CC REG_CC) (const_int 0))
(label_ref (match_operand 1 "" ""))
(pc)))]
""
@@ -4927,10 +6840,10 @@
(pc)))])
(define_peephole2
- [(parallel [(set (cc0) (compare (match_operand:HI 0 "register_operand" "")
+ [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:HI 0 "register_operand" "")
(const_int 0)))
(clobber (match_operand:HI 2 ""))])
- (set (pc) (if_then_else (ge (cc0) (const_int 0))
+ (set (pc) (if_then_else (ge (reg:CC REG_CC) (const_int 0))
(label_ref (match_operand 1 "" ""))
(pc)))]
""
@@ -4940,10 +6853,10 @@
(pc)))])
(define_peephole2
- [(parallel [(set (cc0) (compare (match_operand:HI 0 "register_operand" "")
+ [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:HI 0 "register_operand" "")
(const_int 0)))
(clobber (match_operand:HI 2 ""))])
- (set (pc) (if_then_else (lt (cc0) (const_int 0))
+ (set (pc) (if_then_else (lt (reg:CC REG_CC) (const_int 0))
(label_ref (match_operand 1 "" ""))
(pc)))]
""
@@ -4953,10 +6866,10 @@
(pc)))])
(define_peephole2
- [(parallel [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
+ [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:SI 0 "register_operand" "")
(const_int 0)))
(clobber (match_operand:SI 2 ""))])
- (set (pc) (if_then_else (ge (cc0) (const_int 0))
+ (set (pc) (if_then_else (ge (reg:CC REG_CC) (const_int 0))
(label_ref (match_operand 1 "" ""))
(pc)))]
""
@@ -4967,10 +6880,10 @@
"operands[2] = gen_int_mode (-2147483647 - 1, SImode);")
(define_peephole2
- [(parallel [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
+ [(parallel [(set (reg:CC REG_CC) (compare:CC (match_operand:SI 0 "register_operand" "")
(const_int 0)))
(clobber (match_operand:SI 2 ""))])
- (set (pc) (if_then_else (lt (cc0) (const_int 0))
+ (set (pc) (if_then_else (lt (reg:CC REG_CC) (const_int 0))
(label_ref (match_operand 1 "" ""))
(pc)))]
""
@@ -4985,19 +6898,37 @@
;; Compare with 0 (test) jumps
;; ************************************************************************
-(define_insn "branch"
+(define_insn_and_split "branch"
[(set (pc)
(if_then_else (match_operator 1 "simple_comparison_operator"
- [(cc0)
+ [(reg:CC REG_CC)
(const_int 0)])
(label_ref (match_operand 0 "" ""))
(pc)))]
- ""
+ "reload_completed"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (pc)
+ (if_then_else (match_op_dup 1
+ [(reg:CC REG_CC)
+ (const_int 0)])
+ (label_ref (match_dup 0))
+ (pc)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*branch"
+ [(set (pc)
+ (if_then_else (match_operator 1 "simple_comparison_operator"
+ [(reg:CC REG_CC)
+ (const_int 0)])
+ (label_ref (match_operand 0 "" ""))
+ (pc)))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 0);
}
- [(set_attr "type" "branch")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "branch")])
;; Same as above but wrap SET_SRC so that this branch won't be transformed
@@ -5006,66 +6937,119 @@
(define_insn "branch_unspec"
[(set (pc)
(unspec [(if_then_else (match_operator 1 "simple_comparison_operator"
- [(cc0)
+ [(reg:CC REG_CC)
(const_int 0)])
(label_ref (match_operand 0 "" ""))
(pc))
] UNSPEC_IDENTITY))]
- ""
+ "reload_completed"
{
return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 0);
}
- [(set_attr "type" "branch")
- (set_attr "cc" "none")])
+ [(set_attr "type" "branch")])
;; ****************************************************************
;; AVR does not have following conditional jumps: LE,LEU,GT,GTU.
;; Convert them all to proper jumps.
;; ****************************************************************/
-(define_insn "difficult_branch"
+(define_insn_and_split "difficult_branch"
+ [(set (pc)
+ (if_then_else (match_operator 1 "difficult_comparison_operator"
+ [(reg:CC REG_CC)
+ (const_int 0)])
+ (label_ref (match_operand 0 "" ""))
+ (pc)))]
+ "reload_completed"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (pc)
+ (if_then_else (match_op_dup 1
+ [(reg:CC REG_CC)
+ (const_int 0)])
+ (label_ref (match_dup 0))
+ (pc)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*difficult_branch"
[(set (pc)
(if_then_else (match_operator 1 "difficult_comparison_operator"
- [(cc0)
+ [(reg:CC REG_CC)
(const_int 0)])
(label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
+ (pc)))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 0);
}
- [(set_attr "type" "branch1")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "branch1")])
;; revers branch
-(define_insn "rvbranch"
+(define_insn_and_split "rvbranch"
[(set (pc)
(if_then_else (match_operator 1 "simple_comparison_operator"
- [(cc0)
+ [(reg:CC REG_CC)
(const_int 0)])
(pc)
(label_ref (match_operand 0 "" ""))))]
- ""
+ "reload_completed"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (pc)
+ (if_then_else (match_op_dup 1
+ [(reg:CC REG_CC)
+ (const_int 0)])
+ (pc)
+ (label_ref (match_dup 0))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*rvbranch"
+ [(set (pc)
+ (if_then_else (match_operator 1 "simple_comparison_operator"
+ [(reg:CC REG_CC)
+ (const_int 0)])
+ (pc)
+ (label_ref (match_operand 0 "" ""))))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);
}
- [(set_attr "type" "branch1")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "branch1")])
-(define_insn "difficult_rvbranch"
+(define_insn_and_split "difficult_rvbranch"
[(set (pc)
(if_then_else (match_operator 1 "difficult_comparison_operator"
- [(cc0)
+ [(reg:CC REG_CC)
(const_int 0)])
(pc)
(label_ref (match_operand 0 "" ""))))]
- ""
+ "reload_completed"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (pc)
+ (if_then_else (match_op_dup 1
+ [(reg:CC REG_CC)
+ (const_int 0)])
+ (pc)
+ (label_ref (match_dup 0))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*difficult_rvbranch"
+ [(set (pc)
+ (if_then_else (match_operator 1 "difficult_comparison_operator"
+ [(reg:CC REG_CC)
+ (const_int 0)])
+ (pc)
+ (label_ref (match_operand 0 "" ""))))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);
}
- [(set_attr "type" "branch")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "branch")])
;; **************************************************************************
;; Unconditional and other jump instructions.
@@ -5087,8 +7071,7 @@
(if_then_else (and (ge (minus (pc) (match_dup 0)) (const_int -2047))
(le (minus (pc) (match_dup 0)) (const_int 2047)))
(const_int 1)
- (const_int 2))))
- (set_attr "cc" "none")])
+ (const_int 2))))])
;; call
@@ -5124,23 +7107,37 @@
(match_operand:HI 2 "general_operand" "")))
(use (const_int 1))])])
-(define_insn "call_insn"
+(define_insn_and_split "call_insn"
[(parallel[(call (mem:HI (match_operand:HI 0 "nonmemory_operand" "z,s,z,s"))
(match_operand:HI 1 "general_operand" "X,X,X,X"))
(use (match_operand:HI 2 "const_int_operand" "L,L,P,P"))])]
;; Operand 1 not used on the AVR.
;; Operand 2 is 1 for tail-call, 0 otherwise.
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(call (mem:HI (match_dup 0))
+ (match_dup 1))
+ (use (match_dup 2))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*call_insn"
+ [(call (mem:HI (match_operand:HI 0 "nonmemory_operand" "z,s,z,s"))
+ (match_operand:HI 1 "general_operand" "X,X,X,X"))
+ (use (match_operand:HI 2 "const_int_operand" "L,L,P,P"))
+ (clobber (reg:CC REG_CC))]
+ ;; Operand 1 not used on the AVR.
+ ;; Operand 2 is 1 for tail-call, 0 otherwise.
+ "reload_completed"
"@
%!icall
%~call %x0
%!ijmp
%~jmp %x0"
- [(set_attr "cc" "clobber")
- (set_attr "length" "1,*,1,*")
+ [(set_attr "length" "1,*,1,*")
(set_attr "adjust_len" "*,call,*,call")])
-(define_insn "call_value_insn"
+(define_insn_and_split "call_value_insn"
[(parallel[(set (match_operand 0 "register_operand" "=r,r,r,r")
(call (mem:HI (match_operand:HI 1 "nonmemory_operand" "z,s,z,s"))
(match_operand:HI 2 "general_operand" "X,X,X,X")))
@@ -5148,21 +7145,36 @@
;; Operand 2 not used on the AVR.
;; Operand 3 is 1 for tail-call, 0 otherwise.
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (call (mem:HI (match_dup 1))
+ (match_dup 2)))
+ (use (match_dup 3))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*call_value_insn"
+ [(set (match_operand 0 "register_operand" "=r,r,r,r")
+ (call (mem:HI (match_operand:HI 1 "nonmemory_operand" "z,s,z,s"))
+ (match_operand:HI 2 "general_operand" "X,X,X,X")))
+ (use (match_operand:HI 3 "const_int_operand" "L,L,P,P"))
+ (clobber (reg:CC REG_CC))]
+ ;; Operand 2 not used on the AVR.
+ ;; Operand 3 is 1 for tail-call, 0 otherwise.
+ "reload_completed"
"@
%!icall
%~call %x1
%!ijmp
%~jmp %x1"
- [(set_attr "cc" "clobber")
- (set_attr "length" "1,*,1,*")
+ [(set_attr "length" "1,*,1,*")
(set_attr "adjust_len" "*,call,*,call")])
(define_insn "nop"
[(const_int 0)]
""
"nop"
- [(set_attr "cc" "none")
- (set_attr "length" "1")])
+ [(set_attr "length" "1")])
; indirect jump
@@ -5189,8 +7201,7 @@
push %A0\;push %B0\;ret
eijmp"
[(set_attr "length" "1,2,1,3,1")
- (set_attr "isa" "rjmp,jmp,ijmp,ijmp,eijmp")
- (set_attr "cc" "none")])
+ (set_attr "isa" "rjmp,jmp,ijmp,ijmp,eijmp")])
;; table jump
;; For entries in jump table see avr_output_addr_vec.
@@ -5198,23 +7209,41 @@
;; Table made from
;; "rjmp .L<n>" instructions for <= 8K devices
;; ".word gs(.L<n>)" addresses for > 8K devices
-(define_insn "*tablejump"
+(define_insn_and_split "*tablejump_split"
[(set (pc)
- (unspec:HI [(match_operand:HI 0 "register_operand" "!z,*r,z")]
+ (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
UNSPEC_INDEX_JMP))
(use (label_ref (match_operand 1 "" "")))
(clobber (match_dup 0))
(clobber (const_int 0))]
"!AVR_HAVE_EIJMP_EICALL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (pc)
+ (unspec:HI [(match_dup 0)]
+ UNSPEC_INDEX_JMP))
+ (use (label_ref (match_dup 1)))
+ (clobber (match_dup 0))
+ (clobber (const_int 0))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*tablejump"
+ [(set (pc)
+ (unspec:HI [(match_operand:HI 0 "register_operand" "!z,*r,z")]
+ UNSPEC_INDEX_JMP))
+ (use (label_ref (match_operand 1 "" "")))
+ (clobber (match_dup 0))
+ (clobber (const_int 0))
+ (clobber (reg:CC REG_CC))]
+ "!AVR_HAVE_EIJMP_EICALL && reload_completed"
"@
ijmp
push %A0\;push %B0\;ret
jmp __tablejump2__"
[(set_attr "length" "1,3,2")
- (set_attr "isa" "rjmp,rjmp,jmp")
- (set_attr "cc" "none,none,clobber")])
+ (set_attr "isa" "rjmp,rjmp,jmp")])
-(define_insn "*tablejump.3byte-pc"
+(define_insn_and_split "*tablejump.3byte-pc_split"
[(set (pc)
(unspec:HI [(reg:HI REG_Z)]
UNSPEC_INDEX_JMP))
@@ -5222,10 +7251,28 @@
(clobber (reg:HI REG_Z))
(clobber (reg:QI 24))]
"AVR_HAVE_EIJMP_EICALL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (pc)
+ (unspec:HI [(reg:HI REG_Z)]
+ UNSPEC_INDEX_JMP))
+ (use (label_ref (match_dup 0)))
+ (clobber (reg:HI REG_Z))
+ (clobber (reg:QI 24))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*tablejump.3byte-pc"
+ [(set (pc)
+ (unspec:HI [(reg:HI REG_Z)]
+ UNSPEC_INDEX_JMP))
+ (use (label_ref (match_operand 0 "" "")))
+ (clobber (reg:HI REG_Z))
+ (clobber (reg:QI 24))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_EIJMP_EICALL && reload_completed"
"clr r24\;subi r30,pm_lo8(-(%0))\;sbci r31,pm_hi8(-(%0))\;sbci r24,pm_hh8(-(%0))\;jmp __tablejump2__"
[(set_attr "length" "6")
- (set_attr "isa" "eijmp")
- (set_attr "cc" "clobber")])
+ (set_attr "isa" "eijmp")])
;; FIXME: casesi comes up with an SImode switch value $0 which
@@ -5254,16 +7301,13 @@
(plus:SI (match_operand:SI 0 "register_operand")
(match_operand:SI 1 "const_int_operand")))
(clobber (scratch:QI))])
- (parallel [(set (cc0)
- (compare (match_dup 5)
- (match_operand:SI 2 "const_int_operand")))
- (clobber (scratch:QI))])
- (set (pc)
- (if_then_else (gtu (cc0)
- (const_int 0))
- (label_ref (match_operand 4))
- (pc)))
+ (parallel [(set (pc)
+ (if_then_else (gtu (match_dup 5)
+ (match_operand:SI 2 "const_int_operand"))
+ (label_ref (match_operand 4))
+ (pc)))
+ (clobber (scratch:QI))])
(set (match_dup 7)
(match_dup 6))
@@ -5312,16 +7356,13 @@
(plus:SI (match_dup 0)
(match_operand:SI 1 "const_int_operand")))
(clobber (scratch:QI))])
- (parallel [(set (cc0)
- (compare (match_dup 5)
- (match_operand:SI 2 "const_int_operand")))
- (clobber (scratch:QI))])
- (set (pc)
- (if_then_else (gtu (cc0)
- (const_int 0))
- (label_ref (match_operand 4))
- (pc)))
+ (parallel [(set (pc)
+ (if_then_else (gtu (match_dup 5)
+ (match_operand:SI 2 "const_int_operand"))
+ (label_ref (match_operand 4))
+ (pc)))
+ (clobber (scratch:QI))])
(set (match_operand:HI 7 "register_operand")
(match_operand:HI 6))
@@ -5341,11 +7382,10 @@
;; This instruction sets Z flag
(define_insn "sez"
- [(set (cc0) (const_int 0))]
- ""
+ [(set (reg:CC REG_CC) (const_int 0))]
+ "reload_completed"
"sez"
- [(set_attr "length" "1")
- (set_attr "cc" "compare")])
+ [(set_attr "length" "1")])
;; Clear/set/test a single bit in I/O address space.
@@ -5358,8 +7398,7 @@
operands[2] = GEN_INT (exact_log2 (~INTVAL (operands[1]) & 0xff));
return "cbi %i0,%2";
}
- [(set_attr "length" "1")
- (set_attr "cc" "none")])
+ [(set_attr "length" "1")])
(define_insn "*sbi"
[(set (mem:QI (match_operand 0 "low_io_address_operand" "i"))
@@ -5370,11 +7409,10 @@
operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1]) & 0xff));
return "sbi %i0,%2";
}
- [(set_attr "length" "1")
- (set_attr "cc" "none")])
+ [(set_attr "length" "1")])
;; Lower half of the I/O space - use sbic/sbis directly.
-(define_insn "*sbix_branch"
+(define_insn_and_split "*sbix_branch_split"
[(set (pc)
(if_then_else
(match_operator 0 "eqne_operator"
@@ -5386,6 +7424,33 @@
(label_ref (match_operand 3 "" ""))
(pc)))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (pc)
+ (if_then_else
+ (match_operator 0 "eqne_operator"
+ [(zero_extract:QIHI
+ (mem:QI (match_dup 1))
+ (const_int 1)
+ (match_dup 2))
+ (const_int 0)])
+ (label_ref (match_dup 3))
+ (pc)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*sbix_branch"
+ [(set (pc)
+ (if_then_else
+ (match_operator 0 "eqne_operator"
+ [(zero_extract:QIHI
+ (mem:QI (match_operand 1 "low_io_address_operand" "i"))
+ (const_int 1)
+ (match_operand 2 "const_int_operand" "n"))
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return avr_out_sbxx_branch (insn, operands);
}
@@ -5395,11 +7460,10 @@
(const_int 2)
(if_then_else (match_test "!AVR_HAVE_JMP_CALL")
(const_int 2)
- (const_int 4))))
- (set_attr "cc" "clobber")])
+ (const_int 4))))])
;; Tests of bit 7 are pessimized to sign tests, so we need this too...
-(define_insn "*sbix_branch_bit7"
+(define_insn_and_split "*sbix_branch_bit7_split"
[(set (pc)
(if_then_else
(match_operator 0 "gelt_operator"
@@ -5408,6 +7472,27 @@
(label_ref (match_operand 2 "" ""))
(pc)))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (pc)
+ (if_then_else
+ (match_operator 0 "gelt_operator"
+ [(mem:QI (match_dup 1))
+ (const_int 0)])
+ (label_ref (match_dup 2))
+ (pc)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*sbix_branch_bit7"
+ [(set (pc)
+ (if_then_else
+ (match_operator 0 "gelt_operator"
+ [(mem:QI (match_operand 1 "low_io_address_operand" "i"))
+ (const_int 0)])
+ (label_ref (match_operand 2 "" ""))
+ (pc)))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
operands[3] = operands[2];
operands[2] = GEN_INT (7);
@@ -5419,11 +7504,10 @@
(const_int 2)
(if_then_else (match_test "!AVR_HAVE_JMP_CALL")
(const_int 2)
- (const_int 4))))
- (set_attr "cc" "clobber")])
+ (const_int 4))))])
;; Upper half of the I/O space - read port to __tmp_reg__ and use sbrc/sbrs.
-(define_insn "*sbix_branch_tmp"
+(define_insn_and_split "*sbix_branch_tmp_split"
[(set (pc)
(if_then_else
(match_operator 0 "eqne_operator"
@@ -5435,6 +7519,33 @@
(label_ref (match_operand 3 "" ""))
(pc)))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (pc)
+ (if_then_else
+ (match_operator 0 "eqne_operator"
+ [(zero_extract:QIHI
+ (mem:QI (match_dup 1))
+ (const_int 1)
+ (match_dup 2))
+ (const_int 0)])
+ (label_ref (match_dup 3))
+ (pc)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*sbix_branch_tmp"
+ [(set (pc)
+ (if_then_else
+ (match_operator 0 "eqne_operator"
+ [(zero_extract:QIHI
+ (mem:QI (match_operand 1 "high_io_address_operand" "n"))
+ (const_int 1)
+ (match_operand 2 "const_int_operand" "n"))
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return avr_out_sbxx_branch (insn, operands);
}
@@ -5444,10 +7555,9 @@
(const_int 3)
(if_then_else (match_test "!AVR_HAVE_JMP_CALL")
(const_int 3)
- (const_int 5))))
- (set_attr "cc" "clobber")])
+ (const_int 5))))])
-(define_insn "*sbix_branch_tmp_bit7"
+(define_insn_and_split "*sbix_branch_tmp_bit7_split"
[(set (pc)
(if_then_else
(match_operator 0 "gelt_operator"
@@ -5456,6 +7566,27 @@
(label_ref (match_operand 2 "" ""))
(pc)))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (pc)
+ (if_then_else
+ (match_operator 0 "gelt_operator"
+ [(mem:QI (match_dup 1))
+ (const_int 0)])
+ (label_ref (match_dup 2))
+ (pc)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*sbix_branch_tmp_bit7"
+ [(set (pc)
+ (if_then_else
+ (match_operator 0 "gelt_operator"
+ [(mem:QI (match_operand 1 "high_io_address_operand" "n"))
+ (const_int 0)])
+ (label_ref (match_operand 2 "" ""))
+ (pc)))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
operands[3] = operands[2];
operands[2] = GEN_INT (7);
@@ -5467,8 +7598,7 @@
(const_int 3)
(if_then_else (match_test "!AVR_HAVE_JMP_CALL")
(const_int 3)
- (const_int 5))))
- (set_attr "cc" "clobber")])
+ (const_int 5))))])
;; ************************* Peepholes ********************************
@@ -5477,12 +7607,12 @@
(plus:SI (match_dup 0)
(const_int -1)))
(clobber (scratch:QI))])
- (parallel [(set (cc0)
- (compare (match_dup 0)
+ (parallel [(set (reg:CC REG_CC)
+ (compare:CC (match_dup 0)
(const_int -1)))
(clobber (match_operand:QI 1 "d_register_operand" ""))])
(set (pc)
- (if_then_else (eqne (cc0)
+ (if_then_else (eqne (reg:CC REG_CC)
(const_int 0))
(label_ref (match_operand 2 "" ""))
(pc)))]
@@ -5520,12 +7650,12 @@
[(set (match_operand:HI 0 "d_register_operand" "")
(plus:HI (match_dup 0)
(const_int -1)))
- (parallel [(set (cc0)
- (compare (match_dup 0)
+ (parallel [(set (reg:CC REG_CC)
+ (compare:CC (match_dup 0)
(const_int -1)))
(clobber (match_operand:QI 1 "d_register_operand" ""))])
(set (pc)
- (if_then_else (eqne (cc0)
+ (if_then_else (eqne (reg:CC REG_CC)
(const_int 0))
(label_ref (match_operand 2 "" ""))
(pc)))]
@@ -5561,12 +7691,12 @@
(plus:HI (match_dup 0)
(const_int -1)))
(clobber (scratch:QI))])
- (parallel [(set (cc0)
- (compare (match_dup 0)
+ (parallel [(set (reg:CC REG_CC)
+ (compare:CC (match_dup 0)
(const_int -1)))
(clobber (match_operand:QI 1 "d_register_operand" ""))])
(set (pc)
- (if_then_else (eqne (cc0)
+ (if_then_else (eqne (reg:CC REG_CC)
(const_int 0))
(label_ref (match_operand 2 "" ""))
(pc)))]
@@ -5602,12 +7732,12 @@
(plus:HI (match_dup 0)
(const_int -1)))
(clobber (match_operand:QI 3 "d_register_operand" ""))])
- (parallel [(set (cc0)
- (compare (match_dup 0)
+ (parallel [(set (reg:CC REG_CC)
+ (compare:CC (match_dup 0)
(const_int -1)))
(clobber (match_operand:QI 1 "d_register_operand" ""))])
(set (pc)
- (if_then_else (eqne (cc0)
+ (if_then_else (eqne (reg:CC REG_CC)
(const_int 0))
(label_ref (match_operand 2 "" ""))
(pc)))]
@@ -5639,11 +7769,11 @@
[(set (match_operand:QI 0 "d_register_operand" "")
(plus:QI (match_dup 0)
(const_int -1)))
- (set (cc0)
- (compare (match_dup 0)
+ (set (reg:CC REG_CC)
+ (compare:CC (match_dup 0)
(const_int -1)))
(set (pc)
- (if_then_else (eqne (cc0)
+ (if_then_else (eqne (reg:CC REG_CC)
(const_int 0))
(label_ref (match_operand 1 "" ""))
(pc)))]
@@ -5674,11 +7804,11 @@
(define_peephole ; "*cpse.eq"
- [(set (cc0)
- (compare (match_operand:ALL1 1 "register_operand" "r,r")
+ [(set (reg:CC REG_CC)
+ (compare:CC (match_operand:ALL1 1 "register_operand" "r,r")
(match_operand:ALL1 2 "reg_or_0_operand" "r,Y00")))
(set (pc)
- (if_then_else (eq (cc0)
+ (if_then_else (eq (reg:CC REG_CC)
(const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
@@ -5709,11 +7839,11 @@
;; and thus longer and slower and not easy to be rolled back.
(define_peephole ; "*cpse.ne"
- [(set (cc0)
- (compare (match_operand:ALL1 1 "register_operand" "")
+ [(set (reg:CC REG_CC)
+ (compare:CC (match_operand:ALL1 1 "register_operand" "")
(match_operand:ALL1 2 "reg_or_0_operand" "")))
(set (pc)
- (if_then_else (ne (cc0)
+ (if_then_else (ne (reg:CC REG_CC)
(const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
@@ -5736,8 +7866,7 @@
(mem:QI (pre_inc:HI (reg:HI REG_SP))))]
""
"pop %0"
- [(set_attr "cc" "none")
- (set_attr "length" "1")])
+ [(set_attr "length" "1")])
;; Enable Interrupts
(define_expand "enable_interrupt"
@@ -5770,11 +7899,10 @@
"@
cli
sei"
- [(set_attr "length" "1")
- (set_attr "cc" "none")])
+ [(set_attr "length" "1")])
;; Library prologue saves
-(define_insn "call_prologue_saves"
+(define_insn_and_split "*call_prologue_saves"
[(unspec_volatile:HI [(const_int 0)] UNSPECV_PROLOGUE_SAVES)
(match_operand:HI 0 "immediate_operand" "i,i")
(set (reg:HI REG_SP)
@@ -5783,16 +7911,36 @@
(use (reg:HI REG_X))
(clobber (reg:HI REG_Z))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(unspec_volatile:HI [(const_int 0)] UNSPECV_PROLOGUE_SAVES)
+ (match_dup 0)
+ (set (reg:HI REG_SP)
+ (minus:HI (reg:HI REG_SP)
+ (match_dup 1)))
+ (use (reg:HI REG_X))
+ (clobber (reg:HI REG_Z))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "call_prologue_saves"
+ [(unspec_volatile:HI [(const_int 0)] UNSPECV_PROLOGUE_SAVES)
+ (match_operand:HI 0 "immediate_operand" "i,i")
+ (set (reg:HI REG_SP)
+ (minus:HI (reg:HI REG_SP)
+ (match_operand:HI 1 "immediate_operand" "i,i")))
+ (use (reg:HI REG_X))
+ (clobber (reg:HI REG_Z))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"ldi r30,lo8(gs(1f))
ldi r31,hi8(gs(1f))
%~jmp __prologue_saves__+((18 - %0) * 2)
1:"
[(set_attr "length" "5,6")
- (set_attr "cc" "clobber")
(set_attr "isa" "rjmp,jmp")])
; epilogue restores using library
-(define_insn "epilogue_restores"
+(define_insn_and_split "*epilogue_restores"
[(unspec_volatile:QI [(const_int 0)] UNSPECV_EPILOGUE_RESTORES)
(set (reg:HI REG_Y)
(plus:HI (reg:HI REG_Y)
@@ -5802,10 +7950,32 @@
(match_dup 0)))
(clobber (reg:QI REG_Z))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(unspec_volatile:QI [(const_int 0)] UNSPECV_EPILOGUE_RESTORES)
+ (set (reg:HI REG_Y)
+ (plus:HI (reg:HI REG_Y)
+ (match_dup 0)))
+ (set (reg:HI REG_SP)
+ (plus:HI (reg:HI REG_Y)
+ (match_dup 0)))
+ (clobber (reg:QI REG_Z))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "epilogue_restores"
+ [(unspec_volatile:QI [(const_int 0)] UNSPECV_EPILOGUE_RESTORES)
+ (set (reg:HI REG_Y)
+ (plus:HI (reg:HI REG_Y)
+ (match_operand:HI 0 "immediate_operand" "i,i")))
+ (set (reg:HI REG_SP)
+ (plus:HI (reg:HI REG_Y)
+ (match_dup 0)))
+ (clobber (reg:QI REG_Z))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"ldi r30, lo8(%0)
%~jmp __epilogue_restores__ + ((18 - %0) * 2)"
[(set_attr "length" "2,3")
- (set_attr "cc" "clobber")
(set_attr "isa" "rjmp,jmp")])
@@ -5826,7 +7996,7 @@
MEM_VOLATILE_P (operands[2]) = 1;
})
-(define_insn "*gasisr"
+(define_insn_and_split "*gasisr_split"
[(unspec_volatile [(match_operand:QI 0 "const_int_operand" "P,K")
(match_operand:QI 1 "const_int_operand" "n,n")]
UNSPECV_GASISR)
@@ -5835,9 +8005,29 @@
(set (match_operand:BLK 2)
(unspec_volatile:BLK [(match_dup 2)] UNSPECV_MEMORY_BARRIER))]
"avr_gasisr_prologues"
+ "#"
+ "&& reload_completed"
+ [(parallel [(unspec_volatile [(match_dup 0)
+ (match_dup 1)]
+ UNSPECV_GASISR)
+ (set (reg:HI REG_SP)
+ (unspec_volatile:HI [(reg:HI REG_SP)] UNSPECV_GASISR))
+ (set (match_dup 2)
+ (unspec_volatile:BLK [(match_dup 2)] UNSPECV_MEMORY_BARRIER))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*gasisr"
+ [(unspec_volatile [(match_operand:QI 0 "const_int_operand" "P,K")
+ (match_operand:QI 1 "const_int_operand" "n,n")]
+ UNSPECV_GASISR)
+ (set (reg:HI REG_SP)
+ (unspec_volatile:HI [(reg:HI REG_SP)] UNSPECV_GASISR))
+ (set (match_operand:BLK 2)
+ (unspec_volatile:BLK [(match_dup 2)] UNSPECV_MEMORY_BARRIER))
+ (clobber (reg:CC REG_CC))]
+ "avr_gasisr_prologues && reload_completed"
"__gcc_isr %0"
- [(set_attr "length" "6,5")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "6,5")])
; return
@@ -5845,8 +8035,7 @@
[(return)]
"reload_completed && avr_simple_epilogue ()"
"ret"
- [(set_attr "cc" "none")
- (set_attr "length" "1")])
+ [(set_attr "length" "1")])
(define_insn "return_from_epilogue"
[(return)]
@@ -5855,8 +8044,7 @@
&& !(cfun->machine->is_interrupt || cfun->machine->is_signal)
&& !cfun->machine->is_naked"
"ret"
- [(set_attr "cc" "none")
- (set_attr "length" "1")])
+ [(set_attr "length" "1")])
(define_insn "return_from_interrupt_epilogue"
[(return)]
@@ -5865,8 +8053,7 @@
&& (cfun->machine->is_interrupt || cfun->machine->is_signal)
&& !cfun->machine->is_naked"
"reti"
- [(set_attr "cc" "none")
- (set_attr "length" "1")])
+ [(set_attr "length" "1")])
(define_insn "return_from_naked_epilogue"
[(return)]
@@ -5874,8 +8061,7 @@
&& cfun->machine
&& cfun->machine->is_naked"
""
- [(set_attr "cc" "none")
- (set_attr "length" "0")])
+ [(set_attr "length" "0")])
(define_expand "prologue"
[(const_int 0)]
@@ -5904,7 +8090,7 @@
;; Some instructions resp. instruction sequences available
;; via builtins.
-(define_insn "delay_cycles_1"
+(define_insn_and_split "delay_cycles_1"
[(unspec_volatile [(match_operand:QI 0 "const_int_operand" "n")
(const_int 1)]
UNSPECV_DELAY_CYCLES)
@@ -5912,13 +8098,31 @@
(unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
(clobber (match_scratch:QI 2 "=&d"))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(unspec_volatile [(match_dup 0)
+ (const_int 1)]
+ UNSPECV_DELAY_CYCLES)
+ (set (match_dup 1)
+ (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
+ (clobber (match_dup 2))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*delay_cycles_1"
+ [(unspec_volatile [(match_operand:QI 0 "const_int_operand" "n")
+ (const_int 1)]
+ UNSPECV_DELAY_CYCLES)
+ (set (match_operand:BLK 1 "" "")
+ (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
+ (clobber (match_scratch:QI 2 "=&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"ldi %2,lo8(%0)
1: dec %2
brne 1b"
- [(set_attr "length" "3")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "3")])
-(define_insn "delay_cycles_2"
+(define_insn_and_split "delay_cycles_2"
[(unspec_volatile [(match_operand:HI 0 "const_int_operand" "n,n")
(const_int 2)]
UNSPECV_DELAY_CYCLES)
@@ -5926,14 +8130,32 @@
(unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
(clobber (match_scratch:HI 2 "=&w,&d"))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(unspec_volatile [(match_dup 0)
+ (const_int 2)]
+ UNSPECV_DELAY_CYCLES)
+ (set (match_dup 1)
+ (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
+ (clobber (match_dup 2))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*delay_cycles_2"
+ [(unspec_volatile [(match_operand:HI 0 "const_int_operand" "n,n")
+ (const_int 2)]
+ UNSPECV_DELAY_CYCLES)
+ (set (match_operand:BLK 1 "" "")
+ (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
+ (clobber (match_scratch:HI 2 "=&w,&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"@
ldi %A2,lo8(%0)\;ldi %B2,hi8(%0)\n1: sbiw %A2,1\;brne 1b
ldi %A2,lo8(%0)\;ldi %B2,hi8(%0)\n1: subi %A2,1\;sbci %B2,0\;brne 1b"
[(set_attr "length" "4,5")
- (set_attr "isa" "no_tiny,tiny")
- (set_attr "cc" "clobber")])
+ (set_attr "isa" "no_tiny,tiny")])
-(define_insn "delay_cycles_3"
+(define_insn_and_split "delay_cycles_3"
[(unspec_volatile [(match_operand:SI 0 "const_int_operand" "n")
(const_int 3)]
UNSPECV_DELAY_CYCLES)
@@ -5943,6 +8165,29 @@
(clobber (match_scratch:QI 3 "=&d"))
(clobber (match_scratch:QI 4 "=&d"))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(unspec_volatile [(match_dup 0)
+ (const_int 3)]
+ UNSPECV_DELAY_CYCLES)
+ (set (match_dup 1)
+ (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
+ (clobber (match_dup 2))
+ (clobber (match_dup 3))
+ (clobber (match_dup 4))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*delay_cycles_3"
+ [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "n")
+ (const_int 3)]
+ UNSPECV_DELAY_CYCLES)
+ (set (match_operand:BLK 1 "" "")
+ (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
+ (clobber (match_scratch:QI 2 "=&d"))
+ (clobber (match_scratch:QI 3 "=&d"))
+ (clobber (match_scratch:QI 4 "=&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"ldi %2,lo8(%0)
ldi %3,hi8(%0)
ldi %4,hlo8(%0)
@@ -5950,10 +8195,9 @@
sbci %3,0
sbci %4,0
brne 1b"
- [(set_attr "length" "7")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "7")])
-(define_insn "delay_cycles_4"
+(define_insn_and_split "delay_cycles_4"
[(unspec_volatile [(match_operand:SI 0 "const_int_operand" "n")
(const_int 4)]
UNSPECV_DELAY_CYCLES)
@@ -5964,6 +8208,31 @@
(clobber (match_scratch:QI 4 "=&d"))
(clobber (match_scratch:QI 5 "=&d"))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(unspec_volatile [(match_dup 0)
+ (const_int 4)]
+ UNSPECV_DELAY_CYCLES)
+ (set (match_dup 1)
+ (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
+ (clobber (match_dup 2))
+ (clobber (match_dup 3))
+ (clobber (match_dup 4))
+ (clobber (match_dup 5))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*delay_cycles_4"
+ [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "n")
+ (const_int 4)]
+ UNSPECV_DELAY_CYCLES)
+ (set (match_operand:BLK 1 "" "")
+ (unspec_volatile:BLK [(match_dup 1)] UNSPECV_MEMORY_BARRIER))
+ (clobber (match_scratch:QI 2 "=&d"))
+ (clobber (match_scratch:QI 3 "=&d"))
+ (clobber (match_scratch:QI 4 "=&d"))
+ (clobber (match_scratch:QI 5 "=&d"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"ldi %2,lo8(%0)
ldi %3,hi8(%0)
ldi %4,hlo8(%0)
@@ -5973,24 +8242,39 @@
sbci %4,0
sbci %5,0
brne 1b"
- [(set_attr "length" "9")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "9")])
;; __builtin_avr_insert_bits
-(define_insn "insert_bits"
+(define_insn_and_split "insert_bits"
[(set (match_operand:QI 0 "register_operand" "=r ,d ,r")
(unspec:QI [(match_operand:SI 1 "const_int_operand" "C0f,Cxf,C0f")
(match_operand:QI 2 "register_operand" "r ,r ,r")
(match_operand:QI 3 "nonmemory_operand" "n ,0 ,0")]
UNSPEC_INSERT_BITS))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (unspec:QI [(match_dup 1)
+ (match_dup 2)
+ (match_dup 3)]
+ UNSPEC_INSERT_BITS))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*insert_bits"
+ [(set (match_operand:QI 0 "register_operand" "=r ,d ,r")
+ (unspec:QI [(match_operand:SI 1 "const_int_operand" "C0f,Cxf,C0f")
+ (match_operand:QI 2 "register_operand" "r ,r ,r")
+ (match_operand:QI 3 "nonmemory_operand" "n ,0 ,0")]
+ UNSPEC_INSERT_BITS))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return avr_out_insert_bits (operands, NULL);
}
- [(set_attr "adjust_len" "insert_bits")
- (set_attr "cc" "clobber")])
+ [(set_attr "adjust_len" "insert_bits")])
;; __builtin_avr_flash_segment
@@ -6001,17 +8285,31 @@
[(set (match_operand:QI 0 "register_operand" "")
(subreg:QI (match_operand:PSI 1 "register_operand" "")
2))
- (set (cc0)
- (compare (match_dup 0)
- (const_int 0)))
(set (pc)
- (if_then_else (ge (cc0)
+ (if_then_else (ge (match_dup 0)
(const_int 0))
(label_ref (match_operand 2 "" ""))
(pc)))
(set (match_dup 0)
(const_int -1))])
+(define_insn_and_split "*flash_segment1"
+ [(set (pc)
+ (if_then_else (ge (match_operand:QI 0 "register_operand" "")
+ (const_int 0))
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
+ ""
+ "#"
+ "reload_completed"
+ [(set (reg:CC REG_CC)
+ (compare:CC (match_dup 0) (const_int 0)))
+ (set (pc)
+ (if_then_else (ge (reg:CC REG_CC) (const_int 0))
+ (label_ref (match_dup 1))
+ (pc)))]
+ "")
+
(define_expand "flash_segment"
[(parallel [(match_operand:QI 0 "register_operand" "")
(match_operand:PSI 1 "register_operand" "")])]
@@ -6092,29 +8390,59 @@
operands[2] = gen_reg_rtx (HImode);
})
-(define_insn "*parityhi2.libgcc"
+(define_insn_and_split "*parityhi2.libgcc_split"
[(set (reg:HI 24)
(parity:HI (reg:HI 24)))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:HI 24)
+ (parity:HI (reg:HI 24)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*parityhi2.libgcc"
+ [(set (reg:HI 24)
+ (parity:HI (reg:HI 24)))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __parityhi2"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
-(define_insn "*parityqihi2.libgcc"
+(define_insn_and_split "*parityqihi2.libgcc_split"
[(set (reg:HI 24)
(zero_extend:HI (parity:QI (reg:QI 24))))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:HI 24)
+ (zero_extend:HI (parity:QI (reg:QI 24))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*parityqihi2.libgcc"
+ [(set (reg:HI 24)
+ (zero_extend:HI (parity:QI (reg:QI 24))))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __parityqi2"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
-(define_insn "*paritysihi2.libgcc"
+(define_insn_and_split "*paritysihi2.libgcc_split"
[(set (reg:HI 24)
(truncate:HI (parity:SI (reg:SI 22))))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:HI 24)
+ (truncate:HI (parity:SI (reg:SI 22))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*paritysihi2.libgcc"
+ [(set (reg:HI 24)
+ (truncate:HI (parity:SI (reg:SI 22))))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __paritysi2"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;; Popcount
@@ -6143,29 +8471,59 @@
operands[2] = gen_reg_rtx (HImode);
})
-(define_insn "*popcounthi2.libgcc"
+(define_insn_and_split "*popcounthi2.libgcc_split"
[(set (reg:HI 24)
(popcount:HI (reg:HI 24)))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:HI 24)
+ (popcount:HI (reg:HI 24)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*popcounthi2.libgcc"
+ [(set (reg:HI 24)
+ (popcount:HI (reg:HI 24)))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __popcounthi2"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
-(define_insn "*popcountsi2.libgcc"
+(define_insn_and_split "*popcountsi2.libgcc_split"
[(set (reg:HI 24)
(truncate:HI (popcount:SI (reg:SI 22))))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:HI 24)
+ (truncate:HI (popcount:SI (reg:SI 22))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*popcountsi2.libgcc"
+ [(set (reg:HI 24)
+ (truncate:HI (popcount:SI (reg:SI 22))))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __popcountsi2"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
-(define_insn "*popcountqi2.libgcc"
+(define_insn_and_split "*popcountqi2.libgcc_split"
[(set (reg:QI 24)
(popcount:QI (reg:QI 24)))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:QI 24)
+ (popcount:QI (reg:QI 24)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*popcountqi2.libgcc"
+ [(set (reg:QI 24)
+ (popcount:QI (reg:QI 24)))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __popcountqi2"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
(define_insn_and_split "*popcountqihi2.libgcc"
[(set (reg:HI 24)
@@ -6204,23 +8562,47 @@
operands[2] = gen_reg_rtx (HImode);
})
-(define_insn "*clzhi2.libgcc"
+(define_insn_and_split "*clzhi2.libgcc_split"
[(set (reg:HI 24)
(clz:HI (reg:HI 24)))
(clobber (reg:QI 26))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:HI 24)
+ (clz:HI (reg:HI 24)))
+ (clobber (reg:QI 26))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*clzhi2.libgcc"
+ [(set (reg:HI 24)
+ (clz:HI (reg:HI 24)))
+ (clobber (reg:QI 26))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __clzhi2"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
-(define_insn "*clzsihi2.libgcc"
+(define_insn_and_split "*clzsihi2.libgcc_split"
[(set (reg:HI 24)
(truncate:HI (clz:SI (reg:SI 22))))
(clobber (reg:QI 26))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:HI 24)
+ (truncate:HI (clz:SI (reg:SI 22))))
+ (clobber (reg:QI 26))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*clzsihi2.libgcc"
+ [(set (reg:HI 24)
+ (truncate:HI (clz:SI (reg:SI 22))))
+ (clobber (reg:QI 26))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __clzsi2"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;; Count Trailing Zeros
@@ -6249,24 +8631,50 @@
operands[2] = gen_reg_rtx (HImode);
})
-(define_insn "*ctzhi2.libgcc"
+(define_insn_and_split "*ctzhi2.libgcc_split"
[(set (reg:HI 24)
(ctz:HI (reg:HI 24)))
(clobber (reg:QI 26))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:HI 24)
+ (ctz:HI (reg:HI 24)))
+ (clobber (reg:QI 26))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*ctzhi2.libgcc"
+ [(set (reg:HI 24)
+ (ctz:HI (reg:HI 24)))
+ (clobber (reg:QI 26))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __ctzhi2"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
-(define_insn "*ctzsihi2.libgcc"
+(define_insn_and_split "*ctzsihi2.libgcc_split"
[(set (reg:HI 24)
(truncate:HI (ctz:SI (reg:SI 22))))
(clobber (reg:QI 22))
(clobber (reg:QI 26))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:HI 24)
+ (truncate:HI (ctz:SI (reg:SI 22))))
+ (clobber (reg:QI 22))
+ (clobber (reg:QI 26))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*ctzsihi2.libgcc"
+ [(set (reg:HI 24)
+ (truncate:HI (ctz:SI (reg:SI 22))))
+ (clobber (reg:QI 22))
+ (clobber (reg:QI 26))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __ctzsi2"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;; Find First Set
@@ -6295,24 +8703,50 @@
operands[2] = gen_reg_rtx (HImode);
})
-(define_insn "*ffshi2.libgcc"
+(define_insn_and_split "*ffshi2.libgcc_split"
[(set (reg:HI 24)
(ffs:HI (reg:HI 24)))
(clobber (reg:QI 26))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:HI 24)
+ (ffs:HI (reg:HI 24)))
+ (clobber (reg:QI 26))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*ffshi2.libgcc"
+ [(set (reg:HI 24)
+ (ffs:HI (reg:HI 24)))
+ (clobber (reg:QI 26))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __ffshi2"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
-(define_insn "*ffssihi2.libgcc"
+(define_insn_and_split "*ffssihi2.libgcc_split"
[(set (reg:HI 24)
(truncate:HI (ffs:SI (reg:SI 22))))
(clobber (reg:QI 22))
(clobber (reg:QI 26))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:HI 24)
+ (truncate:HI (ffs:SI (reg:SI 22))))
+ (clobber (reg:QI 22))
+ (clobber (reg:QI 26))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*ffssihi2.libgcc"
+ [(set (reg:HI 24)
+ (truncate:HI (ffs:SI (reg:SI 22))))
+ (clobber (reg:QI 22))
+ (clobber (reg:QI 26))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __ffssi2"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;; Copysign
@@ -6323,8 +8757,7 @@
UNSPEC_COPYSIGN))]
""
"bst %D2,7\;bld %D0,7"
- [(set_attr "length" "2")
- (set_attr "cc" "none")])
+ [(set_attr "length" "2")])
;; Swap Bytes (change byte-endianness)
@@ -6336,13 +8769,23 @@
(set (match_operand:SI 0 "register_operand" "")
(reg:SI 22))])
-(define_insn "*bswapsi2.libgcc"
+(define_insn_and_split "*bswapsi2.libgcc_split"
[(set (reg:SI 22)
(bswap:SI (reg:SI 22)))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:SI 22)
+ (bswap:SI (reg:SI 22)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*bswapsi2.libgcc"
+ [(set (reg:SI 22)
+ (bswap:SI (reg:SI 22)))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"%~call __bswapsi2"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;; CPU instructions
@@ -6369,8 +8812,7 @@
"@
nop
rjmp ."
- [(set_attr "length" "1")
- (set_attr "cc" "none")])
+ [(set_attr "length" "1")])
;; SLEEP
(define_expand "sleep"
@@ -6390,8 +8832,7 @@
(unspec_volatile:BLK [(match_dup 0)] UNSPECV_MEMORY_BARRIER))]
""
"sleep"
- [(set_attr "length" "1")
- (set_attr "cc" "none")])
+ [(set_attr "length" "1")])
;; WDR
(define_expand "wdr"
@@ -6411,8 +8852,7 @@
(unspec_volatile:BLK [(match_dup 0)] UNSPECV_MEMORY_BARRIER))]
""
"wdr"
- [(set_attr "length" "1")
- (set_attr "cc" "none")])
+ [(set_attr "length" "1")])
;; FMUL
(define_expand "fmul"
@@ -6436,27 +8876,55 @@
avr_fix_inputs (operands, 1 << 2, regmask (QImode, 24));
})
-(define_insn "fmul_insn"
+(define_insn_and_split "fmul_insn"
[(set (match_operand:HI 0 "register_operand" "=r")
(unspec:HI [(match_operand:QI 1 "register_operand" "a")
(match_operand:QI 2 "register_operand" "a")]
UNSPEC_FMUL))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (unspec:HI [(match_dup 1)
+ (match_dup 2)]
+ UNSPEC_FMUL))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*fmul_insn"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (unspec:HI [(match_operand:QI 1 "register_operand" "a")
+ (match_operand:QI 2 "register_operand" "a")]
+ UNSPEC_FMUL))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"fmul %1,%2
movw %0,r0
clr __zero_reg__"
- [(set_attr "length" "3")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "3")])
-(define_insn "*fmul.call"
+(define_insn_and_split "*fmul.call_split"
[(set (reg:HI 22)
(unspec:HI [(reg:QI 24)
(reg:QI 25)] UNSPEC_FMUL))
(clobber (reg:HI 24))]
"!AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:HI 22)
+ (unspec:HI [(reg:QI 24)
+ (reg:QI 25)] UNSPEC_FMUL))
+ (clobber (reg:HI 24))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*fmul.call"
+ [(set (reg:HI 22)
+ (unspec:HI [(reg:QI 24)
+ (reg:QI 25)] UNSPEC_FMUL))
+ (clobber (reg:HI 24))
+ (clobber (reg:CC REG_CC))]
+ "!AVR_HAVE_MUL && reload_completed"
"%~call __fmul"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;; FMULS
(define_expand "fmuls"
@@ -6480,27 +8948,55 @@
avr_fix_inputs (operands, 1 << 2, regmask (QImode, 24));
})
-(define_insn "fmuls_insn"
+(define_insn_and_split "fmuls_insn"
[(set (match_operand:HI 0 "register_operand" "=r")
(unspec:HI [(match_operand:QI 1 "register_operand" "a")
(match_operand:QI 2 "register_operand" "a")]
UNSPEC_FMULS))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (unspec:HI [(match_dup 1)
+ (match_dup 2)]
+ UNSPEC_FMULS))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*fmuls_insn"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (unspec:HI [(match_operand:QI 1 "register_operand" "a")
+ (match_operand:QI 2 "register_operand" "a")]
+ UNSPEC_FMULS))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"fmuls %1,%2
movw %0,r0
clr __zero_reg__"
- [(set_attr "length" "3")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "3")])
-(define_insn "*fmuls.call"
+(define_insn_and_split "*fmuls.call_split"
[(set (reg:HI 22)
(unspec:HI [(reg:QI 24)
(reg:QI 25)] UNSPEC_FMULS))
(clobber (reg:HI 24))]
"!AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:HI 22)
+ (unspec:HI [(reg:QI 24)
+ (reg:QI 25)] UNSPEC_FMULS))
+ (clobber (reg:HI 24))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*fmuls.call"
+ [(set (reg:HI 22)
+ (unspec:HI [(reg:QI 24)
+ (reg:QI 25)] UNSPEC_FMULS))
+ (clobber (reg:HI 24))
+ (clobber (reg:CC REG_CC))]
+ "!AVR_HAVE_MUL && reload_completed"
"%~call __fmuls"
- [(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ [(set_attr "type" "xcall")])
;; FMULSU
(define_expand "fmulsu"
@@ -6524,27 +9020,56 @@
avr_fix_inputs (operands, 1 << 2, regmask (QImode, 24));
})
-(define_insn "fmulsu_insn"
+(define_insn_and_split "fmulsu_insn"
[(set (match_operand:HI 0 "register_operand" "=r")
(unspec:HI [(match_operand:QI 1 "register_operand" "a")
(match_operand:QI 2 "register_operand" "a")]
UNSPEC_FMULSU))]
"AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (unspec:HI [(match_dup 1)
+ (match_dup 2)]
+ UNSPEC_FMULSU))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*fmulsu_insn"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (unspec:HI [(match_operand:QI 1 "register_operand" "a")
+ (match_operand:QI 2 "register_operand" "a")]
+ UNSPEC_FMULSU))
+ (clobber (reg:CC REG_CC))]
+ "AVR_HAVE_MUL && reload_completed"
"fmulsu %1,%2
movw %0,r0
clr __zero_reg__"
- [(set_attr "length" "3")
- (set_attr "cc" "clobber")])
+ [(set_attr "length" "3")])
-(define_insn "*fmulsu.call"
+(define_insn_and_split "*fmulsu.call_split"
[(set (reg:HI 22)
(unspec:HI [(reg:QI 24)
(reg:QI 25)] UNSPEC_FMULSU))
(clobber (reg:HI 24))]
"!AVR_HAVE_MUL"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (reg:HI 22)
+ (unspec:HI [(reg:QI 24)
+ (reg:QI 25)] UNSPEC_FMULSU))
+ (clobber (reg:HI 24))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*fmulsu.call"
+ [(set (reg:HI 22)
+ (unspec:HI [(reg:QI 24)
+ (reg:QI 25)] UNSPEC_FMULSU))
+ (clobber (reg:HI 24))
+ (clobber (reg:CC REG_CC))]
+ "!AVR_HAVE_MUL && reload_completed"
"%~call __fmulsu"
[(set_attr "type" "xcall")
- (set_attr "cc" "clobber")])
+ ])
\f
;; Some combiner patterns dealing with bits.
@@ -6561,8 +9086,7 @@
"INTVAL(operands[4]) == exact_log2 (~INTVAL(operands[2]) & GET_MODE_MASK (QImode))
&& INTVAL(operands[4]) == exact_log2 (INTVAL(operands[5]) & GET_MODE_MASK (QImode))"
"bst %3,0\;bld %0,%4"
- [(set_attr "length" "2")
- (set_attr "cc" "none")])
+ [(set_attr "length" "2")])
;; Move bit $3.0 into bit $0.$4
;; Variation of above. Unfortunately, there is no canonicalized representation
@@ -6577,8 +9101,7 @@
(match_operand:QI 4 "const_0_to_7_operand" "n"))))]
"INTVAL(operands[4]) == exact_log2 (~INTVAL(operands[2]) & GET_MODE_MASK (QImode))"
"bst %3,0\;bld %0,%4"
- [(set_attr "length" "2")
- (set_attr "cc" "none")])
+ [(set_attr "length" "2")])
;; Move bit $3.0 into bit $0.0.
;; For bit 0, combiner generates slightly different pattern.
@@ -6590,8 +9113,7 @@
(const_int 1))))]
"0 == exact_log2 (~INTVAL(operands[2]) & GET_MODE_MASK (QImode))"
"bst %3,0\;bld %0,0"
- [(set_attr "length" "2")
- (set_attr "cc" "none")])
+ [(set_attr "length" "2")])
;; Move bit $2.0 into bit $0.7.
;; For bit 7, combiner generates slightly different pattern
@@ -6603,8 +9125,7 @@
(const_int 7))))]
""
"bst %2,0\;bld %0,7"
- [(set_attr "length" "2")
- (set_attr "cc" "none")])
+ [(set_attr "length" "2")])
;; Combiner transforms above four pattern into ZERO_EXTRACT if it sees MEM
;; and input/output match. We provide a special pattern for this, because
@@ -6620,8 +9141,7 @@
cbi %i0,%1
sbi %i0,%1
sbrc %2,0\;sbi %i0,%1\;sbrs %2,0\;cbi %i0,%1"
- [(set_attr "length" "1,1,4")
- (set_attr "cc" "none")])
+ [(set_attr "length" "1,1,4")])
(define_insn "*insv.not.io"
[(set (zero_extract:QI (mem:QI (match_operand 0 "low_io_address_operand" "i"))
@@ -6630,8 +9150,7 @@
(not:QI (match_operand:QI 2 "register_operand" "r")))]
""
"sbrs %2,0\;sbi %i0,%1\;sbrc %2,0\;cbi %i0,%1"
- [(set_attr "length" "4")
- (set_attr "cc" "none")])
+ [(set_attr "length" "4")])
;; The insv expander.
;; We only support 1-bit inserts
@@ -6648,20 +9167,34 @@
;; complicated.
;; Insert bit $2.0 into $0.$1
-(define_insn "*insv.reg"
+(define_insn_and_split "*insv.reg_split"
[(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r,d,d,l,l")
(const_int 1)
(match_operand:QI 1 "const_0_to_7_operand" "n,n,n,n,n"))
(match_operand:QI 2 "nonmemory_operand" "r,L,P,L,P"))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (zero_extract:QI (match_dup 0)
+ (const_int 1)
+ (match_dup 1))
+ (match_dup 2))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*insv.reg"
+ [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r,d,d,l,l")
+ (const_int 1)
+ (match_operand:QI 1 "const_0_to_7_operand" "n,n,n,n,n"))
+ (match_operand:QI 2 "nonmemory_operand" "r,L,P,L,P"))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"@
bst %2,0\;bld %0,%1
andi %0,lo8(~(1<<%1))
ori %0,lo8(1<<%1)
clt\;bld %0,%1
set\;bld %0,%1"
- [(set_attr "length" "2,1,1,2,2")
- (set_attr "cc" "none,set_zn,set_zn,none,none")])
+ [(set_attr "length" "2,1,1,2,2")])
;; Insert bit $2.$3 into $0.$1
(define_insn "*insv.extract"
@@ -6673,8 +9206,7 @@
(match_operand:QI 3 "const_0_to_7_operand" "n")))]
""
"bst %2,%3\;bld %0,%1"
- [(set_attr "length" "2")
- (set_attr "cc" "none")])
+ [(set_attr "length" "2")])
;; Insert bit $2.$3 into $0.$1
(define_insn "*insv.shiftrt"
@@ -6685,67 +9217,128 @@
(match_operand:QI 3 "const_0_to_7_operand" "n")))]
""
"bst %2,%3\;bld %0,%1"
- [(set_attr "length" "2")
- (set_attr "cc" "none")])
+ [(set_attr "length" "2")])
;; Same, but with a NOT inverting the source bit.
;; Insert bit ~$2.$3 into $0.$1
-(define_insn "*insv.not-shiftrt"
+(define_insn_and_split "*insv.not-shiftrt_split"
[(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
(const_int 1)
(match_operand:QI 1 "const_0_to_7_operand" "n"))
(not:QI (any_shiftrt:QI (match_operand:QI 2 "register_operand" "r")
(match_operand:QI 3 "const_0_to_7_operand" "n"))))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (zero_extract:QI (match_dup 0)
+ (const_int 1)
+ (match_dup 1))
+ (not:QI (any_shiftrt:QI (match_dup 2)
+ (match_dup 3))))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*insv.not-shiftrt"
+ [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
+ (const_int 1)
+ (match_operand:QI 1 "const_0_to_7_operand" "n"))
+ (not:QI (any_shiftrt:QI (match_operand:QI 2 "register_operand" "r")
+ (match_operand:QI 3 "const_0_to_7_operand" "n"))))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return avr_out_insert_notbit (insn, operands, NULL_RTX, NULL);
}
- [(set_attr "adjust_len" "insv_notbit")
- (set_attr "cc" "clobber")])
+ [(set_attr "adjust_len" "insv_notbit")])
;; Insert bit ~$2.0 into $0.$1
-(define_insn "*insv.xor1-bit.0"
+(define_insn_and_split "*insv.xor1-bit.0_split"
[(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
(const_int 1)
(match_operand:QI 1 "const_0_to_7_operand" "n"))
(xor:QI (match_operand:QI 2 "register_operand" "r")
(const_int 1)))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (zero_extract:QI (match_dup 0)
+ (const_int 1)
+ (match_dup 1))
+ (xor:QI (match_dup 2)
+ (const_int 1)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*insv.xor1-bit.0"
+ [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
+ (const_int 1)
+ (match_operand:QI 1 "const_0_to_7_operand" "n"))
+ (xor:QI (match_operand:QI 2 "register_operand" "r")
+ (const_int 1)))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return avr_out_insert_notbit (insn, operands, const0_rtx, NULL);
}
- [(set_attr "adjust_len" "insv_notbit_0")
- (set_attr "cc" "clobber")])
+ [(set_attr "adjust_len" "insv_notbit_0")])
;; Insert bit ~$2.0 into $0.$1
-(define_insn "*insv.not-bit.0"
+(define_insn_and_split "*insv.not-bit.0_split"
[(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
(const_int 1)
(match_operand:QI 1 "const_0_to_7_operand" "n"))
(not:QI (match_operand:QI 2 "register_operand" "r")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (zero_extract:QI (match_dup 0)
+ (const_int 1)
+ (match_dup 1))
+ (not:QI (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*insv.not-bit.0"
+ [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
+ (const_int 1)
+ (match_operand:QI 1 "const_0_to_7_operand" "n"))
+ (not:QI (match_operand:QI 2 "register_operand" "r")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return avr_out_insert_notbit (insn, operands, const0_rtx, NULL);
}
- [(set_attr "adjust_len" "insv_notbit_0")
- (set_attr "cc" "clobber")])
+ [(set_attr "adjust_len" "insv_notbit_0")])
;; Insert bit ~$2.7 into $0.$1
-(define_insn "*insv.not-bit.7"
+(define_insn_and_split "*insv.not-bit.7_split"
[(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
(const_int 1)
(match_operand:QI 1 "const_0_to_7_operand" "n"))
(ge:QI (match_operand:QI 2 "register_operand" "r")
(const_int 0)))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (zero_extract:QI (match_dup 0)
+ (const_int 1)
+ (match_dup 1))
+ (ge:QI (match_dup 2)
+ (const_int 0)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*insv.not-bit.7"
+ [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
+ (const_int 1)
+ (match_operand:QI 1 "const_0_to_7_operand" "n"))
+ (ge:QI (match_operand:QI 2 "register_operand" "r")
+ (const_int 0)))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
{
return avr_out_insert_notbit (insn, operands, GEN_INT (7), NULL);
}
- [(set_attr "adjust_len" "insv_notbit_7")
- (set_attr "cc" "clobber")])
+ [(set_attr "adjust_len" "insv_notbit_7")])
;; Insert bit ~$2.$3 into $0.$1
-(define_insn "*insv.xor-extract"
+(define_insn_and_split "*insv.xor-extract_split"
[(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
(const_int 1)
(match_operand:QI 1 "const_0_to_7_operand" "n"))
@@ -6754,11 +9347,31 @@
(const_int 1)
(match_operand:QI 3 "const_0_to_7_operand" "n")))]
"INTVAL (operands[4]) & (1 << INTVAL (operands[3]))"
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (zero_extract:QI (match_dup 0)
+ (const_int 1)
+ (match_dup 1))
+ (any_extract:QI (xor:QI (match_dup 2)
+ (match_dup 4))
+ (const_int 1)
+ (match_dup 3)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*insv.xor-extract"
+ [(set (zero_extract:QI (match_operand:QI 0 "register_operand" "+r")
+ (const_int 1)
+ (match_operand:QI 1 "const_0_to_7_operand" "n"))
+ (any_extract:QI (xor:QI (match_operand:QI 2 "register_operand" "r")
+ (match_operand:QI 4 "const_int_operand" "n"))
+ (const_int 1)
+ (match_operand:QI 3 "const_0_to_7_operand" "n")))
+ (clobber (reg:CC REG_CC))]
+ "INTVAL (operands[4]) & (1 << INTVAL (operands[3])) && reload_completed"
{
return avr_out_insert_notbit (insn, operands, NULL_RTX, NULL);
}
- [(set_attr "adjust_len" "insv_notbit")
- (set_attr "cc" "clobber")])
+ [(set_attr "adjust_len" "insv_notbit")])
\f
;; Some combine patterns that try to fix bad code when a value is composed
@@ -6887,20 +9500,34 @@
(match_operand:QI 2 "const1_operand" "")
(match_operand:QI 3 "const_0_to_7_operand" "")))])
-(define_insn "*extzv"
+(define_insn_and_split "*extzv_split"
[(set (match_operand:QI 0 "register_operand" "=*d,*d,*d,*d,r")
(zero_extract:QI (match_operand:QI 1 "register_operand" "0,r,0,0,r")
(const_int 1)
(match_operand:QI 2 "const_0_to_7_operand" "L,L,P,C04,n")))]
""
+ "#"
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0)
+ (zero_extract:QI (match_dup 1)
+ (const_int 1)
+ (match_dup 2)))
+ (clobber (reg:CC REG_CC))])])
+
+(define_insn "*extzv"
+ [(set (match_operand:QI 0 "register_operand" "=*d,*d,*d,*d,r")
+ (zero_extract:QI (match_operand:QI 1 "register_operand" "0,r,0,0,r")
+ (const_int 1)
+ (match_operand:QI 2 "const_0_to_7_operand" "L,L,P,C04,n")))
+ (clobber (reg:CC REG_CC))]
+ "reload_completed"
"@
andi %0,1
mov %0,%1\;andi %0,1
lsr %0\;andi %0,1
swap %0\;andi %0,1
bst %1,%2\;clr %0\;bld %0,0"
- [(set_attr "length" "1,2,2,2,3")
- (set_attr "cc" "set_zn,set_zn,set_zn,set_zn,clobber")])
+ [(set_attr "length" "1,2,2,2,3")])
(define_insn_and_split "*extzv.qihi1"
[(set (match_operand:HI 0 "register_operand" "=r")
next reply other threads:[~2020-12-12 4:50 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-12 4:49 abebeos [this message]
2020-12-13 18:51 Georg-Johann Lay
2020-12-13 21:49 ` abebeos
2020-12-17 8:45 ` Senthil Kumar Selvaraj
2020-12-17 11:21 ` Segher Boessenkool
2020-12-17 15:07 ` Paul Koning
2020-12-18 9:13 ` Segher Boessenkool
2020-12-18 17:13 ` Georg-Johann Lay
2020-12-18 18:28 ` Segher Boessenkool
2020-12-18 21:38 ` abebeos
2021-01-05 13:54 ` Senthil Kumar Selvaraj
2021-01-05 19:06 ` Paul Koning
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