From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 65348 invoked by alias); 10 Jun 2015 09:13:38 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 65338 invoked by uid 89); 10 Jun 2015 09:13:36 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-oi0-f49.google.com Received: from mail-oi0-f49.google.com (HELO mail-oi0-f49.google.com) (209.85.218.49) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Wed, 10 Jun 2015 09:13:35 +0000 Received: by oihd6 with SMTP id d6so28157989oih.2 for ; Wed, 10 Jun 2015 02:13:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=yJJ6BHbPqCVHcMoNgTSDjND7GpFo38FROpaShiJpu48=; b=FbcpcAQEtmGpBR6k9qkqVV/koVFAsdrMjAmpbCo1Q5WBoj5KvGPkWXPHv4yu7YlqzQ hwFkBraBN1vGtwk1QiViTySTibZiOU9zPn9ujr03XBNZjYZejkwOS0udAg5YENvK/91K fuUwdXVqqST07DaJ8K10AUF1d5bCk0SvVe1jMGR3F6PmbyPT7JfDoUbXdK6klABwU+ZZ 21GcOaje6GgB/EwIN+1jRekOmBEVCE5JH0L7ZnlFDampNVmE1Dy2SY4+bI4RFJJ7jl7X S+WVZ0ehzDCF/jlVqPaPEnr6FgYQWaa0rRHKkIaPZg4zMZIxxlfZDO+pYqnsyDN38NDo P6CQ== X-Gm-Message-State: ALoCoQlusULrkoaMW6rKfRY2Vcumg1TXvypXCdia5xUNaAoCn8FNgIYQx2+mJChI3GnH9pzeIBqt MIME-Version: 1.0 X-Received: by 10.60.115.1 with SMTP id jk1mr2066989oeb.2.1433927613410; Wed, 10 Jun 2015 02:13:33 -0700 (PDT) Received: by 10.202.87.77 with HTTP; Wed, 10 Jun 2015 02:13:33 -0700 (PDT) In-Reply-To: <5575615E.30509@arm.com> References: <5575615E.30509@arm.com> Date: Wed, 10 Jun 2015 09:35:00 -0000 Message-ID: Subject: Re: [PATCH] [AArch64] PR63870 Improve error messages for NEON single lane memory access intrinsics From: Charles Baylis To: Alan Lawrence Cc: GCC Patches , Tejas Belagod , Marcus Shawcroft , Richard Earnshaw Content-Type: text/plain; charset=UTF-8 X-IsSubscribed: yes X-SW-Source: 2015-06/txt/msg00739.txt.bz2 On 8 June 2015 at 10:33, Alan Lawrence wrote: > Thanks for working on this! > > I'd been fiddling around with a patch with some similar elements to this, > but many trials with union types, subregs, etc., all worsened the register > allocation and led to more unnecessary shuffling / moves. Kugan has been looking into this at Linaro. We should avoid duplicating effort here. > The only real > thing I tried which you don't do here, was to introduce a set_dreg expander > to clean up some of those macro definitions in arm_neon.h. That could easily > follow in a separate patch if desired! I'd prefer that to be a separate step. > So your patch looks good to me. > > A couple of style nits: > > --- a/gcc/config/aarch64/aarch64-builtins.c > +++ b/gcc/config/aarch64/aarch64-builtins.c > @@ -128,7 +128,9 @@ enum aarch64_type_qualifiers > /* Polynomial types. */ > qualifier_poly = 0x100, > /* Lane indices - must be in range, and flipped for bigendian. */ > - qualifier_lane_index = 0x200 > + qualifier_lane_index = 0x200, > + /* Lane indices for single lane structure loads and stores */ > + qualifier_struct_load_store_lane_index = 0x400 > }; > > should be ...'loads and stores. */' > > also the dg-error messages in the testsuite, do not need to be on the same > line as the statement generating the error, because the trailing 0 tells dg > that the position/line number doesn't matter (i.e. dg should allow the error > to be reported at any line); so these could be brought under 80 chars. OK, thanks. I'll re-spin once I've tested on big endian. > Oh, have you tested bigendian? I have started a bigendian build on our validation infrastructure here. Thanks for the review Charles