From: Charles Baylis <charles.baylis@linaro.org>
To: Alan Lawrence <alan.lawrence@arm.com>
Cc: Richard Earnshaw <rearnsha@arm.com>,
"gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
Marcus Shawcroft <marcus.shawcroft@arm.com>,
Tejas Belagod <tejas.belagod@arm.com>
Subject: Re: [PATCH 1/4] vldN_lane error message enhancements (Q registers)
Date: Tue, 14 Apr 2015 16:30:00 -0000 [thread overview]
Message-ID: <CADnVucD0-bgBhk3OGnBtm8RK1Xy9Up+rN8YDTQq0TDEBuvNQ7Q@mail.gmail.com> (raw)
In-Reply-To: <CAOckXuMSZyHU80A6-VjSzZ7bHrtRikTKwn-45DZ9oPPuRX_0HQ@mail.gmail.com>
On 14 April 2015 at 14:45, Alan Lawrence <alan.lawrence@arm.com> wrote:
> Assuming/hoping that this patch is proposed for new stage 1 ;),
IIRC the approach of using __builtin_aarch64_im_lane_boundsi doesn't
work (results in double error messages), and so the patch needs to be
rewritten to avoid it. However, thanks for your comments, I'll reflect
those in the next version of the patch.
Thanks
Charles
next prev parent reply other threads:[~2015-04-14 16:30 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-09 15:28 [PATCH 0/4] [AARCH64,SIMD] PR63870 Improve error messages for single lane load/store charles.baylis
2014-12-09 15:28 ` [PATCH 3/4] vstN_lane error message enhancements (Q register) charles.baylis
2014-12-09 15:28 ` [PATCH 2/4] vldN_lane error message enhancements (D registers) charles.baylis
2014-12-10 9:23 ` Christophe Lyon
2014-12-10 10:26 ` Alan Lawrence
2014-12-09 15:28 ` [PATCH 1/4] vldN_lane error message enhancements (Q registers) charles.baylis
[not found] ` <CAOckXuMSZyHU80A6-VjSzZ7bHrtRikTKwn-45DZ9oPPuRX_0HQ@mail.gmail.com>
2015-04-14 16:30 ` Charles Baylis [this message]
2015-04-14 17:20 ` Alan Lawrence
2014-12-09 15:28 ` [PATCH 4/4] vstN_lane error message enhancements (D registers) charles.baylis
2014-12-10 10:34 ` [PATCH 0/4] [AARCH64,SIMD] PR63870 Improve error messages for single lane load/store Alan Lawrence
2014-12-12 14:12 ` Charles Baylis
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